JP2013197533A - Memory device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory device which has low wiring resistance and enables miniaturization, and to provide a manufacturing method of the memory device.SOLUTION: A memory device 1 includes: a substrate 10; first lower layer wiring 34 which is cyclically arranged on the substrate 10 and includes tungsten or molybdenum; second lower wiring 36 which is placed at the same height as the first lower layer wiring 34 with respect to an upper surface of the substrate 10 and includes tungsten or molybdenum; and upper layer wiring 46 which is placed at a region located immediately above the second lower wiring 36, is connected with the second lower wiring 36, and includes copper or aluminum. A lower surface of the upper layer wiring 46 is positioned at the same height as or lower than an upper surface of the second lower layer wiring 36.

Description

  Embodiments described herein relate generally to a storage device and a method for manufacturing the same.

  Conventionally, a copper wiring formed by a damascene method is used for a bit line of a NAND flash memory. However, if further miniaturization of memory cells is required in the future, copper embedding becomes difficult, and there is a concern that bit lines may be open. On the other hand, although it is conceivable to form the bit line by RIE (reactive ion etching), it is necessary to use a refractory metal such as tungsten instead of copper as a wiring material. In this case, since tungsten wiring is used also in the peripheral circuit region, the wiring resistance increases and the operation speed of the peripheral circuit decreases.

JP 2009-231621 A

  An object of the present invention is to provide a memory device that has low wiring resistance and can be miniaturized, and a method for manufacturing the same.

  The memory device according to the embodiment includes a substrate, a first lower layer wiring periodically arranged on the substrate and containing tungsten or molybdenum, and the same height as the first lower layer wiring with respect to the upper surface of the substrate. And a second lower layer wiring including tungsten or molybdenum, and an upper layer wiring disposed immediately above the second lower layer wiring, connected to the second lower layer wiring, and including copper or aluminum. . The lower surface of the upper layer wiring is located at the same height as or below the upper surface of the second lower layer wiring.

  A method for manufacturing a memory device according to an embodiment includes a step of forming an interlayer insulating film on a substrate, a step of forming a metal film made of tungsten or molybdenum on the interlayer insulating film, and etching the metal film. And forming a first lower layer wiring periodically arranged, forming a second lower layer wiring, forming an insulating film so as to cover the second lower layer wiring, A step of forming a groove reaching the second lower layer wiring in the insulating film; and a step of forming an upper layer wiring by embedding copper or aluminum in the groove.

(A)-(c) is sectional drawing which illustrates the memory | storage device which concerns on 1st Embodiment. 6 is a process plan view illustrating the method for manufacturing the storage device according to the first embodiment; FIG. 10A to 10C are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. 10A to 10C are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. 10A to 10C are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. 10A to 10C are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. 10A to 10C are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. 10A to 10C are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. 10A to 10C are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. 10A to 10C are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. (A) And (b) is a process top view which illustrates the manufacturing method of the memory | storage device which concerns on 1st Embodiment. 10A to 10C are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. 10A to 10C are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. (A) And (b) is a process top view which illustrates the manufacturing method of the memory | storage device which concerns on 1st Embodiment. 10A to 10C are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. 10A to 10C are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. 10A to 10C are process cross-sectional views illustrating the method for manufacturing the memory device according to the first embodiment. (A)-(c) is sectional drawing which illustrates the memory | storage device which concerns on the modification of 1st Embodiment. (A) And (b) is sectional drawing which illustrates the memory | storage device which concerns on 2nd Embodiment.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the first embodiment will be described.
1A to 1C are cross-sectional views illustrating the memory device according to this embodiment. FIGS. 1A and 1B show cross sections orthogonal to each other in the memory region, and FIG. The circuit area is shown.

  As shown in FIGS. 1A to 1C, the storage device 1 according to the present embodiment is a NAND flash memory. In the storage device 1, a memory region Rm in which memory cells for storing information are provided and a peripheral circuit region Rc in which peripheral circuits for inputting / outputting information to / from the memory cells are set.

  In the storage device 1, a silicon substrate 10 is provided. In the memory region Rm, a plurality of element isolation insulators (STI: shallow trench isolation) 11 extending in one direction are formed in the upper layer portion of the silicon substrate 10, and the upper layers of the silicon substrate 10 are formed by the element isolation insulator 11. The portion is separated into a plurality of active areas (AA) 12 extending in one direction. On the other hand, in the peripheral circuit region Rc, the source / drain region 14 and the channel region 15 of the transistor 13 constituting the peripheral circuit are formed in the upper layer portion of the silicon substrate 10.

  In the memory region Rm, floating gate electrodes (FG) 21 are arranged in a matrix on the silicon substrate 10, and a plurality of control gate electrodes (CG) 22 extending in one direction are provided on the floating gate electrode 21. It has been. The direction in which the control gate electrode 22 extends (hereinafter referred to as “CG direction”) is a direction orthogonal to the direction in which the active area 12 extends (hereinafter referred to as “AA direction”). The floating gate electrode 21 is disposed for each closest portion between the active area 12 and the control gate electrode 22. Select gate electrodes (SG) 23 extending in the CG direction are provided on both sides of the group consisting of the plurality of floating gate electrodes 21 and the plurality of control gate electrodes 22. In FIG. 1B, only three control gate electrodes 22 are shown between a pair of select gate electrodes 23 for the sake of simplicity. The same applies to other figures described later. However, a larger number of control gate electrodes 22 may be provided between the select gate electrodes 23. On the other hand, in the peripheral circuit region Rc, the gate electrode 24 of the transistor 13 is provided on the silicon substrate 10.

  On the silicon substrate 10, an interlayer insulating film 25 made of, for example, silicon oxide is provided so as to cover the floating gate electrode 21, the control gate electrode 22, the selection gate electrode 23, and the gate electrode 24. In the memory region Rm, a bit line contact 26 is embedded so as to penetrate the interlayer insulating film 25 and is connected to the active area 12. A source line 27 is buried above the interlayer insulating film 25. The source line 27 extends in the CG direction and is connected to the active area 12 via a source line contact 28. On the other hand, in the peripheral circuit region Rc, an SD wiring 29 is buried above the interlayer insulating film 25 and connected to the source / drain region 14 via the SD contact 30.

  An interlayer insulating film 31 made of, for example, silicon oxide is provided on the interlayer insulating film 25. Vias 32 and 33 are provided in the interlayer insulating film 31. The via 32 is connected to the bit line contact 26, and the via 33 is connected to the SD wiring 29.

  In the memory region Rm, a plurality of bit lines 34 (first lower layer wirings) are periodically provided on the interlayer insulating film 31. Each bit line 34 is disposed immediately above each active area 12 and extends in the AA direction. The bit lines 34 are critical wirings arranged in the shortest cycle in the storage device 1. In the bit line 34, a wiring body 34a made of tungsten (W) and a barrier film 34b covering the lower surface of the wiring body 34a are provided. The barrier film 34b is, for example, a two-layer film in which a titanium layer and a titanium nitride layer are stacked. The bit line 34 is connected to the active area 12 through the via 32 and the bit line contact 26.

  On the other hand, in the peripheral circuit region Rc, a plurality of wirings 36 (second lower layer wirings) are provided. The wirings 36 are arranged at the same height as the bit lines 34 with respect to the upper surface 10a of the silicon substrate 10 and are periodically arranged. The arrangement period of the wirings 36 is equal to the arrangement period of the bit lines 34. In the wiring 36, a wiring body 36a made of tungsten (W) and a barrier film 36b covering the lower surface of the wiring body 36a are provided. The barrier film 36b is, for example, a two-layer film in which a titanium layer and a titanium nitride layer are stacked. The wiring 36 is connected to the SD wiring 29 through the via 33.

  A silicon nitride film 38 is provided on the upper surface of the bit line 34. An interlayer insulating film 41 made of, for example, silicon oxide is provided so as to cover the bit line 34, the silicon nitride film 38, and the wiring 36. An air gap 42 extending in the CG direction is formed between the stacked bodies including the bit line 34 and the silicon nitride film 38 in the interlayer insulating film 41.

  A silicon nitride film 43 is provided on the interlayer insulating film 41, and an interlayer insulating film 44 made of, for example, silicon oxide is provided thereon. In the peripheral circuit region Rc, a wiring 46 (upper layer wiring) is provided so as to penetrate the interlayer insulating film 44 and the silicon nitride film 43 and be embedded in the upper part of the interlayer insulating film 41. In the wiring 46, a wiring body 46a made of copper (Cu) and a barrier film 46b covering the side surface and the lower surface of the wiring body 46a are provided. The barrier film 46b is, for example, a two-layer film in which a titanium layer and a titanium nitride layer are stacked. The wiring 46 is thicker than the wiring 36, extends in the same direction as the wiring 36, and is disposed in a region including a region immediately above the plurality of wirings 36, and a lower surface thereof is in contact with an upper surface of the plurality of wirings 36. . Thereby, the wiring 46 is connected to the plurality of wirings 36. The lower surface 46c of the wiring 46 is located at the same height as or lower than the wiring 36 and the upper surface 36c. In the memory region Rm, no wiring in the same layer as the wiring 46 is provided.

  A barrier film 47 made of, for example, silicon carbonitride (SiCN) is provided in a region including the region immediately above the wiring 46 on the interlayer insulating film 44. On the barrier film 47, a via (not shown) made of, for example, aluminum and an uppermost layer wiring (not shown) may be provided.

Next, a method for manufacturing the storage device according to the present embodiment will be described.
FIG. 2 is a process plan view illustrating the method for manufacturing the memory device according to this embodiment, showing a memory area,
3 to 10 are process cross-sectional views illustrating the method for manufacturing the memory device according to this embodiment.
FIG. 11 is a process plan view illustrating the method for manufacturing the memory device according to this embodiment.
12 and 13 are process plan views illustrating the method for manufacturing the memory device according to this embodiment.
FIG. 14 is a process plan view illustrating the method for manufacturing the memory device according to this embodiment.
15 to 17 are process cross-sectional views illustrating the method for manufacturing the memory device according to this embodiment.

3A is a cross-sectional view taken along line AA ′ shown in FIG. 2, and FIG. 3B is a cross-sectional view taken along line BB ′ shown in FIG.
3 to 10, 12, 13, and 15 to 17, (a) and (b) show cross sections orthogonal to each other in the memory region, and (c) shows the peripheral circuit region. Indicates.
Further, in FIGS. 11 and 14, (a) in each figure shows a memory area, and (b) shows a peripheral circuit area.

  First, as shown in FIGS. 2 and 3A to 3C, a silicon substrate 10 is prepared. Next, a tunnel film is formed on the silicon substrate 10 in the memory region Rm, and a gate insulating film is formed on the silicon substrate 10 in the peripheral circuit region Rc. Next, a conductive film is formed and selectively removed to form a lower portion of the floating gate electrode 21 and the selection gate electrode 23 extending in the AA direction in the memory region Rm, and a gate in the peripheral circuit region Rc. A lower portion of the electrode 24 is formed. Next, in the memory region Rm, a portion of the upper layer portion of the silicon substrate 10 that is not covered with the floating gate electrode 21 is selectively removed to form a trench, and silicon oxide is buried in the trench, thereby AA. An element isolation insulator 11 extending in the direction is formed. At this time, a portion between the element isolation insulators 11 in the silicon substrate 10 becomes an active area 12.

  Next, an interelectrode insulating film is formed, and a conductive film is formed thereon. Next, the conductive film, the interelectrode insulating film, and the floating gate electrode 21 are selectively removed. Thereby, in the memory region Rm, a plurality of control gate electrodes 22 extending in the CG direction and an upper portion of the selection gate electrode 23 are formed. The floating gate electrodes 21 are divided along the AA direction and arranged in a matrix. On the other hand, the upper portion of the gate electrode 24 is formed in the peripheral circuit region Rc.

  Next, impurities are implanted using the control gate electrode 22, the selection gate electrode 23, and the gate electrode 24 as a mask. Thereby, in the memory region Rm, an impurity diffusion region (not shown) is formed in a region excluding the region immediately below the control gate electrode 22 and the region directly below the selection gate electrode 23 in the active area 12. On the other hand, in the peripheral circuit region Rc, source / drain regions 14 are formed on both sides of the region immediately below the gate electrode 24 in the upper layer portion of the silicon substrate 10. At this time, the region immediately below the gate electrode 24 in the upper layer portion of the silicon substrate 10 becomes the channel region 15.

  Next, silicon oxide is deposited on the entire surface, and a planarization process such as CMP (chemical mechanical polishing) is performed, so that the floating gate electrode 21, the control gate electrode 22, the selection gate electrode 23, and the gate are formed. An interlayer insulating film 25 that covers the electrode 24 is formed. 3 and the subsequent drawings, the tunnel film, the gate insulating film, and the interelectrode insulating film described above are shown as a part of the interlayer insulating film 25.

  Next, a resist film (not shown) is formed on the interlayer insulating film 25 and patterned by a lithography method to form a resist pattern (not shown). Next, anisotropic etching such as RIE is performed using this resist pattern as a mask. Thus, contact holes 71 to 73 penetrating the interlayer insulating film 25 are formed in the interlayer insulating film 25. The contact holes 71 are formed in a staggered position so as to reach each active area 12, the contact holes 72 are formed in a line extending in the CG direction so as to reach a plurality of active areas 12, and the contact holes 73 are It is formed at a position reaching the source / drain region 14. Thereafter, the resist pattern is removed.

  Next, as shown in FIGS. 4A to 4C, a resist film is formed and patterned by a lithography method to form a resist pattern (not shown), and this is used as a mask to form an anisotropy such as RIE. Etching is performed to form trenches 75 to 77 above the interlayer insulating film 25. The trench 75 is formed so as to extend in the CG direction in the region where the control gate electrode 22 is disposed, and the trench 76 is formed so as to extend in the CG direction in a region including the region immediately above the contact hole 72. The trench 77 is formed to extend in the CG direction in a region including the region directly above the contact hole 73 and communicates with the contact hole 73. Thereafter, the resist pattern is removed.

  Next, as shown in FIGS. 5A to 5C, a barrier film (not shown) is formed as necessary, and then tungsten is deposited. Next, planarization processing such as CMP is performed on tungsten using the interlayer insulating film 25 as a stopper. Thereby, tungsten is buried in the contact holes 71 to 73 and the trenches 75 to 77, and the tungsten is removed from the upper surface of the interlayer insulating film 25. As a result, the bit line contact 26 is embedded in the contact hole 71, the source line contact 28 is embedded in the contact hole 72, the SD contact 30 is embedded in the contact hole 73, and each in the trench 75 and the trench 76. The source line 27 is embedded, and the SD wiring 29 is embedded in the trench 77.

  Next, as shown in FIGS. 6A to 6C, an interlayer insulating film 31 is formed by depositing silicon oxide on the interlayer insulating film 25 and performing a planarization process such as CMP. Next, a resist film is formed and patterned by a lithography method to form a resist pattern (not shown). By using this as a mask, anisotropic etching such as RIE is performed, whereby via holes 78 and 79 is formed. The via hole 78 is formed so as to reach the bit line contact 26, and the via hole 79 is formed so as to reach the SD wiring 29. Thereafter, the resist pattern is removed.

  Next, as shown in FIGS. 7A to 7C, a barrier film (not shown) is formed as necessary, and then tungsten is deposited. Next, planarization processing such as CMP is performed on tungsten using the interlayer insulating film 31 as a stopper. As a result, tungsten is buried in the via holes 78 and 79 and the tungsten is removed from the upper surface of the interlayer insulating film 31. As a result, the via 32 is embedded in the via hole 78 and the via 33 is embedded in the via hole 79. The via 32 is connected to the bit line contact 26, and the via 33 is connected to the SD wiring 29.

Next, as shown in FIGS. 8A to 8C, for example, a titanium layer and a titanium nitride layer are deposited on the interlayer insulating film 31 to form a barrier film 81. Next, tungsten is deposited by, for example, a CVD method to form a tungsten film 82 made of tungsten. Next, a silicon nitride film 83 is formed, and a silicon oxide film 84 is formed by a CVD (chemical vapor deposition) method using TEOS (tetraethoxysilane: Si (OC ₂ H ₅ ) ₄ ) as a raw material. A silicon film 85 is formed, and a silicon oxide film 86 (core material film) is formed by a CVD method using TEOS as a raw material. The silicon nitride film 83, the silicon oxide film 84, the amorphous silicon film 85, and the silicon oxide film 86 constitute a laminated mask film as a whole.

  Next, as shown in FIGS. 9A to 9C, a resist film is formed and exposed using, for example, EUV (extreme ultraviolet) light generated by a DPP (Discharged Produced Plasma) method. And then develop. Thereby, a resist pattern (not shown) is formed. Next, by performing anisotropic etching such as RIE using this resist pattern as a mask, the silicon oxide film 86 is patterned in a line and space pattern. As a result, a plurality of core members 86a are formed in both the memory region Rm and the peripheral circuit region Rc. In the memory region Rm, the core member 86a is formed so as to extend in the AA direction and have an arrangement period twice as long as the arrangement period of the active area 12. On the other hand, also in the peripheral circuit region Rc, the core member 86a is formed so that the arrangement cycle is twice the arrangement cycle of the active area 12. Thereafter, the resist pattern is removed. Next, the core material 86a is slimmed down.

  Next, as shown in FIGS. 10A to 10C, a silicon nitride film (not shown) is formed on the entire surface. Next, the silicon nitride film is subjected to anisotropic etching such as RIE. As a result, the portion of the silicon nitride film deposited on the upper surface of the amorphous silicon film 85 and the upper surface of the core material 86a (see FIG. 9) is removed, and the portion deposited on the side surface of the core material 86a is removed. Remains. As a result, a side wall 87 made of silicon nitride is formed on the side surface of the core material 86a. The side wall 87 is formed in a loop shape so as to go around both ends of the line-shaped core member 86a. Next, the core material 86a is removed by wet etching.

  Next, as shown in FIGS. 11A and 11B, a resist film is formed on the amorphous silicon film 85 and patterned by a lithography method. Thereby, a resist pattern 88 is formed so as to cover a part of the side wall 87. In the memory region Rm, the resist pattern 88 is formed, for example, in a strip shape extending in the CG direction so as to cover a portion other than the loop portion in the side wall 87. On the other hand, in the peripheral circuit region Rc, the resist pattern 88 is formed, for example, in a rectangular shape in a region including the region immediately above the via 33.

  Next, anisotropic etching such as RIE is performed using the resist pattern 88 as a mask to remove a portion of the side wall 87 that is not covered with the resist pattern 88. Thereby, in the memory region Rm, the loop portions at both ends of the side wall 87 are removed. That is, a loop cut is performed. On the other hand, in the peripheral circuit region Rc, the side wall 87 remains in the region immediately above the via 33 and in the vicinity thereof.

  Next, as shown in FIGS. 12A to 12C, the amorphous silicon film 85 and the silicon oxide film 84 are selected by performing anisotropic etching such as RIE using the side wall 87 (see FIG. 11) as a mask. To remove. Next, the silicon nitride film 83 is selectively removed by performing isotropic etching such as wet etching using the patterned amorphous silicon film 85 and silicon oxide film 84 as a mask. At this time, the side wall 87 made of silicon nitride is also removed.

  Next, as shown in FIGS. 13A to 13C and FIGS. 14A and 14B, from the patterned silicon nitride film 83, silicon oxide film 84, and amorphous silicon film 85 (see FIG. 12). An anisotropic etching such as RIE is performed using the laminated mask as a mask. Thereby, the tungsten film 82 and the barrier film 81 are selectively removed, and the pattern of the side wall 87 (see FIG. 11) is transferred. As a result, in the memory region Rm, a plurality of bit lines 34 extending in the AA direction and periodically arranged are formed. Each bit line 34 is connected to each via 32. On the other hand, in the peripheral circuit region Rc, a plurality of wirings 36 that are periodically arranged at the same cycle as that of the bit lines 34 are formed. The plurality of wirings 36 are commonly connected to the via 33. At this time, the tungsten film 82 becomes the wiring bodies 34a and 36a, and the barrier film 81 becomes the barrier films 34b and 36b. Further, in the etching process, the upper part of the laminated mask disappears. The remaining silicon nitride film 83 becomes the silicon nitride film 38. The bit line 34 and the wiring 36 are critical wirings having the shortest arrangement period among the wirings of the storage device 1.

  Next, as shown in FIGS. 15A to 15C, silicon oxide is deposited by a CVD method using TEOS as a raw material, and a planarization process such as CMP is performed on the upper surface, whereby the bit lines 34 and An interlayer insulating film 41 is formed so as to cover the wiring 36. At this time, the air gap 42 is formed so that silicon oxide is not completely filled between the stacked bodies formed of the bit line 34 and the silicon nitride film 38.

  Next, silicon nitride is deposited on the interlayer insulating film 41 to form a silicon nitride film 43. Next, an interlayer insulating film 44 is formed by depositing silicon oxide by a CVD method using TEOS as a raw material and performing a planarization process such as CMP. Next, a resist film is formed on the interlayer insulating film 44 and patterned by a lithography method to form a resist pattern (not shown). By using this as a mask, anisotropic etching such as RIE is performed, thereby interlayer insulating. The film 44 is selectively removed. At this time, the silicon nitride film 43 serves as a stopper, and the etching is temporarily stopped. Thereafter, anisotropic etching such as RIE is further performed to selectively remove the silicon nitride film 43, the interlayer insulating film 41, and the silicon nitride film 38. As a result, a groove 90 reaching the wiring 36 is formed in the peripheral circuit region Rc. The bottom surface 90a of the groove 90 is flat, for example, and the upper surface 36c of the wiring 36 is exposed. On the other hand, the entire memory region Rm is covered with a resist pattern, and no groove or the like is formed. Thereafter, the resist pattern is removed.

  Next, as shown in FIGS. 16A to 16C, for example, a titanium layer is deposited, and a titanium nitride layer is deposited to form a (Ti / TiN) bilayer film 91 on the entire surface. At this time, the (Ti / TiN) bilayer film 91 is also formed on the inner surface of the groove 90. Next, copper is deposited on the entire surface to form a copper film 92 on the (Ti / TiN) bilayer film 91. At this time, the copper film 92 is also embedded in the groove 90.

  Next, as shown in FIGS. 17A to 17C, planarization processing such as CMP is performed using the interlayer insulating film 44 as a stopper. As a result, portions of the copper film 92 and the (Ti / TiN) bilayer film 91 deposited on the upper surface of the interlayer insulating film 44 are removed, and the portion deposited in the trench 90 remains. As a result, the wiring 46 is formed in the groove 90. At this time, the (Ti / TiN) bilayer film 91 becomes the barrier film 46b, and the copper film 92 becomes the wiring body 46a. That is, in the present embodiment, the relatively thin bit line 34 and the wiring 36 are formed by the RIE method using the sidewall process, and the relatively thick wiring 46 is formed by the damascene method.

  Next, as shown in FIGS. 1A to 1C, silicon carbonitride is deposited on the entire surface of the interlayer insulating film 44 and the wiring 46 to form a barrier film 47. Thereafter, an interlayer insulating film (not shown) is formed so as to cover the barrier film 47. In the interlayer insulating film, vias (not shown) and uppermost layer wirings (not shown) may be formed by reflowing aluminum. In this way, the storage device 1 according to this embodiment is manufactured.

Next, the effect of this embodiment is demonstrated.
In the present embodiment, the wiring body 34a of the bit line 34 is formed of tungsten. Therefore, the bit line 34 can be processed by etching such as RIE. Thereby, compared with the case where the bit line 34 is formed by the damascene method, the bit line 34 can be made thinner and the arrangement period can be shortened. For example, the width of the bit line 34 can be less than 20 nm. As a result, the storage device 1 can be highly integrated.

  On the other hand, in the present embodiment, the wiring 46 is provided, and the wiring 46 is connected to the SD wiring 29 via the wiring 36 and the via 33. Thereby, the wiring 46 and the wiring 36 become the shunt wiring of the SD wiring 29, and the effective wiring resistance of the SD wiring 29 can be reduced. As a result, the peripheral circuit can be speeded up as compared with the case where the wiring 46 is not provided.

  Further, since the wiring 46 is arranged in an upper layer than the SD wiring 29, it can be formed thicker than the SD wiring 29. Thereby, the resistance of the wiring 46 can be reduced, and the wiring 46 can be formed by a damascene method. Therefore, copper having a low resistivity can be used as the material of the wiring 46, and the resistance of the wiring 46 can be further reduced.

  Further, in the present embodiment, the via 33 is formed in the same process as the via 32 and the wiring 36 is formed in the same process as the bit line 34. Therefore, in order to form the via 33 and the wiring 36, the number of processes is increased. There is no increase. In addition, since no connecting member such as a via is provided between the wiring 46 and the wiring 36, the resistance between the two wirings is low, and a process for forming such a connecting member is unnecessary. Thereby, an increase in the number of processes due to the provision of the wiring 46 can be suppressed, and the manufacturing cost of the memory device 1 can be suppressed. On the other hand, when the wiring 46 is formed as a normal upper layer wiring, it is necessary to form a via for connecting the wiring 46 to the wiring 36, which increases the wiring resistance and increases the wiring layer by one layer. , Manufacturing costs increase.

  Furthermore, in this embodiment, since the bit line 34 is formed by a sidewall process, the bit line 34 can be further miniaturized. For this reason, the storage device 1 can be further highly integrated. Further, since the wiring 36 is formed in the same process as the bit line 34, the wiring 36 is also formed by a sidewall process, and each wiring 36 is thinned. Since a plurality of wirings 36 are connected in common, the wiring resistance does not increase.

Next, a modification of this embodiment will be described.
18A and 18B are cross-sectional views illustrating a memory device according to this modification. FIGS. 18A and 18B show cross sections orthogonal to each other in the memory area, and FIG. 18C shows a peripheral circuit area.
As shown in FIGS. 18A to 18C, the storage device 1a according to the present modification is lower in the lower surface of the wiring 46 than the storage device 1 according to the first embodiment described above (see FIG. 1). The difference is that 46 c is located below the upper surface 36 c of the wiring 36.

In such a configuration, in the step shown in FIG. 15, the etching for forming the groove 90 is continued for a while after the upper surface 36c of the wiring 36 is exposed, and the bottom surface 90a of the groove 90 is located below the upper surface 36c of the wiring 36. This can be realized by placing the switch in the position.
According to this modified example, in addition to the upper surface of the wiring 36, a part of the side surface comes into contact with the wiring 46, and the contact area between the wiring 36 and the wiring 46 increases, so that the contact resistance decreases. Configurations, manufacturing methods, and operational effects other than those described above in the present modification are the same as those in the first embodiment described above.

Next, a second embodiment will be described.
FIG. 19 is a schematic cross-sectional view illustrating the memory device according to this embodiment. FIG. 19A shows a memory area, and FIG. 19B shows a peripheral circuit area.
In FIGS. 19A and 19B, for convenience of illustration, the insulating portion is omitted, and only the conductive portion is schematically illustrated.
As shown in FIGS. 19A and 19B, in the storage device 2 according to the present embodiment, the silicon substrate 10 is provided, and the memory region Rm and the peripheral circuit region Rc are set.

  In the memory region Rm, a plurality of memory cells 50 are provided, and each memory cell 50 is provided with, for example, one transistor 51 and one memory element 52. In the transistor 51, a gate electrode 53 and contacts 54 and 55 connected to a pair of source / drain regions (not shown) are provided. The contact 54 is connected to the wiring 56, and the contact 55 is connected to one terminal of the memory element 52. The other terminal of the memory element 52 is connected to the upper wiring 58 through a via 57.

  On the other hand, a peripheral circuit 60 is provided in the peripheral circuit region Rc. In the peripheral circuit 60, a contact 61 having a lower end connected to the silicon substrate 10, a wiring 62 connected to the upper end of the contact 61, and a wiring 63 disposed on the wiring 62 are provided.

  The wirings 56 and 62 are each composed of a wiring main body (not shown) and a barrier film (not shown) made of tungsten, and are arranged at the same height with respect to the upper surface 10a of the silicon substrate 10 as a reference. 10 are periodically arranged in the same cycle. The wirings 56 and 62 are critical wirings, which are formed by the same etching process, and are formed using, for example, a sidewall process.

  On the other hand, the wiring 63 includes a wiring main body (not shown) made of copper and a barrier film (not shown). The lower surface of the wiring 63 is located at the same height as or below the upper surface of the wiring 62, and is in contact with the upper surface of the wiring 62. The wiring 63 is thicker than the wiring 62. For example, a plurality of wirings 62 are commonly connected to one wiring 63. The wiring 63 is formed by the damascene method.

The wiring 58 is formed of a wiring body (not shown) made of copper and a barrier film (not shown).
Furthermore, the memory element 52 is, for example, an MTJ (Magnetic Tunnel Junction) element or a resistance change element.

  The effect of this embodiment is the same as that of the first embodiment described above. That is, when the wiring body of the wiring 56 is formed of tungsten, processing by an etching method can be performed, and the wiring 56 can be formed finely. As a result, the degree of integration of memory cells can be increased. Further, the wiring 56 can be formed more finely by using the side wall process together. On the other hand, by providing the wiring 63 containing copper, it is possible to reduce the wiring resistance in the peripheral circuit and increase the speed of the peripheral circuit. Further, by bringing the wiring 63 into direct contact with the wiring 62 without vias, the resistance between the wirings can be reduced and the manufacturing cost can be reduced.

  In each of the above embodiments, the material of the wiring body of the lower layer wiring formed by the RIE method is tungsten (W), and the material of the wiring body of the upper layer wiring formed by the damascene method is copper (Cu). However, the wiring material is not limited to this. For example, the material of the lower wiring layer is preferably a material that can be processed by the RIE method. For example, molybdenum (Mo) may be used instead of tungsten. Further, the material of the upper layer side wiring is preferably a material having a lower resistivity than the material of the lower layer side wiring. For example, aluminum (Al) may be used instead of copper.

  According to the embodiments described above, it is possible to realize a memory device that has low wiring resistance and can be miniaturized, and a method for manufacturing the same.

  As mentioned above, although some embodiment of this invention was described, these embodiment is shown as an example and is not intending limiting the range of invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the scope of the invention described in the claims and the equivalents thereof. Further, the above-described embodiments can be implemented in combination with each other.

1, 1a, 2: memory device, 10: silicon substrate, 10a: upper surface, 11: element isolation insulator, 12: active area, 13: transistor, 14: source / drain region, 15: channel region, 21: floating gate Electrode, 22: Control gate electrode, 23: Select gate electrode, 24: Gate electrode, 25: Interlayer insulating film, 26: Bit line contact, 27: Source line, 28: Source line contact, 29: SD wiring, 30: SD Contact, 31: Interlayer insulating film, 32, 33: Via, 34: Bit line, 34a: Wiring body, 34b: Barrier film, 36: Wiring, 36a: Wiring body, 36b: Barrier film, 36c: Upper surface, 38: Silicon Nitride film, 41: interlayer insulating film, 42: air gap, 43: silicon nitride film, 44: interlayer insulating film, 46: wiring, 46a: wiring body, 46b Barrier film, 46c: lower surface, 47: barrier film, 50: memory cell, 51: transistor, 52: memory element, 53: gate electrode, 54, 55: contact, 56: wiring, 57: via, 58: wiring, 60 : Peripheral circuit, 61: contact, 62, 63: wiring, 71, 72, 73: contact hole, 75, 76, 77: trench, 78, 79: via hole, 81: barrier film, 82: tungsten film, 83: silicon Nitride film, 84: silicon oxide film, 85: amorphous silicon film, 86: silicon oxide film, 86a: core material, 87: sidewall, 88: resist pattern, 90: groove, 90a: bottom surface, 91: (Ti / TiN) Double layer film, 92: Copper film, Rc: Peripheral circuit area, Rm: Memory area

Claims (10)

A storage device in which a memory area and a peripheral circuit area are set,
A substrate,
A plurality of bit lines disposed in the memory region, periodically arranged on the substrate, and including tungsten;
A plurality of lower layer wirings including tungsten, disposed in the peripheral circuit region, disposed at the same height as the bit lines with respect to the upper surface of the substrate;
An upper layer wiring disposed immediately above the lower layer wiring, in contact with the plurality of lower layer wirings, and commonly connected to the plurality of lower layer wirings;
With
The upper layer wiring is
A wiring body made of copper;
A barrier film covering a side surface and a lower surface of the wiring body;
Have
The lower surface of the upper layer wiring is located below the upper surface of the lower layer wiring,
The plurality of lower-layer wirings are periodically arranged, and the arrangement period of the lower-layer wirings is equal to the arrangement period of the bit lines,
A storage device which is a NAND flash memory. A substrate,
A first lower layer wiring periodically arranged on the substrate and containing tungsten or molybdenum;
A second lower layer wiring that is disposed at the same height as the first lower layer wiring with respect to the upper surface of the substrate and includes tungsten or molybdenum;
An upper layer wiring that is disposed directly above the second lower layer wiring, is connected to the second lower layer wiring, and includes copper or aluminum;
With
The storage device, wherein a lower surface of the upper layer wiring is positioned at the same height as or lower than an upper surface of the second lower layer wiring.   The storage device according to claim 2, wherein the upper layer wiring is in contact with the second lower layer wiring.   The storage device according to claim 2, wherein the upper layer wiring is commonly connected to a plurality of the second lower layer wirings.   5. The plurality of second lower layer wirings are periodically arranged, and the arrangement cycle of the second lower layer wirings is equal to the arrangement cycle of the first lower layer wirings. The storage device described in 1. The upper layer wiring is
A wiring body made of copper or aluminum;
A barrier film covering a side surface and a lower surface of the wiring body;
The storage device according to any one of claims 2 to 5, comprising:   7. The storage device according to claim 2, wherein the first lower layer wiring is disposed in a memory region, and the second lower layer wiring is disposed in a peripheral circuit region.   The storage device according to claim 2, wherein the storage device is a NAND flash memory, and the first lower layer wiring is a bit line. Forming an interlayer insulating film on the substrate;
Forming a metal film made of tungsten or molybdenum on the interlayer insulating film;
Etching the metal film to form first and lower wirings arranged periodically, and forming a second lower wiring and
Forming an insulating film so as to cover the second lower layer wiring;
Forming a groove reaching the second lower layer wiring in the insulating film;
Forming an upper layer wiring by embedding copper or aluminum in the groove;
A method for manufacturing a storage device comprising:   The method for manufacturing a memory device according to claim 9, wherein in the step of forming the groove, the bottom surface of the groove is positioned below the upper surface of the second lower layer wiring.

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