KR20070000156A - Method of manufacturing a nand type flash memory device - Google Patents
Method of manufacturing a nand type flash memory device Download PDFInfo
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- KR20070000156A KR20070000156A KR1020050055675A KR20050055675A KR20070000156A KR 20070000156 A KR20070000156 A KR 20070000156A KR 1020050055675 A KR1020050055675 A KR 1020050055675A KR 20050055675 A KR20050055675 A KR 20050055675A KR 20070000156 A KR20070000156 A KR 20070000156A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 150000004767 nitrides Chemical class 0.000 claims abstract description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 29
- 229920005591 polysilicon Polymers 0.000 claims abstract description 29
- 238000002955 isolation Methods 0.000 claims abstract description 16
- 238000005530 etching Methods 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000007517 polishing process Methods 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 20
- 238000005498 polishing Methods 0.000 claims description 20
- 239000002002 slurry Substances 0.000 claims description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Non-Volatile Memory (AREA)
Abstract
Description
본 발명은 NAND형 플래쉬 메모리 소자의 제조 방법에 관한 것으로, 특히 소자 분리막과 액티브 영역의 단차를 줄여 안정된 프로파일을 갖는 플로팅 게이트를 형성함으로써 프로그램 효율을 향상시킬 수 있는 NAND형 플래쉬 메모리 소자의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a NAND type flash memory device, and more particularly, to a method of manufacturing a NAND type flash memory device capable of improving program efficiency by forming a floating gate having a stable profile by reducing the step difference between the device isolation layer and the active region. It is about.
NAND형 플래쉬 메모리 소자는 다수의 셀 블럭으로 구성되며, 하나의 셀 블럭은 데이터를 저장하기 위한 다수의 셀이 직렬 연결되어 하나의 스트링을 구성하는 다수의 셀 스트링, 셀 스트링과 드레인 및 셀 스트링과 소오스 사이에 각각 형성된 드레인 선택 트랜지스터 및 소오스 선택 트랜지스터로 구성된다. 여기서, NAND형 플래쉬 메모리 셀을 제조하기 위한 방법의 일 예를 설명하면 다음과 같다.A NAND type flash memory device is composed of a plurality of cell blocks, and a cell block includes a plurality of cell strings, cell strings, drains, and cell strings that form a string by connecting a plurality of cells for storing data in series. And a drain select transistor and a source select transistor respectively formed between the sources. Here, an example of a method for manufacturing a NAND type flash memory cell will be described.
웰 영역등 소정의 구조가 형성된 반도체 기판 상부에 터널 산화막, 제 1 폴리실리콘막, 버퍼 산화막 및 패드 질화막을 순차적으로 형성한다. 소자 분리 마스크를 이용한 사진 및 식각 공정으로 패드 질화막을 패터닝한다. 패드 질화막을 마스크로 버퍼 산화막, 제 1 폴리실리콘막 및 터널 산화막의 소정 영역을 식각한 후 반도체 기판을 소정 깊이로 식각하여 트렌치를 형성한다. 산화 공정을 실시하여 트렌치 내부에 월 산화막을 형성한 후 트렌치가 매립되도록 전체 구조 상부에 절연막, 예컨데 HDP 산화막을 형성한다. 그리고, CMP 공정을 실시하여 절연막을 연마한 후 패드 질화막을 전면 식각 공정으로 제거하여 소자 분리막을 형성한다. 이때, 버퍼 산화막도 패드 질화막 제거시 제거된다. 전체 구조 상부에 제 2 폴리실리콘막을 형성한 후 제 2 폴리실리콘막이 소자 분리막과 소정 영역 중첩되도록 패터닝하여 플로팅 게이트를 형성한다. 전체 구조 상부에 유전체막, 제 3 폴리실리콘막 및 텅스텐 실리사이드막을 형성한 후 패터닝하여 플로팅 게이트와 콘트롤 게이트가 적층된 게이트를 형성한다.A tunnel oxide film, a first polysilicon film, a buffer oxide film, and a pad nitride film are sequentially formed on the semiconductor substrate having a predetermined structure such as a well region. The pad nitride layer is patterned by a photolithography and an etching process using a device isolation mask. After etching a predetermined region of the buffer oxide film, the first polysilicon film, and the tunnel oxide film using the pad nitride film as a mask, the semiconductor substrate is etched to a predetermined depth to form a trench. An oxidation process is performed to form a monthly oxide film in the trench, and then an insulating film, such as an HDP oxide film, is formed over the entire structure to fill the trench. After the CMP process is performed to polish the insulating layer, the pad nitride layer is removed by an entire etching process to form an isolation layer. At this time, the buffer oxide film is also removed when the pad nitride film is removed. After forming the second polysilicon film on the entire structure, the second polysilicon film is patterned so as to overlap a predetermined region with the device isolation film to form a floating gate. A dielectric film, a third polysilicon film, and a tungsten silicide film are formed over the entire structure, and then patterned to form a gate in which a floating gate and a control gate are stacked.
그런데, 상기와 같은 방법으로 NAND형 플래쉬 메모리 소자를 제조할 경우 패드 질화막을 전면 식각 공정으로 제거하기 때문에 패드 질화막 제거시 HDP 산화막도 일부 제거되며, 패드 질화막 제거 시간에 따라 HDP 산화막의 식각 두께도 달라지므로 이에 따라 소자 분리막의 높이가 결정된다. 그런데, 액티브 영역과 소자 분리막의 높이차가 크기 때문에 이후 제 2 폴리실리콘막을 형성하여 플로팅 게이트를 형성할 경우 플로팅 게이트의 프로파일이 일그러게 되고, 유전체막에서의 전기장 변화를 가져와 프로그램 문턱 전압과 분포에 크게 영향을 미친다. However, when the NAND type flash memory device is manufactured as described above, since the pad nitride layer is removed by the entire etching process, some of the HDP oxide layer is also removed when the pad nitride layer is removed, and the etching thickness of the HDP oxide layer varies according to the pad nitride layer removal time. Therefore, the height of the device isolation layer is determined accordingly. However, since the height difference between the active region and the device isolation layer is large, when the second polysilicon layer is formed to form a floating gate, the floating gate profile is distorted, resulting in a change in the electric field in the dielectric layer, which greatly increases the program threshold voltage and distribution. Affect
본 발명의 목적은 패드 질화막 제거 시간에 따라 높이가 결정되는 소자 분리막과 액티브 영역의 높이차가 크지 않도록 하여 플로팅 게이트의 프로파일 일그러짐을 방지할 수 있는 NAND형 플래쉬 메모리 소자의 제조 방법을 제공하는데 있다.An object of the present invention is to provide a method of manufacturing a NAND type flash memory device capable of preventing profile distortion of a floating gate by preventing a height difference between a device isolation layer and an active region whose height is determined according to a pad nitride film removal time.
본 발명의 다른 목적은 연마 공정으로 패드 질화막을 제거하는 동시에 절연막을 제거한 후 버퍼 산화막을 클리닝 공정으로 제거함으로써 소자 분리막과 액티브 영역의 높이차가 크지 않도록 함으로써 플로팅 게이트의 프로파일 일그러짐을 방지할 수 있는 NAND형 플래쉬 메모리 소자의 제조 방법을 제공하는데 있다.Another object of the present invention is to remove the pad nitride film by a polishing process and at the same time remove the insulating film and then remove the buffer oxide film by a cleaning process so that the height difference between the device isolation layer and the active region is not large, NAND type that can prevent the distortion of the floating gate profile The present invention provides a method for manufacturing a flash memory device.
본 발명의 일 실시 예에 따른 NAND형 플래쉬 메모리 소자의 제조 방법은 반도체 기판 상부에 터널 산화막, 제 1 폴리실리콘막, 버퍼 산화막 및 패드 질화막을 순차적으로 형성하는 단계; 상기 패드 질화막, 버퍼 산화막, 제 1 폴리실리콘막 및 터널 산화막의 소정 영역을 식각한 후 상기 반도체 기판을 소정 깊이로 식각하여 트렌치를 형성하는 단계; 상기 트렌치가 매립되도록 전체 구조 상부에 절연막을 형성한 후 1차 연마 공정으로 상기 절연막을 연마하는 단계; 2차 연마 공정으로 상기 패드 질화막을 제거하는 동시에 상기 절연막을 소정 두께 연마하는 단계; 상기 버퍼 산화막을 제거하여 소자 분리막을 형성하는 단계; 전체 구조 상부에 제 2 폴리실리콘막을 형성한 후 패터닝하여 상기 제 1 및 제 2 폴리실리콘막이 적층된 플로팅 게이트를 형성하는 단계; 및 전체 구조 상부에 유전체막 및 도전층을 형성한 후 패터닝하여 콘트롤 게이트를 형성하는 단계를 포함한다.Method of manufacturing a NAND flash memory device according to an embodiment of the present invention comprises the steps of sequentially forming a tunnel oxide film, a first polysilicon film, a buffer oxide film and a pad nitride film on the semiconductor substrate; Etching a predetermined region of the pad nitride film, the buffer oxide film, the first polysilicon film, and the tunnel oxide film, and then etching the semiconductor substrate to a predetermined depth to form a trench; Forming an insulating film on the entire structure to fill the trench, and then polishing the insulating film by a first polishing process; Removing the pad nitride film by a secondary polishing process and simultaneously polishing the insulating film by a predetermined thickness; Removing the buffer oxide layer to form an isolation layer; Forming and then patterning a second polysilicon film on the entire structure to form a floating gate in which the first and second polysilicon films are stacked; And forming a dielectric film and a conductive layer on the entire structure, and then patterning the control gate to form a control gate.
바람직하게, 상기 절연막은 HDP 산화막을 포함하고, 상기 1차 연마 공정은 폴리실리콘막에 대한 연마 선택비가 높은 슬러리를 이용하여 실시한다. 또한, 상기 2차 연마 공정은 산화막에 대한 연마 선택비가 높은 슬러리를 이용하여 실시하고, 상기 버퍼 산화막이 노출되는 시점을 연마 정지점으로 실시한다.Preferably, the insulating film includes an HDP oxide film, and the primary polishing process is performed using a slurry having a high polishing selectivity with respect to the polysilicon film. In addition, the secondary polishing step is performed using a slurry having a high polishing selectivity with respect to the oxide film, and performs a polishing stop point when the buffer oxide film is exposed.
이하, 첨부된 도면을 참조하여 본 발명의 일 실시 예를 상세히 설명하기로 한다.Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.
도 1(a) 내지 도 1(c)는 본 발명의 일 실시 예에 따른 NAND형 플래쉬 메모리 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a NAND type flash memory device according to an exemplary embodiment of the present invention.
도 1(a)를 참조하면, 웰 영역등 소정의 구조가 형성된 반도체 기판(11) 상부에 터널 산화막(12), 제 1 폴리실리콘막(13), 버퍼 산화막(14) 및 패드 질화막(15)을 순차적으로 형성한다. 소자 분리 마스크를 이용한 사진 및 식각 공정으로 패드 질화막(15)을 패터닝한다. 패드 질화막(15)을 마스크로 버퍼 산화막(14), 제 1 폴리실리콘막(13) 및 터널 산화막(12)의 소정 영역을 식각한 후 반도체 기판(11)을 소정 깊이로 식각하여 트렌치를 형성한다. 산화 공정을 실시하여 트렌치 내부에 월 산화막(도시안됨)을 형성한 후 트렌치가 매립되도록 전체 구조 상부에 절연막(16), 예컨데 HDP 산화막을 형성한다. 그리고, 폴리실리콘막에 대한 연마 선택비가 높은 슬러리를 이용한 CMP 공정을 실시하여 절연막(16)을 연마한다.Referring to FIG. 1A, a tunnel oxide film 12, a first polysilicon film 13, a buffer oxide film 14, and a pad nitride film 15 are formed on a semiconductor substrate 11 having a predetermined structure such as a well region. To form sequentially. The pad nitride layer 15 is patterned by a photolithography and an etching process using the device isolation mask. After etching the predetermined regions of the buffer oxide film 14, the first polysilicon film 13, and the tunnel oxide film 12 using the pad nitride film 15 as a mask, the semiconductor substrate 11 is etched to a predetermined depth to form a trench. . An oxidation process is performed to form a monthly oxide film (not shown) in the trench, and then an insulating film 16, for example, an HDP oxide film, is formed on the entire structure to fill the trench. Then, the insulating film 16 is polished by performing a CMP process using a slurry having a high polishing selectivity with respect to the polysilicon film.
도 1(b)를 참조하면, 산화막에 대한 연마 선택비가 높은 슬러리를 이용한 CMP 공정으로 패드 질화막(15)을 연마하여 소자 분리막을 형성한다. 이때, 패드 질화막(15)의 연마 공정은 버퍼 산화막(14)이 노출되는 시점을 연마 정지점으로 설정하여 실시한다. 그런데, 패드 질화막(15)이 연마될 때 절연막(16) 또한 연마되기 때문에 패드 질화막(15)을 전면 식각하여 제거하는 기존의 공정에 비해 소자 분리막과 액티브 영역의 단차가 발생되지 않는다. 이후 버퍼 산화막(14)은 클리닝 공정에 의해 제거되는데, 이때 절연막(16)도 일부 식각된다.Referring to FIG. 1B, the device nitride is formed by polishing the pad nitride layer 15 by a CMP process using a slurry having a high polishing selectivity to an oxide layer. At this time, the polishing process of the pad nitride film 15 is performed by setting the time point at which the buffer oxide film 14 is exposed as the polishing stop point. However, since the insulating layer 16 is also polished when the pad nitride layer 15 is polished, there is no step difference between the device isolation layer and the active region as compared with the conventional process of removing the pad nitride layer 15 by etching the entire surface. Afterwards, the buffer oxide layer 14 is removed by a cleaning process. At this time, the insulating layer 16 is partially etched.
도 1(c)를 참조하면, 전체 구조 상부에 제 2 폴리실리콘막(17)을 형성한 후 제 2 폴리실리콘막(17)이 소자 분리막과 소정 영역 중첩되도록 패터닝하여 플로팅 게이트를 형성한다. 전체 구조 상부에 유전체막(18), 제 3 폴리실리콘막(19) 및 텅스텐 실리사이드막(20)을 형성한 후 패터닝하여 플로팅 게이트와 콘트롤 게이트가 적층된 게이트를 형성한다.Referring to FIG. 1C, after forming the second polysilicon layer 17 on the entire structure, the second polysilicon layer 17 is patterned to overlap the device isolation layer to form a floating gate. A dielectric film 18, a third polysilicon film 19, and a tungsten silicide film 20 are formed over the entire structure, and then patterned to form a gate in which a floating gate and a control gate are stacked.
상술한 바와 같이 본 발명에 의하면 절연막으로 트렌치를 매립한 후 절연막을 1차 연마하고, 패드 질화막 및 절연막을 2차 연마함으로써 패드 질화막을 전면 식각 공정으로 제거하는 기존의 공정에 비해 액티브 영역과 소자 분리막의 단차를 줄여 이후 플로팅 게이트의 프로파일 일그러짐을 방지할 수 있다. 이에 따라 프로그램 문턱 전압을 안정적으로 분포하도록 하여 로딩 효과를 극복할 수 있다.As described above, according to the present invention, the active region and the device isolation film are compared with the conventional process of removing the pad nitride film by the entire etching process by filling the trench with the insulating film and then polishing the insulating film firstly, and polishing the pad nitride film and the insulating film secondly. By reducing the step difference, it is possible to prevent profile distortion of the floating gate. Accordingly, the loading threshold can be overcome by stably distributing the program threshold voltage.
도 1(a) 내지 도 1(c)는 본 발명의 일 실시 예에 따른 NAND형 플래쉬 메모리 소자의 제조 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a NAND flash memory device according to an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 : 반도체 기판 12 : 터널 산화막11 semiconductor substrate 12 tunnel oxide film
13 : 제 1 폴리실리콘막 14 : 버퍼 산화막13: first polysilicon film 14: buffer oxide film
15 : 패드 질화막 16 : 절연막15 pad nitride film 16 insulating film
17 : 제 2 폴리실리콘막 18 : 유전체막17: second polysilicon film 18: dielectric film
19 : 제 3 폴리실리콘막 20 : 텅스텐 실리사이드막19: third polysilicon film 20: tungsten silicide film
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| KR1020050055675A KR20060136126A (en) | 2005-06-27 | Method of manufacturing a NAND type flash memory device |
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