KR20060099157A - Method of manufacturing a flash memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, a first poly that is used as a floating gate in a manufacturing process of a NAND type flash memory device employing a SA-STI (Self Align Shallow Trench Isolation) process and is formed on a tunnel oxide layer. A method of manufacturing a flash memory device capable of preventing inter-cell interference effects by forming a silicon film to a minimum thickness that can protect a tunnel oxide film is provided.

Floating gate, interference effect, first polysilicon film

Description

Method of manufacturing a flash memory device

1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11 semiconductor substrate 12 tunnel oxide film

13: 1st polysilicon film 14: pad nitride film

15 trench 16: device isolation film

17: second polysilicon film 18: dielectric film

19: third polysilicon film 20: tungsten silicide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, a first poly that is used as a floating gate in a manufacturing process of a NAND type flash memory device applying a SA-STI (Self Align Shallow Trench Isolation) process and is formed on a tunnel oxide layer. The present invention relates to a method of manufacturing a flash memory device capable of preventing inter-cell interference effects by forming a silicon film to a minimum thickness that can protect the tunnel oxide film.

In the NAND type flash memory device, a plurality of cells for storing data are connected in series to form a string, and a drain select transistor and a source select transistor are connected between the cell string and the drain and the cell string and the source, respectively. The cell of the NAND type flash memory device forms a device isolation film in a predetermined region on a semiconductor substrate by an STI process, and then forms a gate in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked in a predetermined region on the semiconductor substrate. It is formed by forming junctions on both sides of the gate.

In such a NAND-type flash memory device, it is very important to keep the cell state constant because the state of the cell is affected by the operation of adjacent neighboring cells. The change in the state of a cell due to the operation of adjacent neighboring cells, in particular a program operation, is called an interference effect. That is, the interference effect means that when the second cell adjacent to the first cell to be read is programmed, the threshold voltage is higher than the threshold voltage of the first cell when the first cell is read due to the capacitance action caused by the charge change of the floating gate of the second cell. This refers to a phenomenon in which the reading of the floating gate of the read cell does not change, but the state of the actual cell is distorted due to the change of the state of the adjacent cell. This interference effect causes the state of the cell to change, which results in an increase in the defective rate resulting in a lower yield. Therefore, minimizing the interference effect may be effective to keep the state of the cell constant.

Meanwhile, in a typical NAND type flash memory device manufacturing process, the device isolation layer is formed by using a SA-STI process. After the tunnel oxide film and the first polysilicon film are formed on the semiconductor substrate, the first polysilicon film and the tunnel oxide film are formed. After the region is etched and the semiconductor substrate is etched to a predetermined depth to form a trench, an insulating film is embedded and a polishing process is performed to form an isolation layer. Thereafter, a second polysilicon film is formed on the entire structure, and then patterned to form a floating gate in which the first and second polysilicon films are stacked. In this case, the height of the device isolation layer from the surface of the semiconductor substrate is referred to as an effective field oxide height (EFH), and the effective height is equal to or higher than the height of the first polysilicon layer in order to secure sufficient margin in the process. However, this results in an increase in the interference effect between other cells sharing the same word line, which causes a decrease in cell uniformity. In particular, when fabricating a flash memory device with a multilevel cell structure, such cell uniformity is achieved. This is a very important factor.

The present invention provides a method of manufacturing a flash memory device that can reduce the interference effect between cells by forming a thin first polysilicon film that is used as a floating gate and is formed on the tunnel oxide film.

In the case of cells sharing the word line, the capacitance of both ends of the first polysilicon film increases as the area of the first polysilicon film adjacent to each other with the device isolation layer therebetween increases the charge change of one side of the first polysilicon film, that is, the charge change of the floating gate. The possibility of causing a state distortion phenomenon of the other floating gate in the read operation increases. Therefore, in the present invention, the thickness of the first polysilicon film used as the floating gate and formed on the tunnel oxide film is thinly formed to reduce the interference effect. Meanwhile, in the case of the second polysilicon film formed on the first polysilicon film and serving as a floating gate together with the first polysilicon film, a third polysilicon film serving as a control gate is formed between adjacent second polysilicon films. Since a predetermined bias is applied to the third polysilicon film during a program or read operation, a capacitance effect is less likely to occur between the both ends due to a shielding effect caused by the bias of the third polysilicon film. Therefore, the second polysilicon film is excluded from consideration, and only the capacitance below the device isolation layer needs to be considered. This interference effect is also applied to the general STI process, not the SA-STI process, and is an item that must be considered when the polysilicon layer is adjacent to each other with the device isolation layer therebetween. In particular, as the size of the device isolation layer decreases due to high integration of semiconductor devices, the interference effect becomes more pronounced.

In the method of manufacturing a flash memory device according to an embodiment of the present invention, a tunnel oxide film is formed on a semiconductor substrate, and a first polysilicon film is formed on the tunnel oxide film to a minimum thickness to protect the tunnel oxide film. Forming a nitride film; Forming a trench by etching a predetermined region of the pad nitride layer to the tunnel oxide layer by a photolithography and an etching process using a device isolation mask, and then etching the semiconductor substrate to a predetermined depth; Forming an insulating film to fill the trench, and then performing a polishing process, and removing the pad nitride film to form an isolation layer; Forming a second polysilicon layer over the entire structure and patterning the second polysilicon layer to form a floating gate pattern formed of the first and second polysilicon layers; And forming a dielectric film, a third polysilicon film, and a tungsten silicide film on the entire structure and patterning the same to form a gate in which a floating gate and a control gate are stacked.

Here, the first polysilicon film is formed to a thickness of 100 to 200 kPa.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 (a) to 1 (c) are cross-sectional views of devices sequentially illustrated to explain a method of manufacturing a flash memory device according to an embodiment of the present invention.

Referring to FIG. 1A, a tunnel oxide film 12, a first polysilicon film 13, and a pad nitride film 14 are sequentially formed on a semiconductor substrate 11 having a predetermined structure. After etching a predetermined region of the pad nitride layer 14, the first polysilicon layer 13, and the tunnel oxide layer 12 by a photolithography and etching process using a element isolation mask, the semiconductor substrate 11 is etched to a predetermined depth to form a trench. (15) is formed. Here, although the first polysilicon film 13 is conventionally formed to a thickness of 500 kPa or more, in the present embodiment, the first polysilicon film 13 is formed to a thickness sufficient to protect the tunnel oxide film 12, for example, a thickness of about 100 to 200 kPa.

Referring to FIG. 1B, an oxide process is performed to form a monthly oxide film (not shown) inside the trench 15, and then an insulating film, for example, an HDP oxide film is formed on the entire structure to fill the trench 15. After the CMP process is performed to polish the insulating film, the pad nitride film 14 is removed to form the device isolation film 16. At this time, since the first polysilicon film 13 is formed thin, the effective height of the device isolation film 16 is lower than that of the related art.

Referring to FIG. 1C, after forming the second polysilicon layer 17 on the entire structure, the second polysilicon layer 17 is patterned so as to overlap a predetermined region with the device isolation layer 16 to determine the floating gate. do. A dielectric film 18, a third polysilicon film 19, and a tungsten silicide film 20 are formed over the entire structure, and then patterned to form a gate in which a floating gate and a control gate are stacked. Subsequently, a predetermined ion implantation process is performed to form junctions (not shown) on the semiconductor substrate 11 at both sides of the gate.

As described above, according to the present invention, as the area of the first polysilicon film adjacent to each other with the device isolation layer between them is increased, the capacitance at both ends thereof increases, and is used as a floating gate to form the upper portion of the tunnel oxide film. The first polysilicon film is formed to a minimum thickness capable of protecting the tunnel oxide film. As a result, the width of the cell distribution can be reduced, so that uniformity can be improved, and program speed can be improved, thereby contributing to yield improvement.

Claims (2)

Forming a tunnel oxide layer on the semiconductor substrate, forming a first polysilicon layer on the tunnel oxide layer to a minimum thickness capable of protecting the tunnel oxide layer, and then forming a pad nitride layer; Forming a trench by etching a predetermined region of the pad nitride layer to the tunnel oxide layer by a photolithography and an etching process using a device isolation mask, and then etching the semiconductor substrate to a predetermined depth; Forming an insulating film to fill the trench, and then performing a polishing process, and removing the pad nitride film to form an isolation layer; Forming a second polysilicon layer over the entire structure and patterning the second polysilicon layer to form a floating gate pattern formed of the first and second polysilicon layers; And And forming a dielectric film, a third polysilicon film, and a tungsten silicide film on the entire structure and patterning the same to form a gate in which a floating gate and a control gate are stacked. The method of claim 1, wherein the first polysilicon film is formed to a thickness of about 100 to about 200 microseconds.

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