KR20070026957A - Flash memory device and method of manufacturing the same - Google Patents

Abstract

A flash memory device and its manufacturing method are provided to prevent the degradation of a program efficiency by preventing the degradation of a coupling ratio due to the difference of an EFH(Effective Field oxide Height) in an isolation layer using a plurality of dummy patterns inserted into a boundary between a cell region and a peripheral region. A flash memory device comprises a cell region(100) with a plurality of cells capable of storing data, a peripheral region, and a plurality of dummy patterns. The peripheral region(200) is defined at a periphery of the cell region to apply a bias to a cell of the cell region. The plurality of dummy patterns(400) are formed at a boundary between the cell and peripheral regions to separate the cell region from the peripheral region.

Description

Flash memory device and method of manufacturing the same

1 is a plan view of a NAND type flash memory device of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a partially enlarged view of the dummy pattern of FIG. 1. FIG.

3 is a cross-sectional view taken along the line A-A of FIG. 1 to explain a method of manufacturing a NAND type flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100: cell area 200: peripheral circuit area

300: boundary area 400: dummy pattern

500 semiconductor substrate 600 device isolation film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device. In particular, by inserting a dummy pattern into a boundary region between a cell region and a peripheral circuit region to form a device isolation layer, the EFH of the device isolation layer in all regions can be the same, thereby improving program efficiency. A NAND type flash memory device and a method of manufacturing the same.

The semiconductor memory device includes a cell region in which a plurality of cells are formed and a peripheral circuit region for driving the cell. For example, a NAND-type flash memory device includes a plurality of cell blocks, and one cell block includes a plurality of cell strings and cell strings in which a plurality of cells for storing data are connected in series to form a string. And a drain select transistor and a source select transistor formed between the drain and the cell string and the source, respectively. In addition, a peripheral device including a plurality of high voltage and low voltage transistors is configured in the peripheral circuit area to supply a predetermined bias for performing program, erase, and read operations to predetermined cells of the cell block. On the other hand, a cell of a NAND type flash memory device is formed in which a stack gate in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked is formed in a predetermined region on a semiconductor substrate, and junctions are formed on both semiconductor substrates of the stack gate.

The cell region, peripheral circuit region, and the like of such a NAND type flash memory device are determined by forming a well region corresponding to each region on a semiconductor substrate by an ion implantation process or the like, and forming an element isolation film using an STI process or the like. On the other hand, the element isolation film is formed by an STI process or the like to determine the active region and the field region, and at the same time separates each region and the elements constituted in the region. Here, the device isolation film using the STI process is formed by forming a trench in a predetermined region on the semiconductor substrate, and then forming an insulating film, for example, an HDP oxide film, and planarization by a CMP process. By the way, the cell region has a dense pattern density, and the peripheral circuit region has a coarse pattern density. In particular, the device isolation film formed in the boundary region between the cell region and the peripheral circuit region is larger than the device isolation film in the other regions. However, although the effective field oxide height (EFH) can be kept constant in the cell region according to the characteristics of the CMP process for polishing the insulating film, the pattern density of the coarse region, especially the cell region and the peripheral circuit region Since the polishing amount of the boundary region is larger than that of the cell region, the EFH of the device isolation layer in the boundary region is lowered as a result.

On the other hand, the capacitance ratio is called a coupling ratio. When the coupling ratio is "1", it means that the bias applied to the control gate is applied to the floating gate as it is without a voltage drop. This means that the bias applied to the control gate to drive the memory cell must be higher by that amount. However, since the coupling ratio changes during programming according to the height of the EFH, the program threshold voltage change is generated as much as the EFH change. Therefore, when the uniformity of the CMP process for forming the device isolation film is lowered and the uniformity of the EFH is lowered, the coupling ratio is lowered. As a result, there is a problem of widening the program threshold voltage distribution and lowering the program efficiency.

An object of the present invention is to form a dummy pattern when forming a device isolation layer in a coarse pattern density to make the EFH of the device isolation layer the same in all areas to improve the coupling ratio to improve program efficiency. It is to provide a method for producing.

A flash memory device according to an embodiment of the present invention may include a cell region in which a plurality of cells for storing data are formed; A peripheral circuit region defined around the cell region for applying a bias for a predetermined operation to a predetermined cell of the cell region; And a boundary region formed between the cell region and the peripheral circuit region to separate them, respectively, and including a plurality of dummy patterns.

The dummy pattern is repeatedly formed at intervals of 0.5 μm based on a square donut-shaped pattern of 1.5 μm × 1.5 μm.

On the other hand, a method of manufacturing a flash memory device according to another embodiment of the present invention comprises the steps of determining a cell region, a peripheral circuit region, a boundary region, etc. in a predetermined region on the semiconductor substrate; Forming a trench in a predetermined region of the cell region and a peripheral circuit region and simultaneously forming a dummy pattern by partially leaving the semiconductor substrate in the boundary region; And forming an insulating film on the entire structure and then performing a polishing process to form an element isolation film having the same EFH in all regions.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a flash memory device according to an exemplary embodiment, and FIG. 2 is a partially enlarged view of a dummy pattern.

The cell region 100 is an area in which a plurality of cells for storing data are formed. In the case of a NAND type flash memory device, a plurality of cell strings in which a plurality of cells for storing data are connected in series to form one string, And a drain select transistor and a source select transistor formed between the cell string and the drain and between the cell string and the source, respectively. In addition, the peripheral circuit region 200 is determined around the cell region 100, and a plurality of high voltages and low voltages are provided to supply predetermined biases for program, erase, and read operations to predetermined cells of the cell region 100. It is a region where peripheral elements including transistors are configured. A plurality of dummy patterns 400 according to the present invention are formed in the boundary region 300 for distinguishing the cell region 100 from the peripheral circuit region 200. The dummy pattern 400 is repeatedly formed at intervals of 0.5 μm based on a square donut-shaped pattern of 1.5 μm × 1.5 μm, as shown in a partial enlarged view of FIG. 2. Here, the portion 420 where the pattern is not formed is formed with a width of 0.5 μm, and the portion 410 where the pattern is formed is formed with a width of 0.5 μm in all directions about the portion 420 where the pattern is not formed. .

3 is a cross-sectional view taken along the line A-A of FIG. 1 and illustrates a method for forming a dummy pattern using the same. As shown, the dummy pattern 400 partially overlaps the semiconductor substrate 500 of the boundary region 300 of the cell region 100 and the peripheral circuit region 200 when the trench is formed to form an isolation layer by an STI process. It is formed by etching. This is different from the conventional method of forming a wide trench by etching the semiconductor substrate 500 of the boundary region 300 as a whole. After forming the trench in which the dummy pattern 400 is formed in the boundary region 300, the insulating layer 600, for example, the HDP oxide layer is formed on the entire structure, and the CMP process is performed, thereby forming the cell region 100 and the peripheral circuit region 200. ) And the EFH of the device isolation film of the boundary region 300 are formed in the same manner.

As described above, according to the present invention, a device isolation layer is formed by inserting a plurality of dummy patterns in a boundary region between a cell region and a peripheral circuit region, thereby forming a device isolation layer. Can be prevented from being lowered, thereby reducing the program efficiency.

Claims (3)

A cell region in which a plurality of cells for storing data are formed; A peripheral circuit region defined around the cell region for applying a bias for a predetermined operation to a predetermined cell of the cell region; And a boundary region formed between the cell region and the peripheral circuit region to separate them from each other, the boundary region including a plurality of dummy patterns. The flash memory device of claim 1, wherein the dummy pattern is repeatedly formed at intervals of 0.5 μm based on a square donut-shaped pattern of 1.5 μm × 1.5 μm. Determining a cell region, a peripheral circuit region, a boundary region, and the like in a predetermined region on the semiconductor substrate; Forming a trench in a predetermined region of the cell region and a peripheral circuit region and simultaneously forming a dummy pattern by partially leaving the semiconductor substrate in the boundary region; And A method of manufacturing a flash memory device, comprising: forming an insulating film on an entire structure, and then performing a polishing process to form an element isolation film having the same EFH in all regions.

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