KR20060099153A - Method of manufacturing a flash memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of fabricating a flash memory device, wherein a trench for forming a device isolation layer using a shallow trench isolation (STI) process has a vertical profile from a top of a semiconductor substrate to a depth of a junction, and thereafter, a target depth. By forming the channel to have a predetermined slope profile, it is possible to reduce the channel capacitance by reducing the area of the channel as a whole, thereby reducing the program speed and the program disturbance, especially the disturbance of adjacent cells sharing the word line in the channel boosted with high voltage. A method of manufacturing a NAND type flash memory device is provided.

Device Isolation, Trench, Dual Profile, Channel Capacitance

Description

Method of manufacturing a flash memory device

1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a flash memory device according to an embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

11 semiconductor substrate 12 tunnel oxide film

13: 1st polysilicon film 14: pad nitride film

15 trench 16: device isolation film

17: second polysilicon film 18: dielectric film

19: third polysilicon film 20: tungsten silicide film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of manufacturing a NAND type flash memory device that can reduce program capacitance and improve program speed and program disturbance.

In the NAND type flash memory device, a plurality of cells for storing data are connected in series to form a string, and a drain select transistor and a source select transistor are connected between the cell string and the drain and the cell string and the source, respectively. In the NAND flash memory cell, a device isolation film is formed in a predetermined region of a semiconductor substrate, and a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked in a predetermined region above the semiconductor substrate to form a gate, and semiconductors on both sides of the gate are formed. It is formed by forming an ion implantation region on a substrate. Here, the device isolation film is formed by a shallow trench isolation (STI) process in which a trench is formed in a predetermined region of a semiconductor substrate according to the high integration of the device, and then the insulating film is buried. After forming, an isolation layer may be formed.

The NAND-type flash memory cell injects or emits electrons into a floating gate to perform a program or erase operation. The program operation generates a hot carrier through the side of the drain, and floats the hot carrier through the tunnel oxide layer. This is done by injecting into the gate. In addition, the erase operation is performed by emitting electrons in the floating gate using F-N tunneling generated by a high electric field between the source and the floating gate or the bulk and the floating gate.

In order to perform the program and erase operations of the flash memory cell, a high voltage must be applied to the gate. In this case, a low voltage driving is restricted. This is because bias cannot be applied directly to the floating gate, only through the control gate. That is, since the voltage drop is generated by the dielectric film formed between the control gate and the floating gate, many restrictions are placed on low voltage driving. This voltage drop depends on the thickness of the dielectric film and the junction area.

On the other hand, the capacitance ratio is called a coupling ratio. When the coupling ratio is "1", it means that the bias applied to the control gate is applied to the floating gate as it is without a voltage drop. This means that the bias applied to the control gate to drive the memory cell must be higher by that amount. The coupling ratio of the flash memory cell is affected by the thickness of the dielectric film, the junction area between the dielectric film and the gate, and the channel capacitance. In particular, as the channel capacitance decreases, the coupling ratio becomes large.

These NAND-type flash memory cells are important factors that determine program performance and program disturbance, and it is important to reduce the disturbance while increasing the program speed. It is also difficult to improve all of them.

However, in the conventional manufacturing process of the NAND type flash memory device, the trench for forming the device isolation film is formed to have a predetermined slope from the upper portion of the semiconductor substrate to the target depth, and then other processes such as changing the junction area and the thickness of the dielectric film are made. Many attempts have been made to improve program speed and disturbance characteristics. However, in this process, various additional problems occur, and not only a lot of time and difficulty in solving these additional problems, but also various difficulties in simultaneously improving both program speed and disturbance.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a flash memory device capable of reducing channel capacitance and simultaneously improving program speed and disturbance.

Another object of the present invention is to form a trench for forming the device isolation layer to have a vertical profile from the top of the semiconductor substrate to a predetermined depth, and then to have a predetermined inclined profile up to the target depth, thereby reducing channel capacitance without changing other processes. The present invention provides a method of manufacturing a flash memory device.

Non-programmed cell arrays typically boost the channel to high voltages to suppress program disturbances. However, leaky electrons are generated by the source and the source select transistor, and the discontinuity is caused during the program operation of adjacent cells sharing the wordline by the leaky electrons, which leads to a decrease in yield, which affects productivity. Get mad.

The program disturbance of these cells occurs when a program is repeatedly executed for a long time. Therefore, high bias is maintained in the channel only during the program operation of the cell and immediately after the program operation is terminated, dosing to 0V or a low bias condition. However, when the capacitance of the channel is increased, it becomes a delay factor in discharging the bias of the channel. Therefore, it is advantageous to reduce the channel capacitance, and thus the program capacitance of the cell can be minimized with the reduced channel capacitance.

Therefore, in the present invention, the trench for forming the device isolation layer is formed vertically from the top of the semiconductor substrate to a predetermined depth, and then formed to have a predetermined angle up to the target depth, thereby reducing channel capacitance, thereby improving both program speed and program disturbance. And little effect on other cell characteristics.

A method of manufacturing a flash memory device according to an embodiment of the present invention may include forming a trench having a double slope in a predetermined region on a semiconductor substrate; Forming an isolation layer by forming an insulating layer to fill the trench; Forming a gate in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked in a predetermined region on the semiconductor substrate; And forming a junction on the semiconductor substrate at both sides of the gate.

In another embodiment, a method of manufacturing a flash memory device may include sequentially forming a tunnel oxide layer, a first polysilicon layer, and a pad nitride layer on a semiconductor substrate; the pad nitride layer by a photo-etching process using an isolation mask. Forming a trench having a double slope in a predetermined region of the semiconductor substrate after etching the predetermined region of the tunnel oxide layer; Forming an insulating film to fill the trench, and then performing a polishing process, and removing the pad nitride film to form an isolation layer; Forming a second polysilicon layer over the entire structure and patterning the second polysilicon layer to form a floating gate pattern formed of the first and second polysilicon layers; Forming a dielectric film, a third polysilicon film, and a tungsten silicide film on the entire structure, and then patterning to form a gate in which a floating gate and a control gate are stacked; And forming a junction on the semiconductor substrate at both sides of the gate.

Here, the trench is formed to have a vertical profile up to the depth of the junction and a predetermined inclined profile up to a target depth thereafter.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 (a) to 1 (c) are cross-sectional views of devices sequentially shown to explain a method of manufacturing a NAND type flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A, a tunnel oxide film 12, a first polysilicon film 13, and a pad nitride film 14 are sequentially formed on a semiconductor substrate 11 having a predetermined structure. After etching a predetermined region of the pad nitride layer 14, the first polysilicon layer 13, and the tunnel oxide layer 12 by a photolithography and an etching process using an element isolation mask, the semiconductor substrate 11 is etched to a predetermined depth to form a trench ( 15). At this time, the trench 15 is formed to have a double inclination, and has a vertical profile (A) up to a predetermined depth, for example, the depth of the junction formed thereafter, and then has a predetermined inclination profile (B) up to the target depth. That is, the trench 15 has a vertical profile up to the boundary of the well and the junction formed after the gate forming process.

Referring to FIG. 1B, an oxide process is performed to form a monthly oxide film (not shown) inside the trench 15, and then an insulating film, for example, an HDP oxide film is formed on the entire structure to fill the trench 15. After the CMP process is performed to polish the insulating film, the pad nitride film 14 is removed to form the device isolation film 16.

Referring to FIG. 1C, after forming the second polysilicon layer 17 on the entire structure, the second polysilicon layer 17 is patterned so as to overlap a predetermined region with the device isolation layer 16 to determine the floating gate. do. A dielectric film 18, a third polysilicon film 19, and a tungsten silicide film 20 are formed over the entire structure, and then patterned to form a gate in which a floating gate and a control gate are stacked. Subsequently, a predetermined ion implantation process is performed to form junctions (not shown) on the semiconductor substrate 11 at both sides of the gate. In this case, the junction portion (not shown) may be formed to a portion having a vertical profile of the device isolation layer 16.

As described above, according to the present invention, when forming a trench for forming a device isolation layer using an STI process, the semiconductor substrate has a vertical profile from the top of the semiconductor substrate to the depth of the junction, and then has a predetermined inclined profile from thereafter to the target depth. This reduces the channel capacitance by reducing the area of the channel as a whole, thereby reducing program speed and program disturbances, particularly the discontinuity of adjacent cells sharing wordlines in high-voltage boosted channels.

Claims (4)

Forming a trench having a double profile in a predetermined area on the semiconductor substrate; Forming an isolation layer by forming an insulating layer to fill the trench; Forming a gate in which a tunnel oxide film, a floating gate, a dielectric film, and a control gate are stacked in a predetermined region on the semiconductor substrate; And Forming a junction on the semiconductor substrate at both sides of the gate. The method of claim 1, wherein the trench has a vertical profile up to a depth of the junction and a predetermined inclination profile from thereafter to a target depth. Sequentially forming a tunnel oxide film, a first polysilicon film, and a pad nitride film on the semiconductor substrate; Etching a predetermined region of the pad nitride layer or the tunnel oxide layer by a photolithography and an etching process using an element isolation mask to form a trench having a double profile in the predetermined region of the semiconductor substrate; Forming an insulating film to fill the trench, and then performing a polishing process, and removing the pad nitride film to form an isolation layer; Forming a second polysilicon layer over the entire structure and patterning the second polysilicon layer to form a floating gate pattern formed of the first and second polysilicon layers; Forming a dielectric film, a third polysilicon film, and a tungsten silicide film on the entire structure, and then patterning to form a gate in which a floating gate and a control gate are stacked; And Forming a junction on the semiconductor substrate at both sides of the gate. The method of claim 3, wherein the trench has a vertical profile up to a depth of the junction and a predetermined inclination profile from thereafter to a target depth.

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