KR100891425B1 - NAND flash memory device - Google Patents

Abstract

The present invention relates to a NAND flash memory device, in which a common source line (CSL) is arranged in a shorter form by a distance of about three dummy active regions, When the ion implantation mask is moved in the i-line in the implantation process, the p-type ions are implanted into the dummy active region adjacent to the well pick-up region, and the bias of the common source line CSL is applied to the p- Can be prevented from being connected to the well pickup through the dummy active region of the type. Furthermore, by forming the dummy active region in the field region where the well pickup is formed in the same manner as the active region, the contact resistance occurring in the dummy active region of the well pickup region can be reduced.

Well pickup, dummy active area, common source line, EFH

Description

[0001] NAND FLASH MEMORY DEVICE [0002]

1 is a layout diagram showing a well pickup of a general NAND flash memory device.

2A and 2B are cross-sectional views of devices sequentially shown to show a cut-away view of line A-A of FIG.

3 is a layout diagram illustrating a NAND flash memory device according to a first embodiment of the present invention.

4A is a cross-sectional view taken along line B-B of FIG.

Fig. 4B is a cross-sectional view taken along the line C-C of Fig. 3; Fig.

5 is a layout diagram illustrating a NAND flash memory device according to a second embodiment of the present invention.

6 is a layout diagram illustrating a NAND flash memory device according to a third embodiment of the present invention.

Description of the Related Art

10, 100, 500: active area 20, 200, 600: field area

30, 300, 700: dummy active area W: well pickup

WL1, WL2, WL3, ..., WLn: word line

DCT: drain contact CSL: common source line

DST: Drain select transistor SST: Source select transistor

M: Ion implantation mask

The present invention relates to a NAND flash memory device, and more particularly to a NAND flash memory device capable of suppressing a decrease in effective field height (EFH) in a field region and improving EFH variation, To a NAND flash memory device.

The presence of a well pick-up in an array in the NAND flash memory device is to ensure that the distribution of the entire cell array does not depend on the distance of the well pickup when the erase operation is performed by the well.

1 is a layout diagram showing a well pickup of a general NAND flash memory device.

Referring to FIG. 1, active regions 1 in which channel and source and drain of a memory cell transistor are to be formed are repeated in parallel with the field region 2, respectively. A plurality of word lines WL1, WL2, ..., WLn formed so as to be spaced apart from each other by a predetermined distance are arranged on the active regions 1 at right angles to the active region 1 and the field region 2. [ A drain select transistor (DST) is disposed outside the first word line WL1 and a source select transistor (SST) is disposed outside the nth word line WLn. The plurality of word lines WL1, WL2, ..., WLn including the source select transistor SST and the drain select transistor DST are connected in series to each other to form one cell string, As described above, the cell string structure is continuously repeated. A drain contact (DCT) is disposed above the active region 1 between successive drain select transistors DST and a common source line DST is formed above the active region 1 between successive source select transistors SST. (CSL). The dummy active region D is disposed outside the active region 1 after the well pickup W is disposed between the common source lines CSL. Here, the dummy active region D is formed to be wider than the active region 1. After the well pickup region W is disposed between the common source lines CSL, the ion implantation mask M for performing the ion implantation process into the well pickup region W to make it into the p-type is formed in the well pickup region W And between the active regions 1 including the well pickup region W in order to prevent the field region 2 of the well pickup region W from being etched during the etching of the field region 2, A well pick-up close mask CM is disposed in the upper region of the mask.

2A and 2B are cross-sectional views of devices sequentially shown to show a cut-away view of line A-A of FIG.

2A, a tunnel oxide film 11 and a polysilicon film 12 for a floating gate are sequentially formed on a semiconductor substrate 10, and then a polysilicon film 12, a tunnel oxide film 11, and a semiconductor substrate 10 are etched to form a trench. An isolation film 13, for example, an HDP (high density plasma) oxide film is buried in the trench to form an isolation film 13, and then an isolation process is performed to control the EFH of the isolation film 13. At this time, in order to prevent the device isolation film 13 in the well pickup area W from being lost in the etching process of the device isolation film 13, a close mask CM is formed on the device isolation film 13 in the well pickup area W The etching process is performed.

Referring to FIG. 2B, after removing the close mask CM, a dielectric film 14 and a conductive film 15 for a control gate are sequentially formed on the entire structure.

However, when the gate is formed as described above, the device isolation films 13 on both sides of the last dummy active region D are excessively etched due to the difference in pattern density, so that the distance between the control gate and the well is shortened and the capacitance becomes large . As a result, the bias applied to the control gate during cell operation drops.

It is an object of the present invention, which is devised to solve the above-mentioned problems, to provide a NAND flash memory device for suppressing a decrease in field field EFH and improving EFH fluctuation, thereby lowering a fail ratio according to cell distribution and stress test .

A NAND flash memory device according to an embodiment of the present invention is characterized in that active regions are repeated in parallel with a field region in a semiconductor substrate and a dummy active region formed in parallel with the field region in a field region having a wide width between the active regions, A source select transistor and a drain select transistor formed on both sides of the plurality of word lines and formed over the semiconductor substrate; a common source line formed between the source select transistors; And an ion implantation mask disposed in a remaining region except for the well pickup region for performing the ion implantation process to make the well pickup region into a p-type region.

In the above, the dummy active region has the same size as the width of the active region.

The common source line is not arranged in three or more dummy active regions on both sides of the well pickup among the dummy active regions but is arranged on the top of the active region excluding three or more dummy active regions and is shorter .

The dummy active region has the same size as the width of the active region, and the width of the dummy active region in the region where the well pickup is formed has a width wider than the width of the active region.

The dummy active region is formed to be equal to the width of the active region, except for the open region due to the ion implantation mask.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a layout diagram illustrating a NAND flash memory device according to a first embodiment of the present invention.

Referring to FIG. 3, in the NAND type flash memory device, active regions 10 in which channels, source and drain regions of a memory cell transistor are formed are repeated in parallel with the field regions 20, and a well pickup W is formed The dummy active regions 30 are repeated in parallel with the field regions 20 in the wide field region 20 'between the active regions 10 as well. Here, the dummy active region 30 is equal to the width of the active region 10. A plurality of word lines WL1, WL2, ... WLn formed so as to be spaced apart from each other by a predetermined distance orthogonally to the active region 10, the field region 20 and the dummy active region 30 on the active regions 10 . The drain select transistor DST is arranged outside the first word line WL1 and the source select transistor SST is arranged outside the nth word line WLn. The plurality of word lines WL1, WL2, ..., WLn including the source select transistor SST and the drain select transistor DST are connected in series to each other to form one cell string. As described above, The above cell string structure is continuously repeated continuously. (DCT) is arranged above the active region 10 between the drain select transistors DST of the adjacent cell strings and the active region 10 between the source select transistors SST of the adjacent cell strings, And a common source line CSL is disposed on the upper portion. Here, the common source line CSL is not arranged in three or more dummy active areas 30 on both sides of the well pickup W among the dummy active areas 30, but three or more dummy active areas 30 Are disposed on the active region 10 and arranged in a shorter form by a distance of about three dummy active regions 30 as compared with the common source line CSL. An ion implantation mask M for providing a well pickup W region to a p-type region is formed in a well pickup region W by arranging a well pickup W between common source lines CSL, In the remaining portions.

As described above, by arranging the common source line CSL in a shorter form by the distance of about three dummy active regions 30 compared with the conventional method, the ion implantation process in the p-type ion implantation process using the ion implantation mask (M) The p-type ions are also injected into the dummy active region 30 adjacent to the well pickup region W so that the bias of the common source line CSL is applied to the p-type dummy active region 30, (W) through the first and second bus bars (30). The contact resistance generated in the dummy active region 30 of the well pickup W region can be reduced by forming the dummy active region 30 in the same manner as the active region 10 in the well pickup W region.

FIGS. 4A and 4B are cross-sectional views sequentially illustrating the NAND flash memory device according to the first embodiment of the present invention. FIG. 4A is a cross-sectional view taken along line BB in FIG. Is a cross-sectional view taken along the line CC in Fig.

4A, a tunnel oxide film 102 and a polysilicon film 104 for a floating gate are sequentially formed on a semiconductor substrate 100, and then a polysilicon film 104, a tunnel oxide film 102, and a semiconductor substrate 100 are etched to form a trench. An insulating film such as an HDP oxide film is formed in the trench to form the device isolation film 106 so that the trench is buried. At this time, the active region a and the field region b are defined by the isolation film 106. A part of the element isolation film 106 is etched to control the EFH of the element isolation film 106. At this time, the active region a and the field region b are similarly repeated in the well pickup region, so that the element isolation film 106 in the well pickup region W is not excessively etched during the etching process of the device isolation film 106.

The conductive film 110, the dielectric film 108, and the polysilicon film 104 are sequentially etched after the dielectric film 108 and the conductive film 110 for the control gate are sequentially formed on the entire structure Thereby forming a gate. At this time, the element isolation film 106 in the well pickup (W) region is etched to a constant thickness without overetching, thereby ensuring a distance between the control gate and the well at the time of gate formation. This makes it possible to prevent the capacitance from increasing.

Referring to FIG. 4B, an ion implantation process using an ion implantation mask (not shown in FIG. 3) in which a well pickup region W is exposed is performed to convert the well pickup region W into a p-type region. In this case, i-line is performed using P-type dopant in the ion implantation process. An insulating film (not shown) is formed on the entire structure and then the insulating film is etched with a predetermined mask to form a common source line CSL on the predetermined active region a and the field region b. At this time, the field region b in which the active region a and the element isolation film 106 are formed is opened between the common source lines CSL when the common source line CSL is formed.

As described above, by forming the common source line CSL to be shorter than the dummy active region (30 in Fig. 3) by a distance of about three compared to the common source line CSL of the existing (g), the ion implantation mask Type ion implantation process, the p-type ions are injected into the dummy active region (30 in FIG. 3) adjacent to the well pickup (W) region and the bias of the common source line (CSL) Can be prevented from being connected to the well pickup (W) through the p-type active region.

5 is a layout diagram illustrating a NAND flash memory device according to a second embodiment of the present invention.

Referring to FIG. 5, in the NAND type flash memory device, active regions 100 in which channels, source and drain regions of a memory cell transistor are formed are repeated in parallel with a field region 200, and a well pickup W is formed The dummy active regions 300 are repeated in parallel with the field regions 200 in the wide field region 200 'between the active regions 100 as well. The width of the dummy active region 300 in the region where the well pick-up W is formed is set to be twice the width of the active region 100, Or more. A plurality of word lines WL1, WL2,... WLn formed so as to be spaced apart from each other by a predetermined distance orthogonally to the active region 100, the field region 200 and the dummy active region 300 are formed on the active regions 100 . The drain select transistor DST is arranged outside the first word line WL1 and the source select transistor SST is arranged outside the nth word line WLn. The plurality of word lines WL1, WL2, ..., WLn including the source select transistor SST and the drain select transistor DST are connected in series to each other to form one cell string. As described above, The above cell string structure is continuously repeated continuously. A drain contact (DCT) is disposed above the active region 100 between the drain select transistors DST of the adjacent cell strings and an active region 100 between the source select transistors SST of the adjacent cell strings. And a common source line CSL is disposed on the upper portion. Here, the common source line CSL is not arranged in about three dummy active regions 300 on both sides of the well pickup W among the dummy active region 300 patterns, but three or more dummy active regions 300 Are disposed on the active region 100 except for the common source line CSL and arranged in a shorter form by a distance of about three dummy active regions 300 compared to the common source line CSL. An ion implantation mask M for providing a well pickup W region to a p-type region is formed in a well pickup region W by arranging a well pickup W between common source lines CSL, In the remaining portions.

As described above, by disposing the common source line CSL in a shorter form by the distance of about three dummy active regions 300 compared with the conventional method, the ion implantation process in the p-type ion implantation process using the ion implantation mask (M) The p-type ions are injected into the dummy active region 300 adjacent to the well pickup W region so that the bias of the common source line CSL is applied to the p-type dummy active region 300. [ It is possible to prevent the light from being coupled to the well pickup W through the light source 300. The dummy active region 300 is formed in the field region 200 where the well pickup W is formed in the same manner as the active region 100 and the dummy active region 300 in the region where the well pick- The contact resistance generated in the dummy active region 300 of the well pickup W region can be reduced by making the width of the well region W wider than the width of the active region 100. [

6 is a layout diagram illustrating a NAND flash memory device according to a third embodiment of the present invention.

Referring to FIG. 6, in the NAND type flash memory device, the active regions 500 in which the channel of the memory cell transistor and the source and the drain are to be formed are repeated in parallel with the field region 600, and the well pickup W is formed The dummy active regions 700 are repeated in parallel with the field regions 600 in the wide field region 600 'between the active regions 500. Here, the dummy active region 700 is formed to have the same width as that of the active region 500 except for the region where the p-type dopant is implanted, including the well pickup W. A plurality of word lines WL1, WL2, ..., WLn formed so as to be spaced apart from each other by a predetermined distance orthogonally to the active region 500, the field region 600, and the dummy active region 700 are formed on the active regions 500 . The drain select transistor DST is arranged outside the first word line WL1 and the source select transistor SST is arranged outside the nth word line WLn. The plurality of word lines WL1, WL2, ..., WLn including the source select transistor SST and the drain select transistor DST are connected in series to each other to form one cell string. As described above, The above cell string structure is continuously repeated continuously. A drain contact (DCT) is disposed above the active region 500 between the drain select transistors DST of the adjacent cell strings and an active region 500 between the source select transistors SST of the adjacent cell strings. And a common source line CSL is disposed on the upper portion. Here, the common source line CSL is not arranged in about three dummy active regions 700 among the dummy active region 700 patterns on both sides of the well pickup W, but three or more dummy active regions 700 Are disposed on the active region 500 except for the common source line CSL and arranged in a shorter form by the distance of about three dummy active regions 700 than the common source line CSL. An ion implantation mask M for providing a well pickup W region to a p-type region is formed in a well pickup region W by arranging a well pickup W between common source lines CSL, In the remaining portions. At this time, the dummy active region 700 is not formed in the region where the ion implantation mask M is disposed.

As described above, by disposing the common source line CSL in a shorter form by the distance of about three dummy active regions 700 compared with the conventional one, ion implantation is performed in the p-type ion implantation process using the ion implantation mask (M) The p-type ions are injected into the dummy active region 700 adjacent to the well pickup region W so that the bias of the common source line CSL is applied to the p-type dummy active region 700. [ It is possible to prevent the light from being coupled to the well pickup W through the light source 700. The dummy active region 700 is formed in the field region 600 where the well pickup W is formed in the same manner as the active region 500 so that the dummy active region 700 in the dummy active region 700 of the well pickup The contact resistance can be reduced.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

The effects of the present invention are as follows.

First, by disposing the common source line in a shorter form by the distance of about three dummy active regions compared to the conventional one, when the ion implantation mask is moved in the i-line in the p-type ion implantation process using the ion implantation mask, P-type ions are also injected into the dummy active region adjacent to the region so that the bias of the common source line can be prevented from being connected to the well pickup through the p-type dummy active region.

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Secondly, by forming the dummy active region in the field region where the well pickup is formed in the same manner, the contact resistance occurring in the dummy active region of the well pickup region can be reduced.

Third, by forming the dummy active region in the field region in which the well pickup is formed, the EFH in the field region is prevented from being lowered, and the EFH fluctuation is improved, so that the fail ratio due to cell distribution and stress test can be lowered .

Fourth, the distance between the control gate and the well can be secured by suppressing the EFH in the field region from being lowered.

Fifth, a distance between the control gate and the well is secured to improve the capacitance, thereby improving the bias reduction phenomenon applied to the control gate during cell operation.

Sixth, the disturb characteristics, the retention characteristics, and the cycling characteristics of the cell can be improved by improving the characteristics.

Seventh, the process can be simplified by not performing the close mask process formed on the upper part of the element isolation film in the well pickup area in order to prevent the element isolation film in the well pickup area from being lost.

Claims (5)

A dummy active region formed in the semiconductor substrate such that active regions are repeated in parallel with the field regions, respectively, and a field region having a wide width between the active regions is formed in parallel with the field region; A plurality of word lines formed on the semiconductor substrate and source select transistor and drain select transistors formed on both sides of the plurality of word lines; A common source line formed between the source select transistors; A well pick-up disposed between the common source lines; And And an ion implantation mask disposed at a remaining portion except for the well pickup region for performing an ion implantation process to make the well pickup region into a p-type region. The method according to claim 1, Wherein the dummy active region has the same size as the width of the active region. The method according to claim 1, The common source line is not arranged in three or more dummy active regions on the both sides of the well pickup among the dummy active regions and is disposed in the upper portion of the active region excluding three or more dummy active regions, NAND flash memory device according to claim 1, The method according to claim 1, Wherein the dummy active region has the same size as the width of the active region and the width of the dummy active region in the region where the well pickup is formed has a width wider than the width of the active region. The method according to claim 1, Wherein the dummy active region has a width equal to the width of the active region and is formed in a region except for an open region due to the ion implantation mask.

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