KR20080092543A - Flash memory device and a method of manufacturing thesame - Google Patents

Abstract

A flash memory device and a manufacturing method thereof are provided to form uniformly a distribution of threshold voltage by increasing a coupling ratio of an outermost memory cell. A tunnel insulating layer(101) and a floating gate conduction layer(102) are sequentially stacked on a semiconductor substrate(100). The floating gate conduction layer formed on a selective transistor region and a region including memory cells except for an outermost memory cell adjacent to a selective transistor. A dielectric layer(106), a control gate conduction layer(107), and a metal layer(108) are sequentially stacked on the entire structure including the floating gate conduction layer. A plurality of memory cell gate patterns including the outermost memory cell are formed by etching the metal layer, the control gate conduction layer, the dielectric layer, the floating gate conduction layer, and the tunnel insulating layer. The height of the gate pattern of the outermost memory cell is higher than the height of the gate patterns of the residual memory cells.

Description

Flash memory device and a method of manufacturing the same

1 is a cross-sectional view of a device for describing a flash memory device according to the prior art.

2 to FIG. 2 are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

<Description of the symbols for the main parts of the drawings>

100 semiconductor substrate 101 tunnel insulating film

102 insulating film for floating gate 103 first insulating film for hard mask

104: second insulating film for hard mask 105: photoresist pattern

106: dielectric film 107: conductive film for control gate

108: metal gate layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device and a method for manufacturing the same, and more particularly, to a flash memory device capable of maintaining a constant voltage of a flash memory cell and a method for manufacturing the same.

The semiconductor memory is classified into a volatile memory in which stored information disappears as the supply of electricity is interrupted, and a non-volatile memory that can maintain information even when the supply of electricity is interrupted. The nonvolatile memory includes erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EPROM), and flash memory.

Flash memory is classified into a NOR type and a NAND type according to a cell configuration. The cell array area of the NAND flash memory is composed of a plurality of strings, and 16 or 32 cells are connected to one string. Each string consists of a string select transistor connected in series, a plurality of cell transistors, and a ground select transistor.

1 is a cross-sectional view of a device for describing a flash memory device according to the prior art.

Referring to FIG. 1, the tunnel insulating film 11, the floating gate conductive film 12, the dielectric film 13, the control gate conductive film 14, the metal gate layer 15, and the like are disposed on the semiconductor substrate 10. And the hard mask layer 16 are sequentially stacked. Subsequently, an etching process is performed to deposit the drain select transistors DSL, the source select transistors SSL, and the stacked layers.

A plurality of memory cells WL0 to WL31 are formed between the drain select transistor DSL and the source select transistor SSL.

2A and 2B are distribution charts illustrating distributions of program and erase threshold voltages of a flash memory device according to the related art.

As the degree of integration of semiconductor devices increases, the size of memory cells of flash memory devices also decreases. As a result, the coupling ratio of the memory cell is proportionally smaller, and the threshold voltage Vt of the outermost cell (WL0 and WL31 of FIG. 1) is relatively small due to the interference effect of the neighboring cells during the program operation of the cell. This is because the voltage applied to the drain select transistor DSL and the source select transistor SSL affects the outermost cell when the outermost cell is programmed or erased compared to other cells, whereas the remaining cells WL1 to WL30 are This is caused by the effect of interference by memory cells of the same structure. As a result, as shown in FIGS. 2A and 2B, the threshold voltage distribution is changed during the program and erase operations between the outermost cell and the remaining cells, resulting in a failure of device operation.

The technical problem to be achieved by the present invention is to deposit a conductive film for a floating gate on a semiconductor substrate, and then to etch a conductive film for a floating gate formed on a memory cell region except a region where the outermost memory cells are formed to a predetermined depth, and then remove the dielectric film. The present invention provides a flash memory device capable of uniformly forming a threshold voltage distribution of a flash memory device by increasing a coupling ratio of an outermost memory cell, and a method of forming the same.

A flash memory device according to an embodiment of the present invention includes a drain select transistor and a source select transistor formed on a semiconductor substrate, and a plurality of memory cells formed in a space between the drain select transistor and the source select transistor. The height of the outermost memory cells adjacent to the drain select transistor and the source select transistor among the plurality of memory cells is higher than the height of the remaining plurality of memory cells.

The plurality of memory cells are sequentially stacked with a tunnel insulating film, a floating gate conductive film, a dielectric film, a control gate conductive film, and a metal gate layer, and the thickness of the floating gate conductive film of the outermost memory cell is the remaining thickness. It is thicker than a thickness of the conductive film for the floating gate of the plurality of memory cells.

The thickness of the floating gate conductive film of the outermost memory cell is 10/9 to 2 times thicker than the thickness of the floating gate conductive film of the remaining plurality of memory cells.

A method of manufacturing a flash memory device according to an embodiment of the present invention comprises the steps of sequentially stacking a tunnel insulating film and a conductive film for a floating gate on a semiconductor substrate, a plurality of memory cells except the outermost memory cells of the semiconductor substrate Etching the conductive film for the floating gate formed on the formed region, sequentially depositing a dielectric film, a control gate conductive film, and a metal layer on the entire structure including the floating gate conductive film, and the metal layer And sequentially etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer to form a plurality of memory cell gate patterns including the outermost memory cell.

In the etching of the conductive film for the floating gate, the thickness of the conductive film for the floating gate to be etched is 1/10 to 1/2 of the total thickness of the conductive film for the floating gate.

The etching of the conductive film for the floating gate may include sequentially stacking a first insulating film for a hard mask and a second insulating film for a hard mask on the tunnel insulating film, and patterning the first and second insulating films for the hard mask. And etching the floating gate conductive layer by an etching process using the patterned first and second insulating layers for the hard mask, and removing the patterned first and second insulating layers for the hard mask.

The first insulating film for the hard mask is formed of a SiON film, the second insulating film for the hard mask is formed of an amorphous carbon film, and the etching process is performed by a wet etching process using CHF 3 and O 2.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. It is provided to inform you.

3 to 6 are cross-sectional views of devices for describing a method of manufacturing a flash memory device according to an embodiment of the present invention.

Referring to FIG. 3, a tunnel insulating film 101 is formed on the semiconductor substrate 100. The tunnel insulating film 101 is preferably formed of an oxide film. The tunnel insulating film 101 is deposited by using a wet oxidation process, and the N2O annealing process is performed in a subsequent step to incorporate nitrogen inside the tunnel insulating film 101 to reduce trap density. It is desirable to improve the reliability.

Thereafter, the floating gate conductive film 102 is formed over the entire structure including the tunnel insulating film 101. The floating gate conductive film 102 is preferably formed of a polysilicon film. The floating gate conductive film 102 is preferably formed of a double film composed of an amorphous polysilicon film containing no impurities and a polysilicon film containing impurities.

The first insulating film 103 for hard mask and the second insulating film 104 for hard mask are sequentially stacked on the entire structure including the floating gate conductive film 102. It is preferable that the first insulating film 103 for hard mast is formed of an amorphous carbon film, and the second insulating film 104 for hard mask is formed of a SiON film. Thereafter, the photoresist material is coated on the entire structure including the second insulating film 104 for hard mask, followed by exposure and development processes to form the photoresist pattern 105. The photoresist pattern 105 is preferably formed to include a selection transistor (drain select transistor and source select transistor) of a flash memory device formed in a subsequent process and a region in which outermost memory cells adjacent to the select transistor are formed.

Referring to FIG. 4, a hard mask pattern is formed by sequentially etching the first insulating film 103 for a hard mask and the second insulating film 104 for a hard mask by an etching process using a photoresist pattern. Thereafter, an etching process using a hard mask pattern is performed to etch the exposed floating gate conductive film 102. In this case, the etching process may be performed by adjusting the etching amount so that the tunnel oxide film 101 is not exposed. In this case, the etching of the floating gate conductive film 102 may be performed to be 1/2 to 1/10 of the thickness of the entire floating gate conductive film 102. The etching process may be performed by using a wet etching process using CHF 3 and O 2 as an etching agent or by using a dry etching process.

Although not shown in the drawings, an element isolation process may be performed before or after the etching process of the floating gate conductive layer 102 to etch the floating gate conductive layer 102 in the bit line direction to form an element isolation layer.

Referring to FIG. 5, an etching process is performed to remove the hard mask pattern. Thereafter, the dielectric film 106 is formed over the entire structure including the conductive film 102 for the floating gate. The dielectric film 106 is preferably formed in an ONO structure in which a first oxide film, a nitride film, and a second oxide film are sequentially stacked. Thereafter, the control gate conductive film 107 and the metal gate layer 108 are sequentially stacked on the entire structure including the dielectric film 106. The control film conductive film 107 is preferably formed of a polysilicon film.

Referring to FIG. 6, an etching process is performed to sequentially perform the metal gate layer 108, the control gate conductive film 107, the dielectric film 106, the floating gate conductive film 102, and the tunnel insulating film 101. Etching to form a plurality of memory cell gate patterns WL0 to WL31 and select transistor gate patterns DSL and SSL. In this case, the outermost memory cell gate patterns WL0 and WL31 and the plurality of memory cell gate patterns WL1 to WL30 adjacent to the selection transistor gate patterns DSL and SSL are as high as the height difference of the conductive film 102 for the floating gate. Has a difference (A). That is, the height of the outermost memory cell gate patterns WL0 and WL31 is higher than the height of the floating gate conductive films 102 of the plurality of memory cell gate patterns WL1 to WL30. The coupling ratio of the memory cells is increased. As a result, the threshold voltage distributions of the outermost memory cell gate patterns WL0 and WL31 and the plurality of memory cell gate patterns WL1 to WL30 can be uniformly formed.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to an embodiment of the present invention, after depositing a conductive film for a floating gate on a semiconductor substrate, after etching the conductive film for a floating gate formed on the memory cell region except a region where the outermost memory cells are formed to a predetermined depth, the dielectric By forming the film, it is possible to uniformly form the threshold voltage distribution of the flash memory device by increasing the coupling ratio of the outermost memory cell.

Claims (10)

A drain select transistor and a source select transistor formed on the semiconductor substrate, and a plurality of memory cells formed between the drain select transistor and the source select transistor, The height of the outermost memory cells adjacent to the drain select transistor and the source select transistor of the plurality of memory cells is higher than the height of the remaining plurality of memory cells. The method of claim 1, And a height of the source and drain select transistors is higher than a height of the remaining plurality of memory cells. The method of claim 2, The height of the floating gate of the outermost memory cells and the source and drain select transistors is higher than the floating gate height of the remaining memory cells. The method of claim 2, The thickness of the outermost memory cells and the floating gate of the source and drain select transistors are 10/9 to 2 times thicker than the thickness of the floating gate of the remaining memory cells. Sequentially depositing a tunnel insulating film and a conductive film for a floating gate on the semiconductor substrate; Etching the conductive film for the floating gate formed on a region where a plurality of memory cells are formed except a selection transistor region of the semiconductor substrate and an outermost memory cell adjacent to the selection transistor; Sequentially stacking a dielectric film, a control gate conductive film, and a metal layer on the entire structure including the floating gate conductive film; And The metal layer, the control gate conductive film, the dielectric film, the floating gate conductive film, and the tunnel insulating film are sequentially etched to form a plurality of memory cell gate patterns including the outermost memory cells, wherein the outermost memory cell is formed. And forming a height of the gate pattern of the memory cell to be higher than that of the other remaining memory cells. The method of claim 5, wherein The etching of the conductive film for the floating gate may include etching a thickness of the conductive film for the floating gate to be 1/10 to 1/2 of the total thickness of the conductive film for the floating gate. The method of claim 5, wherein Etching the conductive film for the floating gate Forming a hard mask film on the tunnel insulating film; Patterning the hard mask layer; Etching the conductive film for the floating gate by an etching process using the patterned hard mask layer; And And removing the patterned hard mask layer. The method of claim 7, wherein And the hard mask film is formed by stacking a first insulating film and a second insulating film. The method of claim 8, And the first insulating film is formed of a SiON film, and the second insulating film is formed of an amorphous carbon film. The method of claim 7, wherein The etching process is a flash memory device manufacturing method using a wet etching process using CHF3 and O2.

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