KR19980026887A - Flash memory device - Google Patents

Abstract

A flash memory device is disclosed. The present invention provides a plurality of cell strings in which cell transistors consisting of a floating gate, an insulating film, and a control gate are connected in series to a semiconductor substrate of a first conductivity type, a string select line formed on one side of the cell string and having string select transistors; And a bit line connected to a drain of the string select transistor and a bit line through a contact hole for a bit line, the flash memory device comprising: a lower portion of an inactive region between the cell strings, between a bit line contact hole, and between the select transistors; A first impurity region of a first conductivity type is formed in the center, and a second impurity region of a first conductivity type is formed adjacent to the first impurity region. The second impurity region is composed of an impurity concentration lower than the first impurity region. The present invention improves the isolation characteristics between cell transistors, string select transistors, and bit line contacts, thereby achieving stable chip operation.

Description

Flash memory device

The present invention relates to a flash memory device, and more particularly to a flash memory device that can improve the separation characteristics between cell transistors, string select transistors and bit line contacts.

There are many kinds of semiconductor memory devices. Among them, RAM (random access memory) type memory devices have the characteristic that the stored information is destroyed when the power supply is interrupted, whereas ROM (read only memory) type memory devices are stored information even when the power supply is interrupted from the outside. It has the property to remain as it is. Therefore, such ROM type memory devices are called nonvolatile memory devices. Among these nonvolatile memories, a flash memory device capable of electrically erasing or writing (programming) information is widely used in computers, memory cards, and the like.

The flash memory device generally includes a cell transistor including a source / drain, a floating gate, and a control gate. The floating gate serves to store data and the control gate serves to adjust the floating gate. Here, a NAND flash memory device will be described among conventional flash memory devices.

1 is a circuit diagram of a conventional NAND flash memory device.

Specifically, a conventional NAND flash memory device includes a cell string D in which cell transistors are connected in series, word lines W / L1 to W / Ln, which are means for selecting the cell transistors, and a cell string. String select lines SSL1 and SSL2 connected to one side and configured with string select transistors, bit lines B / L1, B / L2, and B / L3 connected through drain and bit line contacts of the string select transistor; Ground select lines GSL1 and GSL2 connected to the other side of the cell string and configured of ground select transistors are included. The common source line CSL is connected to the source of the ground select transistor.

In particular, the above-described conventional NAND flash memory device inevitably generates a field transistor between one cell transistor and a cell transistor of an adjacent cell string, and a string select transistor of one string select transistor and an adjacent cell string. . These field transistors exist in different cell strings and interfere with cell operation by degrading separation characteristics between cell transistors and cell transistors connected to the same word line, and adjacent string select transistors. To improve this, the layout method of FIG. 2 has been proposed.

2 is a layout diagram of a conventional NAND flash memory device, and FIGS. 3 and 4 are cross-sectional views taken along lines aa1 and bb1 of FIG. 2.

Specifically, the conventional NAND flash memory device exposes a plurality of active regions 11 arranged in parallel in the Y-direction on a first conductivity type semiconductor substrate and a predetermined portion of the active regions 11. An inactive region 15 is formed between the bit line contact 13 positioned in the active region 11 and each of the active regions 11 arranged in parallel.

In addition, the conventional flash memory device is disposed in the X-direction crossing the active region 11 to serve as the string selection lines SSL1 and SSL2 serving as the gate electrode of the string selection transistor, and the control gate electrode of the cell transistor. The floating gate 19 is formed below the word line 17 and the control gate electrode 17 of the cell transistor to inject hot carriers to determine the type of information while isolating adjacent cell transistors in the X-direction. Is formed. In Fig. 2, reference numerals GSL1 and GSL2 denote ground selection lines, and reference numerals 18 in Figs. 3 and 4 denote insulating films.

Here, reference numeral 21 is a field ion implantation pattern formed after the active region of the flash memory device is formed to expose the region where the cell transistor is formed and to inject the channel stop ion into only the exposed region.

Therefore, in the conventional flash memory device illustrated in FIG. 2, channel stop ions are not implanted by the field ion implantation pattern 21 in inactive regions between bit line contacts and between cell string select transistors.

As a result, in the conventional flash memory device, as shown in FIGS. 3 and 4, only one impurity region 23 is formed in the inactive region between the string select transistors adjacent to each other and between the bit line contacts, so that the isolation characteristics are improved. Because of the weakness, there is a problem in obtaining stable chip operation.

Accordingly, an object of the present invention is to provide a flash memory device capable of improving the isolation characteristics between the above-described cell transistors, string select transistors, and bit line contacts.

1 is a circuit diagram of a conventional NAND flash memory device.

2 is a layout diagram of a conventional NAND flash memory device.

3 and 4 are cross-sectional views taken along aa1 and bb1 of FIG. 2.

5 is a layout diagram of a flash memory device of the present invention.

6 and 7 are cross-sectional views taken along aa1 and bb1 of FIG. 5, respectively.

In order to achieve the above technical problem, the present invention provides a plurality of cell strings in which a cell transistor including a floating gate, an insulating film, and a control gate is connected in series to a semiconductor substrate of a first conductivity type, and is formed on one side of the cell string and is a string. A flash memory device having a string select line having select transistors and a bit line connected through a drain and a bit line contact hole of the string select transistor, the flash memory device comprising: between the cell strings, between the bit line contact holes, and the select line; A first impurity region of a first conductivity type is formed in a lower center of an inactive region between transistors, and a second impurity region of a first conductivity type is formed adjacent to the first impurity region Provide a memory device.

The second impurity region is composed of an impurity concentration lower than the first impurity region.

The present invention improves the isolation characteristics between cell transistors, string select transistors, and bit line contacts, thereby achieving stable chip operation.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a layout diagram of a flash memory device of the present invention, and FIGS. 6 and 7 are cross-sectional views taken along aa1 and bb1 of FIG. 2, respectively.

Specifically, the NAND type flash memory device of the present invention includes a plurality of active regions 31 arranged in parallel in the Y-direction on a first conductive type, for example, a p-type semiconductor substrate, and predetermined portions of the active regions 31. In order to expose the portion, an inactive region (field region 35) is formed between the bit line contact 33 located in the active region 31 and each of the active regions 31 arranged in parallel.

In addition, the flash memory device of the present invention is arranged in the X-direction crossing the active region 31 to serve as string selection lines SSL1 and SSL2 serving as gate electrodes of the selection transistors, and serve as control gate electrodes of the cell transistors. A floating gate 39 is formed below the word line 37 and the control gate electrode 37 of the cell transistor to inject hot carriers to determine the type of information while isolating adjacent cell transistors in the X-direction. Is formed. In Fig. 2, reference numerals GSL1 and GSL2 denote ground selection lines, and in Figs. 6 and 7, reference numeral 38 denotes an insulating film.

Here, reference numeral 41 denotes a field ion implantation pattern provided after the active region of the flash memory device is formed and before the tunnel oxide layer is formed. Unlike the conventional method, a channel is exposed between the bit line contacts and the cell string select transistor. Stop ions can be injected.

Accordingly, in the flash memory device of FIG. 5, channel stop ions are implanted using the field ion implantation pattern 21 even in inactive regions between bit line contacts and between cell string select transistors.

As a result, the flash memory device of the present invention, as shown in Figs. 6 and 7, has a first conductivity type in the lower center of the inactive region between the string select transistors adjacent to each other, between the bit line contacts and between the cell transistors. The first impurity region 45 is formed, and the second impurity region 43 of the first conductivity type is formed adjacent to the first impurity region 45. The second impurity region 43 implants impurities at a concentration lower than that of the first impurity region 45. Therefore, in the flash memory device of the present invention, double impurity regions 43 and 45 are formed under the inactive region, thereby improving separation characteristics.

The present invention is not limited to the above embodiments, and it is apparent that many modifications are possible by those skilled in the art within the technical idea of the present invention.

As described above, in the flash memory device of the present invention, stable chip operation may be obtained by improving separation characteristics between cell transistors, string select transistors, and bit line contacts.

Claims (2)

A plurality of cell strings having a cell transistor formed of a floating gate, an insulating film, and a control gate in series with a first conductive semiconductor substrate, a string select line formed at one side of the cell string and having string select transistors, and the string A flash memory device having a bit line connected through a drain of a select transistor and a contact hole for a bit line, the flash memory device comprising: A first impurity region of a first conductivity type is formed in the lower center of the inactive region between the cell strings, between the bit line contact holes, and between the selection transistors, and has a first conductivity adjacent to the first impurity region. A second impurity region of a type is formed. The flash memory device of claim 1, wherein the second impurity region has a lower impurity concentration than the first impurity region.