KR20080037592A - Non-volatile semiconductor memory and manufacturing method of the same - Google Patents

Abstract

A nonvolatile semiconductor memory and a method for manufacturing the same are provided to prevent the short between a memory transistor and a select transistor by preventing the remaining of foreign substances. A semiconductor substrate(SB) has a main surface. Plural memory transistors(MT) have a floating gate(FG) and a control gate(CG) which are laminated on the main surface. Plural select transistors(ST) have a lower gate layer(G2) and an upper gate layer(G1) which are laminated on the main surface. Each select transistor is included in a memory cell(MC) together with one of plural memory transistors. The lower gate layers are separated at every select transistor. The upper gate layer is shared in the plural select transistors. The upper gate layer is electrically connected to each of the lower gate layers of the plural select transistors. The lower gate layer and the upper gate layer are directly contacted to each other.

Description

Nonvolatile semiconductor memory device and manufacturing method thereof {NON-VOLATILE SEMICONDUCTOR MEMORY AND MANUFACTURING METHOD OF THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a method of manufacturing the same, and more particularly, to a nonvolatile semiconductor memory device having a floating gate and a control gate and a method of manufacturing the same.

Some memory cells of a nonvolatile semiconductor memory device have a floating gate transistor (memory transistor) and an isolation transistor (selection transistor) connected in series with each other. Some floating gate transistors (memory transistors) have floating gates and control gates (control gates). Some separation transistors (selection transistors) have a separation gate (select gate).

The plurality of separation transistors (selection transistors) share a separation gate (select gate). Therefore, the plurality of isolation transistors (selection transistors) are turned on and off by controlling the potential of one isolation gate (select gate).

When the isolation transistor is turned off, the memory cell having this isolation transistor (selection transistor) is cut off from the source line. Therefore, whether or not the floating gate transistor (memory transistor) of this memory cell is in an over erased state does not affect the reading of the data. In this way, the read error due to over erasing is prevented by the function of the isolation transistor.

As a manufacturing method of the said nonvolatile semiconductor memory device, the following process is provided. First, a tunnel dielectric layer is formed on a semiconductor substrate. Subsequently, a first conductive layer is formed on this insulating layer. Next, a mask made of a photoresist is formed on the first conductive layer by the lithography method. Subsequently, etching is performed using this mask so that a separation gate (select gate) and a floating gate made of the first conductive layer are simultaneously patterned. Next, an interlayer dielectric layer (insulating layer) and a second conductive layer are formed on the entire surface of the semiconductor substrate. Subsequently, patterning of the second conductive layer is performed so that the second conductive layer remains only in part of the floating gate transistor (memory transistor), so that a control gate (control gate) is formed.

As a technique of such a nonvolatile semiconductor memory device, there is a Japanese Laid-Open Patent Publication No. 7-297304, for example.

In the above conventional example, the separation gate (select gate) is composed of one layer of film composed of the first conductive layer. In order for this isolation gate (select gate) to be shared by a plurality of isolation transistors (selection transistors), the isolation gate (select gate) must be patterned in a straight line so as to conform to the arrangement of the plurality of isolation transistors.

For this reason, when the isolation gate (select gate) and the floating gate are formed in the above process, the pattern of the opening of the mask used for etching should be a pattern avoiding the region where the isolation gate (select gate) extends linearly. For this reason, the opening pattern cannot be a simple straight shape, but becomes a pattern having a large number of ends.

In the fine pattern formation technique, it is generally difficult to accurately form the end portion rather than to form the intermediate portion of the linear pattern. For this reason, when the pattern of the opening part of the said mask is formed, the magnitude | size of the edge part of an opening pattern may become larger than desired. When the etching of the first conductive layer is performed using such a mask, the first conductive layer is locally largely etched at the end of the opening pattern.

When the interlayer dielectric layer (insulating layer) and the second conductive layer are formed on the recessed portions formed by large local etching, a large step occurs on the film surface.

In this stepped portion, foreign matter is likely to remain in the manufacturing process of the nonvolatile semiconductor memory device. If this foreign matter acts as a mask in the etching step, the etching of the second conductive layer may be incomplete at a position between the neighboring floating gate transistor (memory transistor) and the isolation transistor (selection transistor). As a result, there has been a problem that a short circuit between the floating gate transistor (memory transistor) and the isolation transistor (selection transistor) may occur.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and an object thereof is to provide a nonvolatile semiconductor memory device capable of preventing a short circuit between a memory transistor and a selection transistor caused by foreign matters in a manufacturing process, and a manufacturing method thereof. .

A nonvolatile semiconductor memory device according to one embodiment of the present invention includes a semiconductor substrate having a main surface, a plurality of memory transistors, and a plurality of selection transistors. Each of the plurality of memory transistors has a floating gate and a control gate formed by laminating each other on a main surface. Each of the plurality of select transistors has a lower gate layer and an upper gate layer formed on the main surface by laminating each other, and is included in a memory cell together with one of the plurality of memory transistors. The lower gate layer is separated for each of the plurality of select transistors. The upper gate layer is shared by the plurality of select transistors and is electrically connected to the lower gate layers of each of the plurality of select transistors. A method of manufacturing a nonvolatile semiconductor memory device according to one embodiment of the present invention is a method of manufacturing a nonvolatile semiconductor memory device having a plurality of memory cells, and includes the following steps. First, a first insulating layer is formed on a semiconductor substrate. The first conductive layer is formed on this first insulating layer. The first conductive layer is patterned so that each forms a plurality of band shapes extending over a region where the plurality of memory cells are formed. A second insulating layer is formed on the first conductive layer. A plurality of openings are formed in the second insulating layer, each of which exposes the surface of the first conductive layer and crosses a plurality of strips. A second conductive layer is formed to electrically connect with the first conductive layer through the opening and to cover the second insulating layer. A lamination pattern comprising a portion of the first conductive layer and a portion of the second conductive layer electrically insulated from each other by the second insulating layer, and a first conductive formed along the opening and electrically connected to each other at the portion of the opening; The second conductive layer and the first conductive layer are patterned such that a lamination pattern including a portion of the layer and a portion of the second conductive layer is formed.

According to the nonvolatile semiconductor memory device and the manufacturing method thereof of this embodiment, the selection transistor has a lower gate layer and an upper gate layer. The lower gate layer is separated for each select transistor and electrically connected to the upper gate layer shared by the plurality of select transistors. For this reason, the lower gate layer need not be linearly patterned to follow the plurality of select transistors. Therefore, it is possible to extend the opening of the mask for patterning the floating gate and the lower gate layer over the select transistor. Therefore, the openings can be made in a straight line shape, and the openings can be prevented from having an end portion at the middle portion of the memory cell array region. Therefore, it is possible to prevent the remaining of foreign matter which is likely to occur at the position where the end of the opening has been. This can prevent the foreign matter from affecting the etching process during the manufacture of the nonvolatile semiconductor memory device and short-circuit between the memory transistor and the selection transistor.

The above and other objects, features, aspects and advantages of the present invention will become apparent from the following detailed description of the invention which is understood in connection with the accompanying drawings.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described according to drawing.

(Example 1)

With reference to FIG. 1, the some memory cell MC is arrange | positioned in the matrix form on the surface of the semiconductor substrate SB which is a p-type silicon substrate, for example. Each memory cell MC has a selection transistor ST and a memory transistor MT provided adjacent to each other in a column direction (vertical direction in FIG. 1).

On the surface of the semiconductor substrate SB, an inter-element isolation layer LCS is formed in a straight line along a direction crossing the extending direction of the upper gate layer G1. The select transistors ST adjacent to each other are separated by the isolation layer LCS between the elements, and the memory transistors MT adjacent to each other are separated.

1 to 4, each select transistor ST has a stacked structure of an upper gate layer G1 and a lower gate layer G2 formed separately for each of the select transistors ST. The upper gate layer G1 extends in the row direction (the transverse direction in FIG. 1) according to the arrangement of the plurality of selection transistors ST.

Although insulating layer I1 (FIG. 4) is formed between lower gate layer G2 and upper gate layer G1, this insulating layer I1 has opening OP (FIG. 1). In this opening OP, the lower gate layer G2 and the upper gate layer G1 are in direct contact with each other, as shown in FIG. 4. For this reason, the upper gate layer G1 is shared by the plurality of select transistors ST and electrically connected to the lower gate layer G2 of each of the plurality of select transistors ST. The lower gate layer G2 and the semiconductor substrate SB are insulated by the insulating layer I2 (FIGS. 2 and 4). In addition, a mask HS is formed on the upper gate layer G1.

Each memory transistor MT has a stacked structure of a control gate CG and a floating gate FG formed separately for each memory transistor MT. The control gate CG is shared by the plurality of memory transistors MT arranged in the row direction. The floating gate FG and the control gate CG are insulated by the insulating layer IC (FIGS. 3 and 4). In addition, the floating gate FG and the semiconductor substrate SB are insulated by the insulating layer IF (FIGS. 3 and 4). Moreover, the mask HM is formed on the control gate CG.

Mainly referring to FIG. 4, n-type impurity regions DB, DM, and DS are formed on the semiconductor substrate SB.

The lower gate layer G2 of the selection transistor ST is positioned between the impurity region DM and the impurity region DS and faces the semiconductor substrate SB through the insulating layer I2. In addition, since the upper gate layer G1 and the lower gate layer G2 are short-circuited, the upper gate layer G1 functions as a simple wiring portion. Accordingly, the selection transistor ST can function as a single gate type MOS (Metal 0xide Semiconductor) transistor.

The floating gate FG of the memory transistor MT is positioned between the impurity region DM and the impurity region DB and faces the semiconductor substrate SB via the insulating layer IF. The control gate CG and the floating gate FG are insulated by the insulating layer IC. As a result, the memory transistor MT has a structure of a stacked gate type MOS transistor, and can store information by controlling the accumulated charge of the floating gate FG.

In one memory cell MC, the selection transistor ST and the memory transistor MT share the impurity region DM. As a result, the memory cell MC has a structure in which the memory transistor MT and the selection transistor ST are electrically connected in series.

The bit line contact BC is formed on the upper surface of the impurity region DB. The source line contact SC is formed on the upper surface of the impurity region DS. Accordingly, in the memory transistor MT and the selection transistor ST connected in series, which constitute one memory cell MC, the memory transistor MT side is connected to the bit line contact BC, and the selection transistor ST Is connected to the source line contact SC.

The bit line contact BC is connected to a bit line BL made of aluminum wiring or the like. In addition, the source line contact SC is connected to the source line SL made of aluminum wiring or the like.

Referring to Fig. 6, in the memory cell array, BLO, BL1, BL2 are formed as a plurality of bit lines BL extending in the column direction (vertical direction in the drawing). Further, selection lines SLL0 and SLL1 extending in the row direction (horizontal direction in the drawing), and word lines WDL0 and WDL1 are formed. In the memory cell array, a common source line SL is formed.

Among the plurality of bit lines BL, for example, in the bit line BL0, the memory transistor side of the plurality of memory cells MC is connected to the bit line BL0 via the bit line contact BC. Two memory cells MC neighboring in the column direction (vertical direction in the figure) share the source line contact SC formed on the selection transistor ST side. This source line contact SC is connected to the source line SL.

Mainly referring to FIG. 6, of the plurality of word lines, for example, the word line WDL0 is one control gate CG (FIG. 1), and is arranged in the row direction (the horizontal direction in FIGS. 1 and 6). Are shared by the plurality of memory transistors MT.

Among the plurality of selection lines, for example, the selection line SLL0 is one upper gate layer G1 (FIG. 1) and includes a plurality of selection transistors arranged in the row direction (the horizontal direction in FIGS. 1 and 6). Shared by ST). The upper gate layer G1 is electrically connected to the lower gate layer G2 (FIG. 4) in each of the select transistors ST. For this reason, by setting the voltage level of the upper gate layer G1, the voltage levels of the plurality of lower gate layers G2 electrically connected to the upper gate layer G1 are set. Since the lower gate layer G2 functions as a select gate of the selection transistor ST, the voltage level of the selection line SLL0 turns on / off the plurality of selection transistors ST in a row (see FIG. 6). Control in each direction).

The memory cell MC in which the selection transistor ST is turned off is cut off between the bit line BL and the source line SL regardless of the state of the memory transistor MT. Therefore, even if the memory transistor MT is in an over-erased state, the pair of select transistors ST are turned off, thereby not adversely affecting data reading.

In addition, as shown in FIG. 2, the length dimension of the lower gate layer G2 and the floating gate FG in the direction along the extending direction of the upper gate layer G1 (the horizontal direction in FIGS. 1 to 3) ( W) is formed in the same way.

In addition, as shown in FIG. 5, the length dimension of the lower gate layer G2 and the floating gate FG in the direction (vertical direction in FIGS. 1 and 4) along the direction crossing the upper gate layer G1 ( L1) is formed similarly.

Next, the manufacturing method of the nonvolatile semiconductor memory device in this embodiment will be described.

Referring to FIG. 7, for example, an interlayer isolation layer LCS extending in the same direction at a predetermined interval on a semiconductor substrate SB, which is a p-type silicon substrate, is, for example, a LOCOS (Local 0xidation of Silicon) method. Is formed by.

Referring to FIG. 8, an insulating layer (first insulating layer) IS is formed on the upper surface of the semiconductor substrate SB by, for example, a thermal oxidation method.

With reference to FIG. 9, the conductive layer (1st conductive layer) AS which consists of amorphous silicon to which impurity was added, for example is formed on the semiconductor substrate SB.

Referring to FIG. 10, along the region inserted into the interlayer isolation layer LCS, a photoresist P1 having a linear opening is formed by a photolithography technique. This photoresist P1 contains an acid component.

With reference to FIG. 11, the water-soluble upper layer agent 0S is apply | coated on the semiconductor substrate SB so that photoresist P1 may be coat | covered. This water-soluble supernatant (0S) has the property of reacting with an acid and curing at high temperatures.

12, the semiconductor substrate SB is heat treated. Accordingly, at the interface between the photoresist P1 (dashed line in the drawing) and the water-soluble supernatant 0S, a part of the water-soluble supernatant 0S reacts with the acid contained in the photoresist P1 (dashed line in the drawing). Hardened. This cured material is integrated with photoresist P1 (broken portion in the figure) to form photoresist P1R.

Referring to Figure 13, the uncured water soluble supernatant (OS) is removed. As a result, the photoresist P1R having an opening smaller in size than the photoresist P1 shown in FIG. 10 can be obtained. The photoresist P1R has a width W in a direction intersecting with the extending direction of the inter-element isolation layer LCS (Fig. 13), and the extension of the inter-element separation layer LCS. Extending in a straight line in the direction. Therefore, the opening of photoresist P1R extends linearly along the extension direction of inter-element isolation layer LCS.

Referring to FIG. 14, patterning (first patterning process) of the conductive layer AS is performed by etching using the resist P1R as a mask. Subsequently, the resist P1R is removed.

Mainly referring to FIG. 15, by the patterning, a conductive layer AS is formed over a portion between the inter-element isolation layers LCS and has a pattern along the extension direction of the inter-element isolation layer LCS. The pattern of the conductive layer AS is a pattern including the plurality of floating gates FG and the lower gate layer G2 along the column direction (vertical direction in FIG. 1). That is, it is a pattern extending in a strip | belt shape along the formation direction of several memory cell along a column direction (the longitudinal direction of FIG. 1).

With reference to FIG. 16, the insulating layer (2nd insulating layer) 10 which consists of ONO (0xide Nitride 0xide) film, for example is formed in the whole surface on the semiconductor substrate SB.

Mainly referring to FIGS. 17A to 17C, a photoresist P2 is selectively formed on the semiconductor substrate SB by photolithography. The plurality of openings of the photoresist P2 correspond to the positions of the openings OP in FIG. 1. Subsequently, the insulating layer IO is patterned by etching using this photoresist P2 as a mask. Then, photoresist P2 is removed.

The conductive layer (at the position of the plurality of openings OP (FIG. 1) of the insulating layer IO is mainly formed by the pattern of the insulating layer IO described above with reference to FIGS. 18A to 18C. Surface of AS) is exposed. This opening part OP is formed so that it may extend in the direction which cross | intersects the strip | belt-shaped extension direction formed in FIG.

19 (a) to 19 (c), a conductive layer PS made of polysilicon with impurity added, for example, having a thickness of 100 to 130 nm is formed on the entire surface of the semiconductor substrate SB. Subsequently, for example, the conductive layer WS made of tungsten silicide having a thickness of 70 to 100 nm is formed by, for example, the CVD method. Then, the hard mask layer HD which is a silicon oxide film with a thickness of 180-220 nm is formed, for example. As this forming method, for example, a CVD method using TEOS (Tetra Ethyl 0rtho Silicate) as a starting material can be used.

Mainly referring to FIGS. 20A to 20C, the photoresist P3 is selectively formed on the hard mask layer HD described above. The formation region of the photoresist P3 is a region where the control gate CG and the upper gate layer G1 are formed in FIG. 1. Subsequently, the hard mask layer HD is patterned using this photoresist P3. Thereafter, photoresist P3 is removed.

Mainly referring to FIGS. 21A to 21C, a pattern is applied to the hard mask layer HD by the above-described patterning, whereby the mask HS and the mask HM are formed. The mask HS is formed in a region where the upper gate layer G1 is formed in FIG. 1. The mask HM is formed in the region where the control gate CG is formed in FIG. Subsequently, using the masks HS and HM as masks, etching (second patterning process) is performed until the unmasked regions reach the surface of the semiconductor substrate SB.

Referring to Figs. 22A to 22C, two stack gate structures are formed by etching using the masks HS and HM.

One stack gate structure (the stack structure at both ends of FIG. 22C) has an insulating layer IF, a floating gate FG, an insulating layer IC, and a conductive layer on the semiconductor substrate SB. (CGp), conductive layer (CGw), and mask (HM) are stacked in this order to form. The conductive layer CGp and the conductive layer CGw together form the control gate CG. The floating gate FG and the control gate CG are insulated by the insulating layer IC.

The other stack gate structure (two stack structures located in the center of FIG. 22C) has an insulating layer I1, a lower gate layer G2, and an insulating layer (on the semiconductor substrate SB). I1), the conductive layer Glp, the conductive layer Glw, and the mask HS are laminated and formed in this order. The insulating layer I1 has an opening in a region corresponding to the opening OP in FIG. 1. For this reason, the upper gate layer G1 and the lower gate layer G2 are electrically connected at this opening.

Referring to FIGS. 23A to 23C, ion implantation is performed in the semiconductor substrate SB. At this time, the masks HM and HS become masks. As a result, n-type impurity regions DB, DM, and DS are formed on the upper surface of the semiconductor substrate SB.

Referring to Fig. 4, an interlayer insulating layer (not shown) is formed, and bit line contacts BC and source line contacts SC are formed on the interlayer insulating layers. The bit line contact BC is connected to the bit line BL, and the source line contact SC is connected to the source line SL. As described above, the nonvolatile semiconductor memory device according to the present embodiment is manufactured.

24, 25 and 27, the selection transistor STC is a gate electrode, and the gate extends over the plurality of selection transistors STC in the row direction (horizontal direction in FIGS. 24 and 25). It has a layer G2C. The gate layer G2C and the semiconductor substrate SB are insulated by the insulating layer I2C.

In addition, since the structure of this comparative example other than is substantially the same as the structure of Example 1 mentioned above, the same code | symbol is attached | subjected about the same element and the description is abbreviate | omitted.

In this comparative example, the inter-gate region R (FIG. 24), which is the region between the gate layer G2C and the control gate CG on the inter-element isolation layer LCS, is conductive. Material remains, and product defects in which the gate layer G2C and the control gate CG are shorted are likely to occur.

The manufacturing process by which this manufacturing defect will arise is demonstrated below. In addition, since the manufacturing method of this comparative example and the manufacturing method of this Example are the same until the manufacturing process shown in FIG. 9, the process after that is demonstrated.

Mainly referring to FIGS. 29 and 30, the photoresist P1C is selectively formed on the upper surface of the conductive layer AS (FIG. 9) formed on the semiconductor substrate SB by using a photolithography technique.

At this time, unlike the present embodiment described above, in the present comparative example, the photoresist P1C is also formed in a portion (part C of FIG. 29) over the inter-element isolation layer LCS. For this reason, the opening part (surface in which the conductive layer AS is exposed) of the photoresist P1C does not have a linear shape, and has a plurality of end portions E. FIG.

As shown in FIG. 29, the position of the end portion E coincides with the position of the inter-gate region R (FIG. 24).

Subsequently, as in the processes of Figs. 11 to 13 of the present embodiment described above, coating, curing, and removal of the uncured water-soluble supernatant (0S) are performed. As a result, the opening of the photoresist P1C is reduced.

Mainly referring to FIGS. 31, 32 (a) and 32 (b), the photoresist P1RC having the opening smaller than the photoresist P1C (dashed line in the drawing) is formed by the above-described reduction process of the opening. Is formed. As shown in FIG. 31, the opening is wider in a circular shape at the end portion ER than in the middle portion. This is difficult to apply the water-soluble supernatant OS to the end portion E (Fig. 29) of the opening portion of the photoresist P1C (Fig. 29), and the reduction effect of the opening portion is reduced at the end portion E (Fig. 29). Because.

Subsequently, etching is performed using this photoresist P1RC as a mask, and patterning of the conductive layer AS is performed. Thereafter, photoresist P1RC is removed.

As shown in Fig. 31, the position of this end portion ER coincides with the position of the inter-gate region R (Fig. 24).

Mainly referring to FIGS. 33A and 33B, the pattern of the conductive layer AS is formed by the above-described patterning. The dimension of the direction (intermediate side of the figure) which crosses the interlayer isolation layer LCS of the conductive layer AS is small in FIG. 33 (b) compared with FIG. 33 (a). This is because the cross-sectional position of Fig. 33B is located at the end ER (Fig. 31) of the opening portion of the photoresist P1RC.

Referring to FIGS. 34A and 34B, the insulating layer IO is formed to cover the conductive layer AS. Trench of the insulating layer IO is formed between the patterns of the conductive layer AS which are adjacent. The width dimension of this trench is Wa in FIG. 34 (a) and Wb in FIG. 34 (b). There is a relationship of Wa <Wb between both dimensions.

Mainly referring to FIGS. 35A and 35B, the conductive layers PS and WS and the hard mask layer HD are formed on the insulating layer IO. These film formations are also performed on the trench of the insulating layer I0 mentioned above. For this reason, trenches Sa1 and Sa2 (FIG. 35 (a)) are formed in the hard mask layer HD and the conductive layer WS, respectively, in the portion located in the middle of the opening portion of the photoresist P1RC. Further, trenches Sb1 and Sb2 (FIG. 35 (b)) are formed in the hard mask layer HD and the conductive layer WS in the portion located at the end ER (FIG. 3L) of the opening of the photoresist P1RC. Is formed.

Trench Sb2 becomes a trench larger than trench Sa2. In addition, trench Sb1 becomes a trench larger than trench Sa1. In such a large trench, foreign matter (DST) composed of a photoresist, an oxide film, or the like tends to remain. Below, the case where the foreign material DST (FIG. 35 (b)) remains is demonstrated.

In a similar manner to the above-described present embodiment (Figs. 20 (a) to 20 (c)), the hard mask layer HD is patterned to form a desired mask. Next, using this mask, etching for forming a stacked pattern of the portion of the memory transistor MT is performed.

Referring to FIGS. 36A and 36B, when the stacked pattern forming process of the memory transistor MT is normally performed, both the elements of FIGS. 36A and 36B are inter-elements. Etching is performed to expose the top surface of the separation layer LCS. However, since the foreign matter DST (FIG. 35 (b)) acts as a mask for etching, a portion of the interlayer isolation layer LCS that is not etched and broken remains. That is, the insulating layer I0R which is a residue of the insulating layer I0, and the conductive layer PSR which is a residue of the conductive layer PS remain. This conductive layer PSR is located in the inter-gate region R in FIG. In this case, the cross section along the line XXX_XXXX in FIG. 24 is as shown in FIG. 37, and the conductive layer PSR shorts the gate layer G2C and the control gate CG.

In addition, the position of the conductive layer PSR is shown in FIG.

According to this embodiment, as shown in FIG. 1, the selection transistor ST has two gate layers, an upper gate layer G1 and a lower gate layer G2. The upper gate layer G1 is shared by the plurality of select transistors. In addition, as shown in FIG. 4, the upper gate layer G1 and the lower gate layer G2 are electrically connected in the opening OP part. For this reason, even if the lower gate layer G2 is separated for each of the selection transistors ST, the potentials of the plurality of lower gate layers G2 can be controlled by controlling the potentials of one upper gate layer G1. have.

In addition, since the lower gate layer G2 is separated for each of the selection transistors as described above, as shown in FIG. 13, the openings of the photoresist P1R for patterning the conductive layer AS are inter-elements. It may be formed to extend in a straight line along the extending direction (direction perpendicular to the ground) of the separation layer (LCS). Therefore, the shape which the opening part widened like the edge part ER of the opening part of the photoresist P1RC shown in FIG. 3L which is a comparative example does not generate | occur | produce.

As a result, for example, trenches on the upper surfaces of the hard mask layer HD and the conductive layer WS shown in FIG. 19B are uniformly formed throughout. That is, as shown in Fig. 35 (b) as a comparative example, locally large trenches Sb1 and Sb2 are not formed.

Therefore, it is possible to suppress the foreign matter DST remaining in the trench portion. For this reason, the foreign substance DST acts as a mask at the time of etching the conductive layer PS, and is a part of the conductive layer PS at a position corresponding to the inter-gate region R (FIG. 24) in the comparative example. The remaining of the conductive layer PSR (FIG. 37) can be suppressed. As a result, it is possible to suppress the occurrence of product defects in which the area between the lower gate layer G2 and the control gate CG on the inter-element isolation layer LCS is short-circuited. In addition, in the photoresist P1R (FIG. 13), a water-soluble supernatant OS (FIG. 11) is applied to the photoresist P1 (FIG. 10), and a part of the water-soluble supernatant OS is cured ( 12) is formed. As a result, the dimension of the opening of the mask for etching is refined. This photoresist P1 is different from the photoresist P1C (FIG. 29) and does not have a portion C (FIG. 29) over the interlayer isolation layer LCS. For this reason, a water-soluble upper layer (OS) can be apply | coated uniformly throughout. Therefore, as shown in FIG. 31, the shape of the edge part ER of the opening part of a mask can be prevented from becoming large compared with the intermediate part.

In addition, the lower gate layer G2 of the selection transistor ST and the floating gate FG, which is a lower gate layer of the memory transistor MT, have a conductive layer AS formed on the entire surface of the semiconductor substrate SB (Fig. By patterning for 9), they are formed simultaneously. Accordingly, the manufacturing process can be simplified as compared with the case in which the lower gate layer G2 and the floating gate FG are separately formed.

In addition, the upper gate layer G1 of the selection transistor ST and the control gate CG, which is the upper gate layer of the memory transistor MT, have conductive layers PS and WS formed on the entire surface of the semiconductor substrate SB. By patterning for FIG. 19). Accordingly, the manufacturing process can be simplified as compared with the case in which the upper gate layer G1 and the control gate CG are separately formed.

4, the lower gate layer G2 and the upper gate layer Gl are electrically connected by direct contact. For this reason, in order to electrically connect the lower gate layer G2 and the upper gate layer G1, it is not necessary to perform another film formation.

2 and 3, the length dimension W of the lower gate layer G2 and the floating gate FG is the same along the extending direction (the horizontal direction in the drawing) of the upper gate layer G1. . Therefore, as shown in FIG. 13, the lower gate layer GT2 and the floating gate FG can be patterned by the linear photoresist P1R having the pattern width W. FIG.

In addition, as shown in FIG. 1, the element isolation layer LCS is formed on the semiconductor substrate SB in a straight line along a direction intersecting with an extending direction of the upper gate layer G1. For this reason, in patterning for separating the conductive layer AS on the element isolation layer LCS, the photoresist P1R (Fig. 13) serving as a mask can also be formed in a linear shape.

(Example 2)

Referring to FIG. 39, the configuration of the present embodiment is different from that of the first embodiment in terms of the size of the floating gate FG. That is, the length dimension of the floating gate FG in the direction crossing the extending direction of the upper gate layer G1 (the transverse direction in FIG. 39) is L2, which is smaller than the length dimension L1 of the lower gate layer G2.

The selection transistor ST has a complicated structure in which two gates are in contact with an opening provided in an insulating layer therebetween. On the other hand, the memory transistor MT has a simple stack structure. For this reason, the memory transistor MT is easier to be miniaturized than the selection transistor ST, and the size of the memory transistor MT can be made smaller than that of the selection transistor ST.

In addition, since the structure of this other Example is substantially the same as the structure of Example 1 mentioned above, the same code | symbol is attached | subjected about the same element and the description is abbreviate | omitted.

According to the present embodiment, as shown in FIG. 39, the length of the floating gate FG is smaller than the length of the lower gate layer G2. As a result, the memory transistor MT is miniaturized. Therefore, the storage capacity per unit area of the device can be increased.

While the invention has been described and described in detail, it is intended to be illustrative, and not restrictive, and the scope of the invention is to be clearly understood as interpreted by the appended claims.

1 is a schematic plan view showing a planar layout in a memory cell array of a nonvolatile semiconductor memory device according to the first embodiment of the present invention.

2 to 5 are schematic cross-sectional views corresponding to the II-II, III-III, IV-IV and V-V lines of FIG. 1.

6 is a circuit diagram showing a schematic circuit configuration of a nonvolatile semiconductor memory device according to the first embodiment of the present invention.

7-16 are schematic sectional drawing which shows the 1st-10th process of the manufacturing method of the nonvolatile semiconductor memory device of Example 1 of this invention in order. In addition, the cross-sectional position of these figures corresponds to the position along any one of the II-II and III-III lines of FIG.

17A to 17C are schematic sectional views showing the eleventh step of the manufacturing method of the nonvolatile semiconductor memory device according to the first embodiment of the present invention. In addition, each cross-sectional position of these figures corresponds to the position along each of the II-II, III-III, and IV-IV line | wire of FIG.

18A to 18C are schematic cross-sectional views showing a twelfth step of the method for manufacturing a nonvolatile semiconductor memory device according to the first embodiment of the present invention. In addition, each cross-sectional position of these figures corresponds to the position along each of the II-II, III-III, and IV-IV line | wire of FIG.

19A to 19C are schematic cross-sectional views showing a thirteenth step of the method for manufacturing a nonvolatile semiconductor memory device according to the first embodiment of the present invention. In addition, each cross-sectional position of these figures corresponds to the position along each of the II-II, III-III, and IV-IV line | wire of FIG.

20A to 20C are schematic cross-sectional views showing a fourteenth step of the method for manufacturing a nonvolatile semiconductor memory device according to the first embodiment of the present invention. In addition, each cross-sectional position of these figures corresponds to the position along each of the II-II, III-III, and IV-IV line | wire of FIG.

21A to 21C are schematic cross-sectional views showing a fifteenth step of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention. In addition, each cross-sectional position of these figures corresponds to the position along each of the II-II, III-III, and IV-IV line | wire of FIG.

22A to 22C are schematic cross-sectional views showing a sixteenth step of the method for manufacturing the nonvolatile semiconductor memory device according to the first embodiment of the present invention. In addition, each cross-sectional position of these figures corresponds to the position along each of the II-II, III-III, and IV-IV line | wire of FIG.

23A to 23C are schematic cross-sectional views showing a seventeenth step of the method for manufacturing a nonvolatile semiconductor memory device according to the first embodiment of the present invention. In addition, each cross-sectional position of these figures corresponds to the position along each of the II-II, III-III, and IV-IV line | wire of FIG.

24 is a schematic plan view showing a planar layout in a memory cell array of a nonvolatile semiconductor memory device in a comparative example.

25 to 28 are schematic cross-sectional views taken along line XXV-XXV, XXVI-XXVI, XX'-XX ', and XX'-XX' of FIG. 24, respectively.

29 and 30 are schematic plan views and schematic cross-sectional views showing a first step of the method of manufacturing the nonvolatile semiconductor memory device of the comparative example. 30 corresponds to the line XXX-XXX in FIG.

31 is a schematic plan view showing a second step of the method for manufacturing the nonvolatile semiconductor memory device of the comparative example.

32A and 32B are schematic cross-sectional views showing a second step of the manufacturing method of the nonvolatile semiconductor memory device of the comparative example. 32 (a) and 32 (b) respectively correspond to the XIIA-XIIA lines and XIIB-XIIB lines in Fig. 31.

33A and 33B are schematic cross-sectional views schematically showing a third step of the manufacturing method of the nonvolatile semiconductor memory device of the comparative example. 33 (a) and 33 (b) correspond to the XIIA-XIIA lines and XIIB-XIIB lines in Fig. 31, respectively.

3A and 34B are schematic cross-sectional views schematically showing a fourth step of the manufacturing method of the nonvolatile semiconductor memory device of the comparative example. 34 (a) and 34 (b) respectively correspond to the XIIA-XIIA lines and XIIB-XIIB lines in Fig. 31.

35A and 35B are schematic cross-sectional views schematically showing a fifth step of the manufacturing method of the nonvolatile semiconductor memory device of the comparative example. 35 (a) and 35 (b) respectively correspond to the XIIA-XIIA lines and XIIB-XIIB lines in Fig. 31.

36A and 36B are schematic cross-sectional views schematically showing a sixth step of the method of manufacturing the nonvolatile semiconductor memory device of the comparative example. 36 (a) and 36 (b) respectively correspond to the VIIII-XIIA lines and XIIB-XIIB lines in Fig. 31.

37 is a schematic cross-sectional view schematically showing a sixth step of the method of manufacturing the nonvolatile semiconductor memory device of the comparative example. In addition, the cross-sectional position of this figure corresponds to the XXX'-XXX 'line | wire of FIG.

It is a schematic sectional perspective view of the area | region enclosed by the broken line A of FIG.

FIG. 39 is a schematic cross-sectional view showing the structure of the nonvolatile semiconductor memory device according to the second embodiment of the present invention, and the cross-sectional position corresponds to the cross-sectional position of FIG. 4 in the first embodiment.

Claims (8)

A semiconductor substrate SB having a major surface, A plurality of memory transistors MT each having a floating gate FG and a control gate CG formed by stacking each other on the main surface; Each of which has a lower gate layer G2 and an upper gate layer G1 formed by stacking each other on the main surface, and each of which is included in the memory cell MC together with one of the plurality of memory transistors MT. Select transistor (ST), The lower gate layer G2 is separated for each of the plurality of selection transistors ST, The upper gate layer G1 is shared by the plurality of select transistors ST and is electrically connected to the lower gate layer G2 of each of the plurality of select transistors ST. Nonvolatile Semiconductor Memory. The method of claim 1, And the lower gate layer (G2) and the upper gate layer (G1) are in direct contact with each other. The method of claim 1, And the lower gate layer (G2) and the floating gate have the same length along the extending direction of the upper gate layer (G1). The method of claim 1, And a length of the floating gate is shorter than a length of the lower gate layer (G2) along a direction crossing the extending direction of the upper gate layer (G1). The method of claim 1, And a device-to-element isolation layer (LCS) formed on the semiconductor substrate (SB) in a straight line along a direction intersecting with an extension direction of the upper gate layer (Gl). A manufacturing method of a nonvolatile semiconductor memory device having a plurality of memory cells MC, Forming a first insulating layer IS on the semiconductor substrate SB, Forming a first conductive layer AS on the first insulating layer IS; Patterning the first conductive layer AS such that each of the plurality of band shapes extends over a region where the plurality of memory cells MC are formed; Forming a second insulating layer (IO) on the first conductive layer (AS), Exposing a surface of the first conductive layer AS to the second insulating layer IO, and forming a plurality of openings OP each of which crosses the plurality of band shapes; Forming a second conductive layer PS so as to be electrically connected to the first conductive layer AS via the opening OP and to cover the second insulating layer IO; A lamination pattern including a part of the first conductive layer AS and a part of the second conductive layer PS electrically insulated from each other by the second insulating layer IO, and the opening OP And forming a stacked pattern including a portion of the first conductive layer AS and a portion of the second conductive layer PS that are formed and electrically connected to each other at a portion of the opening OP. Patterning the conductive layer PS and the first conductive layer AS A method of manufacturing a nonvolatile semiconductor memory device having a. The method of claim 6, The process of patterning the said 1st conductive layer (AS) has the process of forming the mask (P1R) which has a linear opening part, The manufacturing method of the nonvolatile semiconductor device characterized by the above-mentioned. The method of claim 6, The process of patterning the first conductive layer AS, Forming process of resist pattern P1, Applying a liquid material (OS) to fill the opening of the resist pattern (P1), After hardening a part of said liquid material OS in the boundary part with the said resist pattern P1, the process of removing the unhardened part of the said liquid material OS A method of manufacturing a nonvolatile semiconductor memory device, comprising:

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