JP2003289114A - Semiconductor storage device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of improving the coupling ratio of a memory cell. <P>SOLUTION: This semiconductor device is provided with a plurality of gate- insulating films 2 formed on a semiconductor substrate 1, a plurality of floating gate electrodes 4 formed on the gate-insulating film configuring a memory cell array 3, a plurality of element isolation regions 6 formed between the floating gate electrodes and at a memory cell array edge part 5, so that the difference of height of the upper face in the memory cell array and the upper face of the floating gate electrode, can be made larger than the difference of the height of the upper face in the memory cell array edge and the upper face of the floating gate electrode, an inter-gate insulating film 8 formed on the floating gate electrode surface, a control gate electrode 11 formed on the inter-gate insulating film, and a source/drain diffusion layer formed under the side face of the edge part of the floating gate electrode in the semiconductor substrate. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a floating gate as a charge storage layer, and more particularly to a semiconductor memory device having a floating gate separated by an element isolation region provided in a memory cell array and at an end of the memory cell array. The present invention relates to a device and a manufacturing method thereof.

[0002]

2. Description of the Related Art Conventionally, as a semiconductor memory device, for example, an EEPROM for electrically writing / erasing data
(Electrically Erasable Programmable Read-Only Mem
ory) is known. In this EEPROM, memory cells are arranged at intersections of row lines and column lines which intersect each other to form a memory cell array. A MOS transistor having a stacked gate structure in which a floating gate and a control gate are stacked is usually used for the memory cell. Among EEPROMs, a NAND type EEPROM is known as a method suitable for a large capacity memory.

The structure of such a memory cell will be described with reference to FIG. This memory cell has a self-aligned ST in which a floating gate electrode and a device region are formed in a self-aligned manner.
It has an I (Shallow Trench Isolation) structure. That is, the element region 102 defined by the element isolation region 101 is provided in the semiconductor substrate 100. A floating gate electrode 104 is formed on the element region 102 with a gate insulating film 103 interposed therebetween. An inter-gate insulating film 105 is provided on the surface of the floating gate electrode 104 and the element isolation region 101. This gate insulating film 10
On top of this, a polycrystalline silicon layer 106 and a silicide layer 10 are formed.
A control gate electrode 108 is formed by stacking the control gate electrodes 7 and 7.

Here, the floating gate electrode 104 is in an electrically floating state, and by applying a voltage between the control gate electrode 108 and the element region 102, charges are taken in and out of the floating gate electrode 104, and a MOS transistor is formed. It operates as a storage device by changing the threshold voltage of. Charge is taken in and out of the floating gate electrode 104 by flowing in the gate insulating film 103 or the inter-gate insulating film 105.
It is performed by N tunnel current or hot carrier injection.

FIG. 35 shows an equivalent circuit of this memory cell. The capacitance of the gate insulating film is represented by Cox, and the capacitance of the inter-gate insulating film is represented by Cono. The potential Vfg of the floating gate electrode when the potential of the element region is 0 and the potential Vcg is applied to the control gate can be expressed as follows. That is, Vfg is the product of Cr and Vcg, where Cr is the coupling ratio and this Cr is C
It is a value obtained by dividing ono by the sum of Cox and Cono. In order to charge the floating gate, it is necessary to apply a large electric field to the gate insulating film. For that purpose, it is effective to increase Cono and increase the coupling ratio. In the memory cell having the structure shown in FIG. 34, the area of the inter-gate insulating film 105 is increased by providing the inter-gate insulating film 105 also on the sidewall portion of the floating gate electrode 104,
I try to make Cono bigger.

FIG. 36 shows the structure of another memory cell. This memory cell has a self-aligned STI structure in which the floating gate electrode and the element region are formed in a self-aligned manner. That is, the element region 102 defined by the element isolation region 101 is provided in the semiconductor substrate 100. The gate insulating film 1 is formed on the element region 102.
The floating gate electrode 109 provided with a wing portion is formed via 03. An inter-gate insulating film 110 is provided on the surface of the floating gate electrode 109 and the element isolation region 101. A control gate electrode 113 in which a polycrystalline silicon layer 110 and a silicide layer 112 are stacked is formed on the inter-gate insulating film 110. In the memory cell thus formed, the wing portion of the floating gate occupies the area of the inter-gate insulating film. But,
In this structure, it is necessary to form a large element isolation region in order to provide a region for isolating the floating gate on the element isolation region, which hinders reduction of the area of the memory cell array region.

Next, the structure near the end of the memory cell array in the conventional semiconductor memory device using the memory cell structure shown in FIG. 34 will be described with reference to FIGS. 37 and 38. Here, FIG. 37 is a top view of FIG.
A cross section along line P "is shown. Each memory cell is isolated by an element isolation region 101, and control gate electrodes 108 of each memory cell are connected to each other to form a memory cell array. A large number of integrated semiconductor memory devices generally include a memory cell array section and a peripheral circuit area for driving the memory cell array section, where the memory cell array continues to the right of FIGS. It is assumed that the peripheral circuit region is formed on the left side, and the control gate electrode extends outside the memory cell array on the left side and is connected to the drive circuit.

A structure near the end of the memory cell array in a conventional semiconductor memory device using the memory cell structure shown in FIG. 36 corresponding to another conventional example will be described with reference to FIGS. 39 and 40. Here, FIG. 39 shows a cross section taken along the line “Q-R” in FIG. 40 showing the upper surface. 37 and 38 is different from the conventional technique except that a wing portion is provided on the floating gate electrode to increase the area of the inter-gate insulating film on the surface of the floating gate to increase the Cono of the capacitor. It is common.

[0009]

The conventional semiconductor memory device as described above has the following problems. FIG. 41 shows FIG.
9 is an example of a problem in the semiconductor memory device shown in FIG.
The upper surface of the element isolation region 101 is located below the upper surface of the floating gate electrode 104, and a step is formed there. The step of the element isolation region 101 between the memory cells in the memory cell region 109 is filled with the polycrystalline silicon layer 106.
The step 10 remains as a step even after the polycrystalline silicon layer 106 is formed. Here, the polycrystalline silicon layer has a high degree of conformity with the base, and the step of the base is reproduced as it is on the top surface shape of the polycrystalline silicon layer. When a silicide layer is formed on such a step, a coverage defect 111 of the silicide layer as shown in FIG. 41 is likely to occur. That is, when the thickness of the silicide layer 107 is smaller than the step P, poor coverage occurs. Here, the silicide layer 10
When the layer thickness of 7 is large, etching becomes difficult in the step of forming the opening when the contact is provided between the gate electrodes. In addition, when the conductive layer is buried in the openings after the openings are provided between the gate electrodes, it is difficult to fill the deeper depths below the conductive layer. Therefore, it is desirable to make the depth of the openings shallow. preferable. Thus, it is difficult to increase the thickness of the silicide layer in order to prevent poor coverage.

Such poor coverage not only causes an increase in electrical resistance of wiring, but also causes RIE (Reacti).
ve Ion Etching), which causes over-etching and under-etching at the time of etching the gate for patterning the control gate, and causes disconnection or short circuit of the wiring. That is, since the thickness of the silicide layer is formed to be much thicker than the other portion on the step, if the thick silicide layer and the silicide layer in the other thin portion are simultaneously etched under the condition of etching the thin film thickness portion, the thick portion Under etching occurs due to etching residue. Conversely, if the thick silicide layer and the silicide layer in the other thin portion are simultaneously etched under the condition that the thick portion is completely etched,
Over-etching occurs in which the lower polycrystalline silicon layer is excessively etched in the thin portion. As described above, the partial difference in the film thickness of the silicide layer causes a defect when the silicide layer is etched.

Even if no coverage failure occurs, the step difference of the gate electrode reduces the process margin of lithography for patterning when processing the gate electrode as a word line, resulting in a reduction in yield of the semiconductor memory device. Could lead to. That is, when the focus of the exposure apparatus for forming the resist pattern is set, if the focus is fixed to the silicide layer whose upper surface outside the memory cell array is in the low position, the focus is fixed in the silicide layer whose upper surface in the memory cell array is in the high position. Therefore, the resist is not formed at the desired position. In such a case, in the silicide layer in which the upper surface in the memory cell array is located at a high position, there is a defect that the shape of the silicide layer after patterning using a resist is displaced from a desired position. On the contrary, when the focus of the exposure apparatus for forming the resist pattern is focused, if the focus is fixed in accordance with the silicide layer whose upper surface in the memory cell array is at a high position, the upper surface outside the memory cell array is focused at the lower silicide layer. Therefore, the resist is not formed at the desired position. In such a case, in the silicide layer where the upper surface outside the memory cell array is located at a low position, there is a defect that the shape of the silicide layer after patterning using a resist is displaced from a desired position.

Further, in order to reduce the operating voltage, it is necessary to increase the above-mentioned coupling ratio. Therefore, in order to increase the area of the floating gate electrode side wall, the element isolation region and the floating gate electrode are There was a problem that the steps above became even larger and the above problems became more apparent. That is, the voltage Vfg applied to the floating gate
If the voltage Vcg applied to the control gate, which is the operating voltage, is to be lowered while keeping the constant value and maintaining the memory characteristic, it is necessary to increase the coupling ratio Cr.

An object of the present invention is to solve the above problems of the prior art. In particular, an object of the present invention is to provide a semiconductor memory device having an improved coupling ratio in memory cells. Still another object of the present invention is to provide a method of manufacturing a semiconductor memory device, which prevents defects during processing due to defective coverage of control gate electrodes. Still another object of the present invention is to provide a method for manufacturing a semiconductor memory device with improved margin in lithography for gate processing.

[0014]

To achieve the above object, the present invention is characterized by a semiconductor substrate, a plurality of gate insulating films formed on the semiconductor substrate, and a plurality of gate insulating films on the gate insulating film. A plurality of floating gate electrodes that are formed to form the memory cell array and a plurality of floating gate electrodes are provided between the floating gate electrodes and at an end of the memory cell array, and a difference in height between the upper surface of the memory cell array and the upper surface of the floating gate electrode is a memory cell array. An element isolation region that is larger than the height difference between the upper surface of the floating gate electrode and the upper surface of the floating gate electrode, an intergate insulating film formed on the surface of the floating gate electrode, and an intergate insulating film formed on the intergate insulating film. And a source / drain diffusion layer formed below a side surface of an end portion of the floating gate electrode in the semiconductor substrate.

Another feature of the present invention is that a semiconductor substrate, a plurality of gate insulating films formed on the semiconductor substrate, and a plurality of floating gates formed on the gate insulating film to form a memory cell array. A plurality of electrodes are provided between the floating gate electrodes and at the end of the memory cell array, and the height of the upper surface in the memory cell array is lower than the height of the upper surface of the floating gate electrode. An element isolation region in which the upper surfaces of the floating gate electrodes have the same height, an inter-gate insulating film formed on the surface of the floating gate electrode, a control gate electrode formed on the inter-gate insulating film, and the semiconductor substrate. A semiconductor memory device having a source / drain diffusion layer formed below a side surface of an end portion of the floating gate therein.

Another feature of the present invention is that a semiconductor substrate, a plurality of gate insulating films formed on the semiconductor substrate, a plurality of gate insulating films formed on the gate insulating film, a first-layer floating gate electrode, and A floating gate electrode having a second layer floating gate electrode and forming a memory cell array, and a plurality of floating gate electrodes provided between the first layer floating gate electrodes and at an end of the memory cell array, and the upper surface in the memory cell array and the first layer. An element isolation region in which the height difference from the upper surface of the floating gate electrode is larger than the height difference between the upper surface at the end of the memory cell array and the upper surface of the first layer floating gate electrode, and the surface of the second layer floating gate electrode. An inter-gate insulating film formed on the above,
A control gate electrode formed on the inter-gate insulating film,
A source / drain diffusion layer formed below a side surface of an end portion of the first layer floating gate electrode in the semiconductor substrate, and the element isolation region formed at an end of the memory cell array is below the second floating gate electrode. Is a semiconductor memory device formed in.

Further, a feature of the present invention is that a semiconductor substrate and
A plurality of gate insulating films formed on this semiconductor substrate,
A plurality of floating gate electrodes formed on the gate insulating film and having a first-layer floating gate electrode and a second-layer floating gate electrode to form a memory cell array, and between the first-layer floating gate electrodes and the memory cell array. There are multiple at the end,
The height of the upper surface of the memory cell array is lower than the height of the upper surface of the first-layer floating gate electrode,
The height of the upper surface at the end of the memory cell array is equal to the height of the upper surface of the first layer floating gate electrode, and the end portion of the element isolation region is formed under the second layer floating gate electrode, and the second An inter-gate insulating film formed on the surface of the floating gate electrode, a control gate electrode formed on the inter-gate insulating film, and a side surface of an end portion of the first layer floating gate electrode in the semiconductor substrate A semiconductor memory device having a source / drain diffusion layer.

Another feature of the present invention is the step of forming a gate insulating film and a floating gate electrode layer on a semiconductor substrate, and partially removing the semiconductor substrate, the gate insulating film and the floating gate electrode layer. Then, a step of depositing an element isolation insulating film to define a memory cell array region, and stacking a floating gate electrode material on the floating gate electrode layer,
Forming the device isolation insulating film and the upper surface of the floating gate electrode layer at the same height; and removing the device isolation region at the end of the memory cell array region, and separating the device in the memory cell array region. A method of manufacturing a semiconductor memory device, comprising: a step of partially removing a surface on a region to make it lower than an upper surface of the floating gate electrode layer; and a step of forming a control gate electrode layer on the floating gate electrode layer. .

Another feature of the present invention is the step of forming a gate insulating film and a floating gate electrode layer on a semiconductor substrate, and partially removing the semiconductor substrate, the gate insulating film and the floating gate electrode layer. A step of depositing an element isolation insulating film to define a memory cell array region, and removing the element isolation region at the end of the memory cell array region,
And a step of partially removing a surface on the device isolation region in the memory cell array region to lower the surface than the upper surface of the floating gate electrode layer, and the device isolation region and the memory cell array region at the end of the memory cell array region. A surface of the element isolation region in the memory cell array region is partially removed so that the upper surface of the element isolation region at the end of the memory cell array region is higher than the upper surface of the floating gate electrode and higher than the upper surface of the element isolation region in the memory cell array region. A method of manufacturing a semiconductor memory device, comprising: a step of increasing the height; a step of forming an intergate insulating film on the exposed surface of the floating gate electrode layer; and a step of forming a control gate electrode layer on the intergate insulating film. is there.

Further, another feature of the present invention is the step of forming a gate insulating film and a floating gate electrode layer on a semiconductor substrate, and the semiconductor substrate, the gate insulating film and the floating gate electrode layer are partially removed. A step of depositing an element isolation insulating film to define a memory cell array region, and removing the element isolation region at the end of the memory cell array region,
And a step of partially removing a surface on the element isolation region in the memory cell region to lower the surface than the upper surface of the floating gate electrode layer, and the element isolation region and the memory cell array region at the end of the memory cell array region. A surface of the element isolation region in the memory cell array region is partially removed so that the upper surface of the element isolation region at the end of the memory cell array region is lower than the upper surface of the floating gate electrode and higher than the upper surface of the element isolation region in the memory cell array region. A method of manufacturing a semiconductor memory device, comprising: a step of increasing the height; a step of forming an inter-gate insulating film on the exposed surface of the floating gate electrode layer; and a step of forming a control gate electrode layer on the inter-gate insulating film. is there.

Further, another feature of the present invention is that a step of forming a gate insulating film and a first floating gate electrode layer on a semiconductor substrate, and a step of forming the semiconductor substrate, the gate insulating film and the first floating gate electrode layer. Partially removing and depositing an element isolation insulating film to define a memory cell array region, and removing the element isolation region at the end of the memory cell array region, and the device in the memory cell array region Removing a part of the surface on the isolation region to make it lower than the upper surface of the first floating gate electrode layer, and the device isolation region at the end of the memory cell array region and the device isolation region in the memory cell array region. Remove a part of the surface,
Making the upper surface of the element isolation region at the end of the memory cell array region higher than the upper surface of the element isolation region in the memory cell array region; and a second floating gate on the exposed surface of the element isolation region and the first floating gate electrode layer. Forming the electrode layer, and removing the second floating gate electrode layer on the device isolation region in the memory cell array to form a plurality of second floating gate electrode layers.
The method includes separating into floating gate electrodes, forming an inter-gate insulating film on the exposed surfaces of the plurality of second floating gate electrodes, and forming a control gate electrode layer on the inter-gate insulating films. A method of manufacturing a semiconductor memory device.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) The structure of a semiconductor memory device according to the present embodiment will be described with reference to FIGS. Here, FIG. 2 shows an upper surface in the vicinity of the boundary of the memory cell array of the NAND flash memory according to the present embodiment, and FIG. 1 shows a cross section taken along the line “AB” in FIG. A cross section taken along line D "is shown in FIG. For example, a plurality of gate insulating films 2 made of a silicon oxide film are formed on a semiconductor substrate 1 made of silicon. A plurality of floating gate electrodes 4 made of a polycrystalline silicon layer forming the memory cell array 3 are formed on the gate insulating film 2. On the left side of FIG. 2, which is the outermost side of the memory cell array 3, is a region of the memory cell array end portion 5.

A plurality of element isolation regions 6 in the memory cell array are provided between the floating gate electrodes 4. The height of the upper surface of the element isolation region 6 in the memory cell array is lower than the height of the upper surface of the floating gate electrode 4, and is higher than the gate insulating film 2. Further, the memory cell array end portion 5 is provided with a memory cell array end element isolation region 7 having an upper surface higher than the upper surface of the memory cell array element isolation region 6. The height of the upper surface of the memory cell array end element isolation region 7 is equal to the height of the upper surface of the floating gate electrode 4.

On the surface of each floating gate electrode 4, on the surface of the element isolation region 6 in the memory cell array and on the surface of the element isolation region 7 at the end of the memory cell array, there is an inter-gate insulation made of, for example, a laminated film of a silicon oxide film and a silicon nitride film. The film 8 is formed. A control gate electrode 11 is formed on the inter-gate insulating film 8 by the polycrystalline silicon layer 9 and the silicide layer 10 thereon. Then, the gate insulating film 2
A device region 12 is formed near the surface of the lower semiconductor substrate 1.

FIG. 3, which is a cross section taken along the line “C-D” in FIG. 2, shows a state in which the floating gate electrode 4 is formed on the semiconductor substrate 1 with the gate insulating film 2 interposed therebetween. Here, a source / drain diffusion layer 13 is formed in the element region 12 in the semiconductor substrate 1 between the floating gates 4.

As shown in FIG. 2, an element isolation region 6 in the memory cell array for isolating the element regions 12 from each other is formed in parallel with the element regions 12. A plurality of memory cell columns are sandwiched between the element isolation regions 6 in the memory cell array. In this memory cell column, the source / drain diffusion layers 13 at both ends below the adjacent floating gates 4 as shown in FIG. 3 are shared with each other, and a plurality of memory cell transistors are connected in series to form a memory cell column. ing. Here, since the step difference between the height of the upper surface of the element isolation region 6 in the memory cell array and the height of the upper surface of the floating gate electrode 4 defines the coupling ratio, the size of the step is adjusted so as to obtain the required coupling ratio. It is set. Here, the step is set so as to have the same value as the width of the floating gate electrode 4, for example. For example, the width of the floating gate electrode 4 is about 0.1 μm.
m, the step between the upper surface of the element isolation region 6 in the memory cell array and the upper surface of the floating gate electrode 4 can be formed to be about 0.1 μm. In this way, the inter-gate insulating film 8 can be formed around the floating gate electrode 4 so as to have an area approximately three times the width of the gate insulating film 2, and the coupling ratio can be increased.

Here, STI is used as a device isolation method. Here, in the memory cell array element isolation region 6 and the memory cell array end element isolation region 7, in order to have an element isolation function, the upper surface of the element isolation region is higher than the upper surface of the gate insulating film 2 below the floating gate electrode 4. It is set so that it is always located above, and is formed of, for example, a silicon oxide film. Further, the element isolation region 6 in the memory cell region
Although a plurality of are provided, all of them have the same width.

Further, the widths of a plurality of floating gate electrodes 4 provided in the memory cell array 3 and the widths of the floating gate electrodes 4 provided adjacent to the end portion 5 of the memory cell array are equal to each other.

In the cross section shown in FIG. 1, one control gate electrode 11 is provided in common in the memory cell array 3 to control each floating gate electrode 4. Although not shown, the exposed surface of each structure is covered with an interlayer insulating film made of BPSG (silicon oxide film containing boron) or the like.

As described above, the height of the upper surface of the element isolation region in the memory cell array region is made lower than that in the outside of the memory cell array to provide a fine semiconductor memory device having an improved coupling ratio in the memory cell. You can

Next, a method of manufacturing the semiconductor memory device of this embodiment will be described with reference to FIGS. 1 and 4 to 10. First, as shown in FIG. 4, the gate insulating film 2 is formed on the semiconductor substrate 1.
To form. Next, a first polycrystalline silicon film 20 which will be a part of the floating gate electrode 4 is formed on the gate insulating film 2.
Next, a mask material 21 is formed on the first polycrystalline silicon film 20.
To form. For the mask material 21, for example, a silicon nitride film is used.

Next, as shown in FIG. 5, the mask material 21
Is patterned, and the mask material 21 is etched. Further, the first polycrystalline silicon film 20 and the gate insulating film 2 are etched in a self-aligned manner with the mask material 21, the semiconductor substrate 1 is further etched, and in the memory cell array formation planned region 22, the memory cell array for the element isolation region is formed. A plurality of inner element isolation trenches 23 are formed so as to have equal widths. Further, in the memory cell array edge formation scheduled area 24 outside the memory cell array formation scheduled area, a memory cell array edge element isolation trench 25 having a width larger than that of the memory cell array element isolation trench 23 is formed. In the memory cell array formation-scheduled region 22, the vicinity of the upper surface of the semiconductor substrate 1 divided by the element isolation trenches 23 in the memory cell array is defined as the element region 12.

Next, as shown in FIG. 6, the element isolation trenches 23 in the memory cell array and the element isolation trenches 25 in the memory cell array end portion are filled with an insulating film, for example, a silicon oxide film 26, and then CMP (chemical mechanical polishing) is performed. The surface is flattened by a method or the like. Thus, each element isolation region is formed in a self-aligned manner with each adjacent floating gate electrode.

Next, as shown in FIG. 7, the mask material 2
Remove 1. When a silicon nitride film is used as the mask material 21, for example, hot phosphoric acid is used to remove the mask material 21. The step difference between the upper surface of the silicon oxide film 26 in the element isolation region and the upper surface of the first polycrystalline silicon layer 20, which is a part of the floating gate electrode, thus generated is due to the thickness of the mask material 21 at the time of deposition. The thickness is obtained by removing the damage amount on the mask material and the surface of the first polycrystalline silicon layer 20 when the element isolation groove is formed and the mask material is removed.

Next, as shown in FIG. 8, the mask material 2
The second polycrystalline silicon film 27 is embedded in the portion where 1 is removed. The second polycrystalline silicon film 27 is electrically connected to the first polycrystalline silicon film 20 already formed in the previous step to become the floating gate electrode 4 together. After the second polycrystalline silicon film 27 is buried, a flattening method such as a CMP method is used to remove the second polycrystalline silicon film 20 from the silicon oxide film 26 in the element isolation region by a damascene method.

Next, as shown in FIG. 9, a photoresist 28 is formed so as to open the inside of the memory cell array 3 by the photolithography method and cover the end portion 5 of the memory cell array.
To form. At this time, the boundary of the opening of the photoresist 28 is arranged so as to be located on the element region 12 of the end portion 5 of the memory cell array, that is, on the floating gate electrode 4 of the end portion 5 of the memory cell array. Here, in FIG. 9, the boundary of the opening of the photoresist 28 needs to be located in any part of the region X from the left end to the right end of the floating gate electrode 4 of the end portion 5 of the memory cell array. This is a later step,
This is to prevent the element isolation region from being removed outside the desired region. Next, the insulating film 26 embedded in the element isolation region in the memory cell array 3 which is not covered with the photoresist 28 is etched back to form the element isolation region 6 in the memory cell array. Here, the etching amount is adjusted so that the upper surface height of the element isolation region in the memory cell array 3 is obtained so as to obtain a required coupling ratio. This etching is performed using one or both of RIE and a dilute hydrofluoric acid chemical solution.

Thus, the height of the upper surface of the element isolation region 6 in the memory cell array is made lower than the height of the upper surface of the floating gate electrode 4. On the other hand, in the memory cell array end portion 5, the upper surface of the element isolation region is kept at the same height as the floating gate electrode 4,
It becomes the memory cell array end element isolation region 7. The height of the upper surface of the element isolation region 6 in the memory cell array is formed to be higher than the height of the gate insulating film 2.

Next, as shown in FIG. 10, after removing the photoresist 28, an inter-gate insulating film 8 is formed on the exposed surface.

Next, as shown in FIG. 1, a polycrystalline silicon layer 9 to be a control gate electrode is deposited on the intergate insulating film 8. By setting the polycrystalline silicon layer 9 to have a sufficient thickness, the step between the element isolation region 6 in the memory cell array and the floating gate electrode 4 is filled. That is, by depositing the polycrystalline silicon layer 9 having a thickness that is at least half the width of the element isolation region 6 in the memory cell array, the step between the element isolation region 6 in the memory cell array and the floating gate 4 is filled. Further, since there is no step between the memory cell array end element isolation region 7 and the floating gate electrode 4, the step does not exist in that portion of the polycrystalline silicon layer 9 deposited thereon.

Next, the silicide layer 10 is formed on the polycrystalline silicon layer 9. For the silicide layer, for example, tungsten silicide is used. Further, a depression 29 is formed on the upper surface of the polycrystalline silicon layer 9 buried in the element isolation region 6 in the memory cell array, but since the step is extremely small, the depression 29 is formed when the silicide layer is formed. Embedded by. Subsequently, the control gate electrode 11 and the floating gate electrode 4 are patterned and processed so as to become a gate electrode and a word line of a transistor, and impurities for forming the source / drain diffusion layer 13 are ion-implanted. The semiconductor memory device as shown in FIG. 1 is completed.

As described above, according to the method of manufacturing the semiconductor memory device of the present embodiment, the step between the element isolation region 6 in the memory cell array and the floating gate electrode 4 becomes the control gate electrode 11 in the memory cell array 3 region. Crystalline silicon layer 9
The step is almost eliminated when the silicide layer 10 is formed. Further, in the memory cell array end portion 5, since the upper surface of the memory cell array end element isolation region 7 and the upper surface of the floating gate electrode 4 are at the same height, no step can be formed in the silicide layer 10. Therefore, it is possible to prevent poor coverage of the silicide layer at the end portion of the memory cell array, and a reduction in margin due to a change in the height of the gate inside and outside the array in a lithography process for processing the gate. That is, it is possible to prevent the disconnection of the control gate electrode on the element isolation region at the end of the memory cell array, which has occurred in the conventional technique. Moreover, over-etching and under-etching at the time of patterning the silicide layer can be prevented.

Regarding the memory cell at the end 5 of the memory cell array, the inter-gate insulating film 8 is not formed on one side wall of the floating gate 4 and the element isolation region 7 at the end of the memory cell array is in contact with the memory cell. Although the coupling ratio is different from that of the other floating gates 4, the memory cells at the end of the memory cell array are generally used as dummy cells that do not function as elements because the processing accuracy varies. There is no loss. That is, in the memory cell array, 100
Since a memory cell row is provided in units of several thousand from a book,
Even if one row of dummy cells is provided at the end portion, the area increase is slight. Further, the dummy cells are not limited to one column at the end of the memory cell array, but may be provided for two columns or more.

(Second Embodiment) As shown in FIG. 11, in the semiconductor memory device of the present embodiment, the width L1 of the element region 30 of the memory cell in the end portion 5 of the memory cell array is set to that of the other memory cell array 3. The width is larger than the width L2 of the element region 12, and the other structure is the same as the structure of the semiconductor memory device of the first embodiment. Here, L1 can be set to be several times as large as L2. Here, FIG. 11 is a cross-sectional view taken along the line “EF” of FIG. 12, which is a top view of the semiconductor memory device. Further, the gate insulating film 31 and the floating gate electrode 32 on the element region 12 in the end portion 5 of the memory cell array are the same as the gate insulating film 2 in the memory cell array 3.
The width of the floating gate electrode 4 is larger than that of the floating gate electrode 4. Here, each component width refers to the distance in the longitudinal direction of the control gate electrode 11 as shown in the left-right direction in the top view of FIG. The other structure is the same as the structure of the semiconductor memory device of the first embodiment, and the description thereof is omitted. Also in the semiconductor memory device of the present embodiment, the same effect as that of the semiconductor memory device of the first embodiment can be obtained.

The manufacturing method of the present embodiment is the same as the manufacturing method of the semiconductor memory device of the first embodiment, in the step of defining the memory cell array region shown in FIG. Instead of the step of forming the width of the first polycrystalline silicon layer 20 to be larger than the width of the first polycrystalline silicon layer 20 in the memory cell array formation scheduled region 22, other manufacturing steps are the same as those of the first embodiment. The same steps as the method can be applied.

In the method of manufacturing the semiconductor memory device of this embodiment, the same effect as that of the method of manufacturing the semiconductor memory device of the first embodiment can be obtained. Further, it is possible to increase the margin of misalignment and misalignment when forming the pattern of the photoresist 28 in the step shown in FIG. 9 shown in the manufacturing method of the first embodiment.

(Third Embodiment) As shown in FIG. 13, the semiconductor memory device of this embodiment has a memory cell array end element isolation region 3 in a memory cell array end portion 5.
5, the height of the upper surface of the floating gate electrode 4 is higher than that of the floating gate electrode 4, and the other structures are the same as those of the semiconductor memory device of the first embodiment. Thus, the height of the step between the element isolation region and the floating gate electrode is
It is smaller at the end of the memory cell array than in the memory cell array region. Here, FIG. 13 is a cross-sectional view taken along the line "GH" of FIG. 14, which is a top view of the semiconductor memory device. Here, the step between the upper surface of the memory cell array end element isolation region 35 and the upper surface of the floating gate electrode 4 is
It is formed to be smaller than the step between the upper surface of the element isolation region 6 in the memory cell array and the upper surface of the floating gate electrode 4, so that the control gate electrode is not defective due to the step as in the prior art. The other structure is the same as the structure of the semiconductor memory device of the first embodiment, and the description thereof is omitted. Also in the semiconductor memory device of the present embodiment, the same effect as that of the semiconductor memory device of the first embodiment can be obtained.

The manufacturing method according to this embodiment will be described with reference to FIGS. 4, 5, 13, and 15 to 18. First, in the step shown in FIG. 4, the gate insulating film 2, the first polycrystalline silicon film 20 serving as the floating gate electrode 4, and the mask material 21 are formed on the semiconductor substrate 1. Here, the first polycrystalline silicon film 20 is formed so as to have a finally required film thickness, and the thickness thereof is made larger than that of the first polycrystalline silicon film 20 of the first embodiment. ing.

Next, as shown in FIG. 5, the mask material 2
1 is patterned, and the mask material 21 is etched.
Furthermore, the floating gate electrode 4 is self-aligned with the mask material 21,
The gate insulating film 2 is etched and the semiconductor substrate 1 is further etched to form trenches 23 and 25 for element isolation regions.

Next, as shown in FIG. 15, the element isolation trenches 23 and 25 are filled with an insulating film such as a silicon oxide film 26, and then planarized by a CMP method or the like.

Next, as shown in FIG. 16, the mask material 2
After removing 1, the photoresist 36 is formed by photolithography so as to open the cell array region and cover the region other than the array. At this time, the boundary of the opening of the photoresist 36 is located on the element region 12 of the end portion 5 of the memory cell array. Then, the silicon oxide film 26 embedded in the element isolation groove exposed in the opening of the photoresist 36 is etched back. In this way, the height of the upper surface of the silicon oxide film 26 in the isolation trench of the memory cell array region 3 is made lower than the height of the upper surface of the floating gate electrode 4. On the other hand, in the end portion 5 of the memory cell array, the upper surface of the silicon oxide film 26 in the isolation trench is the floating gate electrode 4
Is higher than the upper surface of.

Next, as shown in FIG. 17, after removing the photoresist 36, the silicon oxide film 26 in the element isolation trench is further etched back. As a result, the silicon oxide film in the memory cell array 3 is further lowered, and the element isolation region 6 in the memory cell array is formed. Even in regions other than the memory cell array 3, the silicon oxide film in the element isolation trench becomes low, the step between the upper surface of the element isolation trench and the floating gate electrode 4 becomes small, and the memory cell array end element isolation region 3 is formed.
5 is formed. Here, etchback is performed using either or both of RIE and a chemical solution of dilute hydrofluoric acid. Here, the height difference between the upper surface of the memory cell array end element isolation region 35 and the upper surface of the floating gate electrode 4 is the height difference between the upper surface of the in-memory cell array element isolation region 6 and the upper surface of the floating gate electrode 4. Is always smaller than.
The upper surface of the memory cell array end element isolation region 35 is formed higher than the upper surface of the floating gate electrode 4 and higher than the upper surface of the in-memory cell array element isolation region 6. The height of the upper surface of the floating gate electrode 4 is formed to be equal both in the memory cell array end portion 5 and in the memory cell array 3.

Next, as shown in FIG. 18, an inter-gate insulating film 8 is formed on the exposed surface. Further, the semiconductor memory device as shown in FIG. 13 is completed through the steps of forming the polycrystalline silicon layer 9 and the silicide layer 10 which will be the control gate electrodes 11.

The method of manufacturing the semiconductor memory device of this embodiment can obtain the same effects as those of the method of manufacturing the semiconductor memory device of the first embodiment. Further, according to the method of manufacturing the semiconductor memory device of the present embodiment, the number of CMP steps is reduced, and there is no step of depositing the floating gate electrode in two steps. Therefore, the method of manufacturing the semiconductor memory device of the first embodiment. The number of manufacturing steps can be reduced compared to.

As in the second embodiment, the element region width L1 of the memory cell at the end of the memory cell array can be made larger than the element region width L2 of another memory cell. In this case, the same effect as that of the second embodiment can be obtained.

(Fourth Embodiment) As shown in FIG. 19, the semiconductor memory device of the present embodiment has a memory cell array end element isolation region 4 in a memory cell array end portion 5.
The height of the upper surface of 0 is formed lower than the height of the upper surface of the floating gate electrode 4, and the other structures are the same as the structure of the semiconductor memory device of the first embodiment. Thus, the height of the step between the element isolation region and the floating gate electrode is
It is smaller at the end of the memory cell array than in the memory cell array region. Here, FIG. 19 is a cross-sectional view taken along the line "I-J" of FIG. 20, which is a top view of the semiconductor memory device. Here, the height of the upper surface of the element isolation region 40 at the memory cell array end portion 5 outside the memory cell array is equal to the height of the element isolation region 6 in the memory cell array 3 region.
It is always higher than the height of the upper surface of the. Here, the step between the upper surface of the memory cell array end element isolation region 40 and the upper surface of the floating gate electrode 4 is smaller than the step between the upper surface of the memory cell array element isolation region 6 and the upper surface of the floating gate electrode 4. The small size prevents the control gate electrode from being defective due to the step difference as in the prior art. The other structure is the same as the structure of the semiconductor memory device of the first embodiment, and the description thereof is omitted. Also in the semiconductor memory device of the present embodiment, the same effect as that of the semiconductor memory device of the first embodiment can be obtained. In this way, the occurrence of disconnection defects due to the step of the control gate electrode at the end of the memory cell array is prevented. Further, it is preferable that the step difference between the upper surface of the element isolation region and the upper surface of the floating gate electrode outside the memory cell array is as small as possible in order to prevent disconnection defects of the control gate electrode. As described above, since the step at the end of the memory cell array is smaller than the step in the memory cell array, the same effect as that of the semiconductor memory device of the third embodiment can be obtained.

The manufacturing method according to this embodiment will be described with reference to FIGS. 4, 5, 13, 13, 15, 18, 19, and 22.
Will be explained. First, in the step shown in FIG. 4, the gate insulating film 2, the first polycrystalline silicon film 20 serving as the floating gate electrode 4, and the mask material 21 are formed on the semiconductor substrate 1. Here, the first polycrystalline silicon film 20 is formed so as to have a finally required film thickness, and the thickness thereof is made larger than that of the first polycrystalline silicon film 20 of the first embodiment. ing.

Next, as shown in FIG. 5, the mask material 2
1 is patterned, and the mask material 21 is etched.
Furthermore, the floating gate electrode 4 is self-aligned with the mask material 21,
The gate insulating film 2 is etched and the semiconductor substrate 1 is further etched to form trenches 23 and 25 for element isolation regions.

Next, as shown in FIG. 15, the element isolation trenches 23 and 25 are filled with an insulating film such as a silicon oxide film 26, and then planarized by a CMP method or the like.

Next, as shown in FIG. 21, the mask material 2
After removing 1, the photoresist 41 is formed by photolithography so as to open the cell array region and cover the region other than the array. At this time, the boundary of the opening of the photoresist 41 is positioned on the element region 12 of the end portion 5 of the memory cell array. Then, the silicon oxide film 26 embedded in the element isolation groove exposed in the opening of the photoresist 41 is etched back. In this way, the height of the upper surface of the silicon oxide film 26 in the isolation trench of the memory cell array region 3 is made lower than the height of the upper surface of the floating gate electrode 4. On the other hand, in the end portion 5 of the memory cell array, the upper surface of the silicon oxide film 26 in the isolation trench is the floating gate electrode 4
Is higher than the upper surface of.

Next, as shown in FIG. 22, after removing the photoresist 41, the silicon oxide film 26 in the element isolation trench is further etched back. As a result, the silicon oxide film in the memory cell array 3 is further lowered, and the element isolation region 6 in the memory cell array is formed. In regions other than the memory cell array 3 as well, the silicon oxide film in the device isolation trench becomes low, the step between the upper surface of the device and the floating gate electrode 4 becomes small, and the device isolation region 4 at the end of the memory cell array is isolated.
0 is formed. Here, etchback is performed using either or both of RIE and a chemical solution of dilute hydrofluoric acid. Here, the height difference between the upper surface of the memory cell array end element isolation region 40 and the upper surface of the floating gate electrode 4 is the height difference between the upper surface of the in-memory cell array element isolation region 6 and the upper surface of the floating gate electrode 4. Is always smaller than.
Further, the upper surface of the memory cell array end element isolation region 40 is formed lower than the upper surface of the floating gate electrode 4 and higher than the upper surface of the in-memory cell array element isolation region 6. The height of the upper surface of the floating gate electrode 4 is formed to be equal both in the memory cell array end portion 5 and in the memory cell array 3.

Next, the inter-gate insulating film 8 is formed on the exposed surface. Further, through a step of forming a polycrystalline silicon layer 9 to be the control gate electrode 11, a silicide layer 10 and the like, FIG.
The semiconductor memory device as shown in 9 is completed.

The method of manufacturing the semiconductor memory device of this embodiment can obtain the same effects as those of the method of manufacturing the semiconductor memory device of the first embodiment. Further, according to the method of manufacturing the semiconductor memory device of the present embodiment, the number of CMP steps is reduced, and there is no step of depositing the floating gate electrode in two steps. Therefore, the method of manufacturing the semiconductor memory device of the first embodiment. The number of manufacturing steps can be reduced compared to.

As in the second embodiment, the element region width L1 of the memory cell at the end of the memory cell array can be made larger than the element region width L2 of the other memory cell. In this case, the same effect as that of the second embodiment can be obtained.

(Fifth Embodiment) The structure of a semiconductor memory device according to the present embodiment will be described with reference to FIGS. Here, FIG. 24 shows an upper surface in the vicinity of the boundary of the memory cell array of the NAND flash memory according to the present embodiment, and FIG. 23 shows a cross section taken along the “KL” line in FIG. For example, a gate insulating film 51 made of a plurality of silicon oxide films is formed on a semiconductor substrate 50 made of silicon. On the gate insulating film 51, a plurality of floating gate electrodes 53 made of a polycrystalline silicon layer forming the memory cell array 52 are formed. Here, the floating gate electrode 53 is composed of a lower first floating gate electrode 54 and a second floating gate electrode 55 formed thereon.
It has a laminated structure with. On the left side of FIG. 23, which is the outermost side of the memory cell array 52, the memory cell array end portion 5 is provided.
There are 6 areas.

A plurality of element isolation regions 57 in the memory cell array are provided between the first floating gate electrodes 54. The height of the upper surface of the element isolation region 57 in the memory cell array is formed lower than the height of the upper surface of the first floating gate electrode 54, and is higher than the gate insulating film 51. Further, the memory cell array end portion 56 is provided with a memory cell array end element isolation region 58 having an upper surface higher than the upper surface of the memory cell array element isolation region 57. This memory cell array end element isolation region 5
The height of the upper surface of 8 is equal to the height of the upper surface of the first floating gate electrode 54.

In the memory cell array 52, the second floating gate electrode 55 on each first floating gate electrode 54 has the upper surfaces of the two element isolation regions 57 in the memory cell array which are in contact with the two side surfaces of the first floating gate electrode 54. Is formed over a part of.

Further, at the memory cell array end 56, the first
The second floating gate electrode 59 on the floating gate electrode 54 is the element isolation region 5 in the memory cell array on the memory cell array side.
7 is formed on a part thereof and is formed in a stripe shape on the memory cell array end element isolation region 58 on the memory cell array end portion 56 side.

On the surface of each second floating gate electrode 55 and the surface of the element isolation region 57 in the memory cell array, an inter-gate insulating film 60 made of, for example, a laminated film of a silicon oxide film and a silicon nitride film is formed. There is. A control gate electrode 63 is formed on the inter-gate insulating film 60 by the polycrystalline silicon layer 61 and the silicide layer 62 thereon. Then, an element region 64 is formed in the vicinity of the surface of the semiconductor substrate 1 below the gate insulating film 51. The control gate electrode 63 has a laminated structure of a polycrystalline silicon layer 61 and a silicide layer 62, and the inter-gate insulating film 60 and the polycrystal in the control gate electrode 63 are provided between the second floating gate electrodes 55 in the memory cell array 52. It is filled with a silicon layer 61.

The cross section on the element region orthogonal to the "KL" line in FIG. 24 has the same structure as that of FIG. 3 shown in the first embodiment.

As shown in FIG. 24, an element isolation region 57 in the memory cell array that isolates the element regions 64 from each other is formed parallel to the element regions 64. A plurality of memory cell columns are formed so as to be sandwiched by the element isolation regions 57 in the memory cell array. In this memory cell column, the source / drain diffusion layers 65 at both ends below the adjacent floating gates 53 are shared with each other, and a plurality of memory cell transistors are connected in series to form a memory cell column. Here, the height of the upper surface of the element isolation region 57 in the memory cell array and the second
The level difference with the height of the upper surface of the floating gate electrode 55 defines the coupling ratio, so the size of the level difference is set so as to obtain the required coupling ratio. Here, unlike the first to fourth embodiments, a wing portion composed of the second floating gate electrode 55 is provided in the floating gate electrode to increase the surface area of the floating gate electrode 53 and increase the coupling ratio. ing.

Here, STI is used as a device isolation method. Here, in the memory cell array element isolation region 57 and the memory cell array end element isolation region 58, the first floating gate electrode 54 is provided in order to have an element isolation function.
The upper surface of the element isolation region is set to always be located above the upper surface of the lower gate insulating film 51, and is formed of, for example, a silicon oxide film. Further, although a plurality of element isolation regions 57 in the memory cell region are provided, all of them have the same width.

Further, the widths of the plurality of first floating gate electrodes 54 provided in the memory cell array 52 and the widths of the first floating gate electrodes 54 provided adjacent to the end portion 56 of the memory cell array are equal to each other. There is.

In the cross section shown in FIG. 23, one control gate electrode 63 is provided in common in the memory cell array 52 to control each floating gate electrode 53. Although not shown, the exposed surface of each structure is covered with an interlayer insulating film made of BPSG or the like.

As described above, the height of the upper surface of the element isolation region in the memory cell array region is made lower than that in the outside of the memory cell array to provide a fine semiconductor memory device having an improved coupling ratio in the memory cell. You can

Here, the upper surface of the memory cell array end element isolation region 58 may be formed at a position higher than the upper surface of the first floating gate electrode 54. Further, the upper surface of the memory cell array end element isolation region 58 has the first floating gate electrode 54.
It may be formed at the same position as the upper surface of the. Further, the upper surface of the memory cell array end element isolation region 58 may be formed at a position lower than the upper surface of the first floating gate electrode 54 and higher than the upper surface of the in-memory cell array element isolation region 57.

The width of the first floating gate electrode 54 at the end 56 of the memory cell array may be equal to the width of the first floating gate electrode 54 in the memory cell array 52. Further, the width of the first floating gate electrode 54 at the memory cell array end 56 may be wider than the width of the first floating gate electrode 54 in the memory cell array 52.

The memory cell array end element isolation region 5
It is also possible to form an opening in the second floating gate 59 on the surface 8 and fill the inside with a polycrystalline silicon layer. in this case,
The size of the opening is the same as the size of the opening between the second floating gates 55 on the element isolation region 57 in the memory cell array 52.

In the semiconductor memory device thus formed, the height from the upper surface of the element isolation region to the upper surface of the floating gate electrode on the element isolation region in the memory cell array is increased as compared with the prior art to increase the coupling ratio. There is. According to the structure of the semiconductor memory device of the present embodiment, the area of the gate insulating film per memory cell can be made larger than before. That is, since the coupling ratio can be improved as compared with the related art, there are advantages such as reduction of the voltage required for writing.

Next, a method of manufacturing the semiconductor memory device of this embodiment will be described with reference to FIGS. 23 and 25 to 31.
First, as shown in FIG. 25, the gate insulating film 51 is formed on the semiconductor substrate 50. Next, the first on the gate insulating film 51
A first polycrystalline silicon film 70, which will be a part of the floating gate electrode 54, is formed. Next, the first polycrystalline silicon film 70
A mask material 71 is formed on top. As the mask material 71, for example, a silicon nitride film is used.

Next, the mask material 71 is patterned and the mask material 71 is etched. Further, the first polycrystalline silicon film 70 and the gate insulating film 5 are self-aligned with the mask material 71.
1 is further etched, and the semiconductor substrate 50 is further etched to form a plurality of device isolation trenches 73 in the memory cell array for the device isolation regions so as to have a uniform width in the memory cell array formation planned region 72. Further, in the memory cell array edge formation scheduled area 74 outside the memory cell array formation scheduled area, a memory cell array edge element isolation groove 75 having a width larger than that of the in-memory cell array element isolation groove 73 is formed. In the memory cell array formation-scheduled region 72, the vicinity of the upper surface of the semiconductor substrate 5 divided by the element isolation trenches 73 in the memory cell array is defined as an element region 64.

Then, as shown in FIG. 26, after the element isolation trenches 73 in the memory cell array and the element isolation trenches 75 at the end of the memory cell array are filled with an insulating film, for example, a silicon oxide film 76, the surface is subjected to CMP or the like. Flatten. Thus, each element isolation region is formed in a self-aligned manner with each adjacent floating gate electrode.

Next, the mask material 71 is removed. When a silicon nitride film is used as the mask material 71, for example, hot phosphoric acid is used to remove the mask material 71. The level difference between the upper surface of the silicon oxide film 76 in the element isolation region and the upper surface of the first polycrystalline silicon film 70, which is a part of the first floating gate electrode, is the thickness of the mask material 71 during deposition. Therefore, the thickness is obtained by removing the damage amount on the mask material and the surface of the first polycrystalline silicon film 70 at the time of forming the element isolation groove and removing the mask material.

Next, as shown in FIG. 27, a photoresist 77 is formed by photolithography to open the inside of the memory cell array 52 and cover the end portion 56 of the memory cell array. At this time, the boundary of the opening of the photoresist 77 is defined by the device region 6 of the end portion 56 of the memory cell array.
4 on the first floating gate electrode 54 of the end portion 56 of the memory cell array. Here, in FIG. 27, the boundary of the opening of the photoresist 77 needs to be located in any part of the region Y from the left end to the right end of the floating gate electrode 4 at the end 5 of the memory cell array. This is to prevent the element isolation region from being removed outside the desired region in a later step. Next, the memory cell array 52 not covered with the photoresist 77.
The insulating film 76 embedded in the element isolation region inside is etched back. This etching is performed using one or both of RIE and a dilute hydrofluoric acid chemical solution. Thus, the silicon oxide film 76 in the element isolation trench in the memory cell array region 52 is formed.
The height of the upper surface of the floating gate electrode 54 is lower than that of the floating gate electrode 54. On the other hand, in the memory cell array end portion 56, the upper surface of the silicon oxide film 76 in the element isolation trench is higher than the upper surface of the floating gate electrode 4. Here, a natural oxide film is formed on the exposed surface of the floating gate electrode.

Next, as shown in FIG. 28, after removing the photoresist 77, the silicon oxide film 76 in the element isolation trench is further etched back. As a result, the silicon oxide film in the memory cell array 52 is further lowered,
An element isolation region 57 in the memory cell array is formed. Even in a region other than the memory cell array 57, the silicon oxide film in the element isolation trench becomes low, and the step between the upper surface of the element isolation trench and the first floating gate electrode 54 is made small. Region 58 is formed. Here, etchback is performed using either or both of RIE and a chemical solution of dilute hydrofluoric acid. here,
The height difference between the upper surface of the memory cell array end element isolation region 58 and the upper surface of the first floating gate electrode 54 is equal to the height of the upper surface of the in-memory cell array element isolation region 57 and the upper surface of the first floating gate electrode 54. It is always smaller than the step. The upper surface of the memory cell array end element isolation region 56 is formed higher than the upper surface of the first floating gate electrode 54 and higher than the upper surface of the in-memory cell array element isolation region 57. The height of the upper surface of the first floating gate electrode 54 is formed to be the same both in the memory cell array end portion 56 and in the memory cell array 52.

Next, as shown in FIG. 29, a second polycrystalline silicon film 78 is deposited on the first floating gate electrode 54. This second polycrystalline silicon film 78 is connected to the first floating gate electrode 54 formed of the first polycrystalline silicon film 70 previously formed, and finally becomes the integrated floating gate electrode 53. The second floating gate electrode 55 may be formed on the natural oxide film formed on the surface of the first floating gate electrode 54 while the natural oxide film remains. This is because the natural oxide film is not a thick film that poses a problem in device operation.

Next, as shown in FIG. 30, the second polycrystalline silicon film 55 is patterned and divided on the element isolation region 57 in the memory cell array to form an opening 79. If the opening 79 between the floating gate electrodes 53 divided on the element isolation region 57 in the memory cell array has the minimum dimensional width that can be processed, the coupling ratio can be further increased. Thus, the floating gate electrode 53 having the wing portion is formed.

Next, as shown in FIG. 31, an inter-gate insulating film 60 is formed on the surface of the floating gate electrode 53 and on the opening 79 of the element isolation region 57 in the memory cell array. Further, a polycrystalline silicon layer 61 to be the control gate electrode 63,
A process such as formation of the silicide layer 62 is performed. By setting the polycrystalline silicon layer 61 to have a sufficient thickness, the element isolation region 57 in the memory cell array and the floating gate electrode 5 are formed.
The step with 3 is buried. That is, by depositing a polycrystalline silicon layer 61 having a thickness equal to or more than half the width of the opening between the floating gates 53 on the element isolation region in the memory cell array 57, the element isolation region 57 in the memory cell array and the floating gate 53 are formed. The step will be embedded. Further, since there is no step between the memory cell array end element isolation region 58 and the floating gate electrode 59, the polycrystalline silicon layer 61 deposited thereon has no step at that portion. For the silicide layer, for example, tungsten silicide is used.

Thus, the height of the upper surface of the element isolation region 57 in the memory cell array is made lower than the height of the upper surface of the floating gate electrode 53. On the other hand, in the memory cell array end portion 5, the floating gate electrode 59 is formed in a stripe shape in the same shape as the control gate electrode 63 on the upper surface of the element isolation region, so that the control gate electrode 63 has no step. The height of the upper surface of the element isolation region 57 in the memory cell array is determined by the gate insulating film 51.
It is formed so as to be located above the height of. Here, the etching amount is adjusted so that the height of the upper surface of the element isolation region 57 in the memory cell array is such that a required coupling ratio is obtained.

Further, the element isolation region 5 in the memory cell array
A depression 80 is formed on the upper surface of the polycrystalline silicon layer 61 buried on the surface 7. However, since the step is extremely small,
When forming the silicide layer, the recess 80 is filled with the silicide layer. Following this, the control gate electrode 63
The floating gate electrode 53 and the floating gate electrode 53 are patterned and processed so as to become the gate electrode and word line of the transistor, and impurities for forming the source / drain diffusion layer 65 are ion-implanted, and the semiconductor as shown in FIG. The storage device is completed.

Thus, the method of manufacturing the semiconductor memory device according to the present embodiment can prevent defects during processing due to defective coverage of the control gate electrode. Further, it is possible to provide a method for manufacturing a semiconductor memory device with an improved margin in lithography for gate processing.

As in the second embodiment, the element region width L1 of the memory cell at the cell array edge can be made larger than the element region width L2 of the other memory cell. In this case, the same effect as that of the second embodiment can be obtained.

(Sixth Embodiment) The structure of a semiconductor memory device according to the present embodiment will be described with reference to FIGS. 32 and 33. Here, FIG. 33 shows an upper surface in the vicinity of the boundary of the memory cell array of the NAND flash memory according to the present embodiment, and FIG. 32 shows a cross section taken along the line "MN" in FIG. For example, a gate insulating film 51 made of a plurality of silicon oxide films is formed on a semiconductor substrate 50 made of silicon. On the gate insulating film 51, a plurality of floating gate electrodes 90 made of a polycrystalline silicon layer forming the memory cell array 52 are formed. Here, the floating gate electrode 90 includes the lower first floating gate electrode 54 and the second floating gate electrode 91 formed thereon.
It has a laminated structure with. Here, the side wall of the second floating gate electrode is not vertical as in the fifth embodiment, but has a tapered shape. That is, the second floating gate electrode 91 has a trapezoidal shape in which the lower surface is wider than the upper surface.
On the left side of FIG. 32, which is the outermost side of the memory cell array 52, is a region of the memory cell array end portion 56.

A plurality of element isolation regions 57 in the memory cell array are provided between the first floating gate electrodes 54. The height of the upper surface of the element isolation region 57 in the memory cell array is formed lower than the height of the upper surface of the first floating gate electrode 54, and is higher than the gate insulating film 51. Further, the memory cell array end portion 56 is provided with a memory cell array end element isolation region 58 having an upper surface higher than the upper surface of the memory cell array element isolation region 57. This memory cell array end element isolation region 5
The height of the upper surface of 8 is equal to the height of the upper surface of the first floating gate electrode 54.

In the memory cell array 52, the second floating gate electrode 91 on each first floating gate electrode 54 has an upper surface of two element isolation regions 57 in the memory cell array which are in contact with two side surfaces of the first floating gate electrode 54. Is formed over a part of.

Further, at the memory cell array end 56, the first
The second floating gate electrode 92 on the floating gate electrode 54 is the element isolation region 5 in the memory cell array on the memory cell array side.
7 is formed on a part thereof and is formed in a stripe shape on the memory cell array end element isolation region 58 on the memory cell array end portion 56 side.

On the surface of each second floating gate electrode 91 and the surface of the element isolation region 57 in the memory cell array, an inter-gate insulating film 93 made of, for example, a laminated film of a silicon oxide film and a silicon nitride film is formed. There is. A control gate electrode 96 is formed on the inter-gate insulating film 93 by the polycrystalline silicon layer 94 and the silicide layer 95 thereon. Then, an element region 64 is formed in the vicinity of the surface of the semiconductor substrate 1 below the gate insulating film 51. The control gate electrode 96 has a laminated structure of a polycrystalline silicon layer 94 and a silicide layer 95, and the inter-gate insulating film 93 and the polycrystal in the control gate electrode 96 are provided between the second floating gate electrodes 91 in the memory cell array 52. It is filled with a silicon layer 94.

The cross section on the element region orthogonal to the "MN" line in FIG. 33 has the same configuration as that of FIG. 3 shown in the first embodiment.

As shown in FIG. 33, an element isolation region 57 in the memory cell array which isolates the element regions 64 from each other is formed in parallel with the element regions 64. A plurality of memory cell columns are formed so as to be sandwiched by the element isolation regions 57 in the memory cell array. In this memory cell row, the source / drain diffusion layers 65 at both ends below the adjacent floating gates 90 are shared with each other, and a plurality of memory cell transistors are connected in series to form a memory cell row. Here, the height of the upper surface of the element isolation region 57 in the memory cell array and the second
The level difference with the height of the upper surface of the floating gate electrode 91 defines the coupling ratio, so the size of the level difference is set so as to obtain the required coupling ratio. Here, unlike the first to fourth embodiments, a wing portion composed of the second floating gate electrode 91 is provided in the floating gate electrode to increase the surface area of the floating gate electrode 90 and increase the coupling ratio. ing.

Here, STI is used as the element isolation method. Here, in the memory cell array element isolation region 57 and the memory cell array end element isolation region 58, the first floating gate electrode 54 is provided in order to have an element isolation function.
The upper surface of the element isolation region is set to always be located above the upper surface of the lower gate insulating film 51, and is formed of, for example, a silicon oxide film. Further, although a plurality of element isolation regions 57 in the memory cell region are provided, all of them have the same width.

Further, the widths of the plurality of first floating gate electrodes 54 provided in the memory cell array 52 and the widths of the first floating gate electrodes 54 provided adjacent to the memory cell array end portion 56 are equal to each other. There is.

In the cross section shown in FIG. 32, one control gate electrode 96 is commonly provided in the memory cell array 52 to control each floating gate electrode 90. Although not shown, the exposed surface of each structure is covered with an interlayer insulating film made of BPSG or the like.

As described above, the height of the upper surface of the element isolation region in the memory cell array region is made lower than that in the outside of the memory cell array to provide a fine semiconductor memory device having an improved coupling ratio in the memory cell. You can

Here, the upper surface of the memory cell array end element isolation region 58 may be formed at a position higher than the upper surface of the first floating gate electrode 54. Further, the upper surface of the memory cell array end element isolation region 58 has the first floating gate electrode 54.
It may be formed at the same position as the upper surface of the. Further, the upper surface of the memory cell array end element isolation region 58 may be formed at a position lower than the upper surface of the first floating gate electrode 54 and higher than the upper surface of the in-memory cell array element isolation region 57.

The width of the first floating gate electrode 54 at the memory cell array end 56 may be equal to the width of the first floating gate electrode 54 in the memory cell array 52. Further, the width of the first floating gate electrode 54 at the memory cell array end 56 may be wider than the width of the first floating gate electrode 54 in the memory cell array 52.

The memory cell array end element isolation region 5
Alternatively, the second floating gate 92 may be provided with an opening on which the polycrystalline silicon layer is embedded. in this case,
The size of the opening is the same as the size of the opening between the second floating gates 91 on the element isolation region 57 in the memory cell array 52.

In the semiconductor memory device thus formed, the same effect as that of the semiconductor memory device of the fifth embodiment can be obtained.

According to the method of manufacturing the semiconductor memory device of the present embodiment, in the step of FIG. 30 showing the method of manufacturing the semiconductor memory device in the fifth embodiment, the etching condition is changed to form the tapered opening. It can be manufactured by providing on the element isolation region in each memory cell array and sequentially depositing an inter-gate insulating film, a polycrystalline silicon layer, and a silicide layer on the exposed surface.

In the method of manufacturing the semiconductor memory device of this embodiment, since the side surface of the second floating gate electrode is tapered, an inter-gate insulating film and a multi-gate insulating film are formed between adjacent floating gate electrodes on the element isolation region. It becomes easy to embed with a crystalline silicon layer. That is, on the element isolation region, the opening area can be formed larger above the opening portion between the adjacent floating gates than the corresponding portion of the semiconductor memory device of the fifth embodiment. Therefore, when the opening portion between the floating gate electrodes on the element isolation region is provided with the same depth as in the fifth embodiment, the frontage is wider than that in the fifth embodiment.
It becomes easy to fill the opening. In the fifth embodiment, the gap between the floating gate electrodes on the element isolation region is limited because the gap is filled narrowly. On the other hand, in the present embodiment, it is possible to narrow the limit of this step and embed a larger step. That is, on the element isolation region, the step difference between the element isolation region upper surface and the floating gate electrode upper surface is made larger,
The coupling ratio can be increased.

As in the second embodiment, the element region width L1 of the memory cell at the cell array edge can be made larger than the element region width L2 of the other memory cell. In this case, the same effect as that of the second embodiment can be obtained.

In addition to the above, the respective embodiments are not limited to the above.
It can be implemented in combination. The embodiments described above can be applied to various types of nonvolatile semiconductor memory devices such as NAND type and NOR type.

[0111]

According to the present invention, it is possible to provide a semiconductor memory device having an improved coupling ratio in a memory cell. Further, according to another feature of the present invention, it is possible to provide a method for manufacturing a semiconductor memory device in which a defect at the time of processing due to a defective coverage of the control gate electrode is prevented. Further, according to another feature of the present invention, it is possible to provide a method for manufacturing a semiconductor memory device with an improved margin in lithography for gate processing.

[Brief description of drawings]

FIG. 1 is a cross-sectional view taken along the “AB” line in FIG. 2 showing the structure of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a top view showing the structure of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view taken along the “CD” line in FIG. 2 showing the structure of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view of a step showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a sectional view of a step showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view of a step showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view of a step showing the method of manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 8 is a sectional view of a step showing the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 9 is a sectional view of a step showing the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 10 is a sectional view of a step showing the method for manufacturing the semiconductor memory device according to the first embodiment of the present invention.

FIG. 11 is a cross-sectional view taken along the line “EF” in FIG. 13 showing the structure of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 12 is a top view showing the structure of the semiconductor memory device according to the second embodiment of the present invention.

FIG. 13 is a cross-sectional view taken along the line “GH” in FIG. 14 showing the structure of the semiconductor memory device according to the third embodiment of the present invention.

FIG. 14 is a top view showing a structure of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 15 is a sectional view of a step showing a method for manufacturing a semiconductor memory device according to a third embodiment of the present invention.

FIG. 16 is a sectional view of a step showing the method for manufacturing the semiconductor memory device according to the third embodiment of the present invention.

FIG. 17 is a sectional view of a step showing the method for manufacturing the semiconductor memory device according to the third embodiment of the present invention.

FIG. 18 is a cross-sectional view of a process showing the method of manufacturing the semiconductor memory device according to the third embodiment of the present invention.

FIG. 19 is a sectional view taken along the line “IJ” in FIG. 20, showing the structure of the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 20 is a top view showing the structure of the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 21 is a sectional view of a step showing the method for manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 22 is a sectional view of a step showing the method of manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 23 is a cross-sectional view taken along the line “KL” in FIG. 24 showing the structure of the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 24 is a top view showing the structure of the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 25 is a sectional view of a step showing the method for manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 26 is a sectional view of a step showing the method of manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 27 is a sectional view of a step showing the method of manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 28 is a sectional view of a step showing the method of manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 29 is a sectional view of a step showing the method of manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 30 is a sectional view of a step showing the method for manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

FIG. 31 is a sectional view of a step showing the method of manufacturing the semiconductor memory device according to the fourth embodiment of the present invention.

32 is a cross-sectional view showing the structure of the semiconductor memory device according to the fifth embodiment of the present invention, taken along the line “MN” in FIG. 33.

FIG. 33 is a top view showing the structure of the semiconductor memory device according to the fifth embodiment of the present invention.

FIG. 34 is a sectional view showing a memory cell of an example of a conventional semiconductor memory device.

FIG. 35 is an equivalent circuit diagram showing a memory cell of an example of a conventional semiconductor memory device.

FIG. 36 is a sectional view showing a memory cell of another example of the conventional semiconductor memory device.

FIG. 37 is a cross-sectional view showing a structure in the vicinity of an end portion of a memory cell array in an example of a conventional semiconductor memory device.

FIG. 38 is a top view showing the structure near the end of the memory cell array in an example of a conventional semiconductor memory device.

FIG. 39 is a cross-sectional view showing a structure in the vicinity of an end portion of a memory cell array in another example of the conventional semiconductor memory device.

FIG. 40 is a top view showing a structure in the vicinity of an end portion of a memory cell array in another example of the conventional semiconductor memory device.

FIG. 41 is a cross-sectional view showing a defect near the end of the memory cell array in the conventional semiconductor memory device.

[Explanation of symbols]

1,50 Semiconductor substrate 2,51 Gate insulating film 3,52 memory cell array 4, 53, 90 Floating gate electrode 5,56 Edge of memory cell array 6,57 Element isolation region in memory cell array 7, 58 Memory cell array end element isolation region 8, 60, 93 Insulation film between gates 9, 61, 94 Polycrystalline silicon layer 10, 62, 95 silicide layer 11, 63, 96 Control gate electrode 12, 64 element area 13,65 Source / drain diffusion layer 20, 70 First polycrystalline silicon film 21,71 Mask material 22, 72 Memory cell array formation planned area 23, 73 Element isolation trench in memory cell array 24 Area to be formed on the edge of memory cell array 25,75 Memory cell array end element isolation trench 26, 76 Silicon oxide film 27, 78 Second polycrystalline silicon film 28, 36, 41, 77 Photoresist 29, 80 depression 30 memory cell array end element region 31 gate insulating film at end of memory cell array 32 Floating gate electrode at end of memory cell array 35, 40 memory cell array element isolation region 54 First Floating Gate Electrode 55, 91 Second floating gate electrode 59, 92 Second floating gate electrode at end of memory cell array 79 openings

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F083 EP03 EP04 EP13 EP23 EP54                       EP56 EP76 ER22 GA22 JA04                       JA35 JA39 JA53 NA01 PR05                       PR07 PR29 PR39 PR40 ZA28                 5F101 BA05 BA07 BA12 BA13 BA29                       BA36 BB05 BB17 BD34 BD35                       BE07 BH13 BH19

Claims (17)

[Claims] 1. A semiconductor substrate, a plurality of gate insulating films formed on the semiconductor substrate, a plurality of floating gate electrodes formed on the gate insulating film to form a memory cell array, and a space between the floating gate electrodes. And a height difference between the upper surface of the memory cell array and the upper surface of the floating gate electrode in the memory cell array end is greater than the height difference between the upper surface of the memory cell array end and the upper surface of the floating gate electrode. Device isolation region, an inter-gate insulating film formed on the surface of the floating gate electrode, a control gate electrode formed on the inter-gate insulating film, and a side surface of an end portion of the floating gate electrode in the semiconductor substrate. A semiconductor memory device having a source / drain diffusion layer formed below. 2. A semiconductor substrate, a plurality of gate insulating films formed on the semiconductor substrate, a plurality of floating gate electrodes formed on the gate insulating film to form a memory cell array, and a space between the floating gate electrodes. And a plurality of upper surfaces in the memory cell array, the height of the upper surface in the memory cell array is lower than the height of the upper surface of the floating gate electrode, and the height of the upper surface in the end of the memory cell array and the upper surface of the floating gate electrode. Element isolation regions of equal size, an intergate insulating film formed on the surface of the floating gate electrode, a control gate electrode formed on the intergate insulating film, and a side surface of the floating gate end portion in the semiconductor substrate. A semiconductor memory device having a source / drain diffusion layer formed below. 3. The semiconductor memory device according to claim 1, wherein the height of the upper surface of the element isolation region is higher than the height of the upper surface of the floating gate electrode at the end of the memory cell array. . 4. The semiconductor memory device according to claim 1, wherein the height of the upper surface of the element isolation region is formed lower than the height of the upper surface of the floating gate electrode at the end of the memory cell array. . 5. The width of the floating gate electrode at the end of the memory cell array is larger than the width of the floating gate electrode in the memory cell array.
5. The semiconductor memory device according to claim 4. 6. The gate insulating film has a silicon oxide film, and the floating gate electrode has a polycrystalline silicon layer,
The inter-gate insulating film has a laminated film of a silicon oxide film and a silicon nitride film, and the control gate electrode has a laminated structure of a polycrystalline silicon layer and a silicide layer. 6. The semiconductor memory device according to claim 1, wherein the inter-gate insulating film and the polycrystalline silicon layer in the control gate electrode are buried between the two. 7. A semiconductor substrate, a plurality of gate insulating films formed on the semiconductor substrate, a plurality of gate insulating films formed on the gate insulating film, and a first layer floating gate electrode and a second layer floating gate electrode. Then, a plurality of floating gate electrodes that constitute the memory cell array and a plurality of floating gate electrodes are provided between the first layer floating gate electrodes and at the end portion of the memory cell array. Isolation region in which the difference in height is larger than the difference in height between the upper surface at the end of the memory cell array and the upper surface of the first layer floating gate electrode, and the inter-gate insulation formed on the surface of the second layer floating gate electrode A film, a control gate electrode formed on the inter-gate insulating film, and a source / drain diffusion layer formed below a side surface of an end portion of the first layer floating gate electrode in the semiconductor substrate. And Bei, the element isolation region formed in the memory cell array end, a semiconductor memory device characterized by being formed under the second floating gate electrode. 8. A semiconductor substrate, a plurality of gate insulating films formed on the semiconductor substrate, a plurality of gate insulating films formed on the gate insulating film, and a first layer floating gate electrode and a second layer floating gate electrode. Then, a plurality of floating gate electrodes forming the memory cell array are provided between the first layer floating gate electrodes and at the end of the memory cell array, and the height of the upper surface in the memory cell array is equal to that of the first layer floating gate electrodes. The height of the upper surface at the end of the memory cell array is equal to the height of the upper surface of the first layer floating gate electrode, and the end is formed below the second layer floating gate electrode. An element isolation region, an inter-gate insulating film formed on the surface of the second floating gate electrode, a control gate electrode formed on the inter-gate insulating film, and a front surface of the semiconductor substrate. The semiconductor memory device characterized by comprising a source-drain diffusion layer formed under the first layer floating gate electrode end portion side. 9. The semiconductor according to claim 7, wherein the height of the upper surface of the element isolation region is formed higher than the height of the upper surface of the first layer floating gate electrode at the end of the memory cell array. Storage device. 10. The semiconductor according to claim 7, wherein the height of the upper surface of the element isolation region is lower than the height of the upper surface of the first layer floating gate electrode at the end of the memory cell array. Storage device. 11. The width of the first layer floating gate electrode at the end of the memory cell array is larger than the width of the first layer floating gate electrode in the memory cell array. 2. The semiconductor memory device according to item 1. 12. The gate insulating film has a silicon oxide film, the first layer floating gate electrode and the second layer floating gate electrode have a polycrystalline silicon layer, and the inter-gate insulating film has a silicon oxide film. Having a laminated film of a film and a silicon nitride film,
The control gate electrode has a stacked structure of a polycrystalline silicon layer and a silicide layer, and the control gate electrode has a second structure in the memory cell array.
11. The semiconductor memory device according to claim 7, wherein a polycrystalline silicon layer in the control gate electrode is embedded between the floating gate electrodes. 13. A step of forming a gate insulating film and a floating gate electrode layer on a semiconductor substrate, and a step of partially removing the semiconductor substrate, the gate insulating film and the floating gate electrode layer to form an element isolation insulating film. Depositing to define a memory cell array region, and stacking a floating gate electrode material on the floating gate electrode layer to form the element isolation insulating film and the upper surface of the floating gate electrode layer at the same height. A step of removing the element isolation region at the end of the memory cell array region and removing a part of the surface on the element isolation region in the memory cell array region to make it lower than the upper surface of the floating gate electrode layer. A method of manufacturing a semiconductor memory device, comprising: a step; and a step of forming a control gate electrode layer on the floating gate electrode layer. 14. A step of forming a gate insulating film and a floating gate electrode layer on a semiconductor substrate, and a step of partially removing the semiconductor substrate, the gate insulating film and the floating gate electrode layer to form an element isolation insulating film. Depositing to define a memory cell array region, removing the element isolation region at the end of the memory cell array region, and partially removing a surface on the element isolation region in the memory cell array region, Lowering the floating gate electrode layer from above, and removing part of the device isolation region at the end of the memory cell array region and the surface on the device isolation region in the memory cell array region to remove the edge of the memory cell array region. The upper surface of the element isolation region is higher than the upper surface of the floating gate electrode,
And, a step of making it higher than the upper surface of the element isolation region in the memory cell array area, a step of forming an inter-gate insulating film on the exposed surface of the floating gate electrode layer, and a control gate electrode layer on the inter-gate insulating film. And a step of forming the semiconductor memory device. 15. A step of forming a gate insulating film and a floating gate electrode layer on a semiconductor substrate, partly removing the semiconductor substrate, the gate insulating film and the floating gate electrode layer to form an element isolation insulating film. Depositing to define a memory cell array region, removing the element isolation region at the end of the memory cell array region, and partially removing a surface on the element isolation region in the memory cell region, Lowering the floating gate electrode layer from above, and removing part of the device isolation region at the end of the memory cell array region and the surface on the device isolation region in the memory cell array region to remove the edge of the memory cell array region. The device isolation region upper surface is lower than the floating gate electrode upper surface,
And, a step of making it higher than the upper surface of the element isolation region in the memory cell array area, a step of forming an inter-gate insulating film on the exposed surface of the floating gate electrode layer, and a control gate electrode layer on the inter-gate insulating film. And a step of forming the semiconductor memory device. 16. The width of the floating gate electrode layer at the end of the memory cell array is formed to be larger than the width of the floating gate electrode layer in the memory cell array in the step of defining the memory cell array region. A method of manufacturing a semiconductor memory device according to claim 13. 17. A device comprising: forming a gate insulating film and a first floating gate electrode layer on a semiconductor substrate; and partially removing the semiconductor substrate, the gate insulating film and the first floating gate electrode layer to form a device. A step of depositing an isolation insulating film to define a memory cell array region; a step of not removing the element isolation region at an end of the memory cell array region and partially forming a surface on the element isolation region in the memory cell array region; And removing the lower surface than the upper surface of the first floating gate electrode layer, and partially removing the surface of the element isolation region at the end of the memory cell array region and the element isolation region in the memory cell array region, Making the upper surface of the element isolation region at the end of the memory cell array region higher than the upper surface of the element isolation region in the memory cell array region; Forming a second floating gate electrode layer on the exposed surface of the first floating gate electrode layer; and forming a second floating gate electrode layer on the device isolation region in the memory cell array.
Removing the floating gate electrode layer to separate it into a plurality of second floating gate electrodes; forming an intergate insulating film on the exposed surface of the plurality of second floating gate electrodes; And a step of forming a control gate electrode layer thereon.