KR20000076879A - Semiconductor integrated circuit - Google Patents

Abstract

The present invention discloses a semiconductor integrated circuit device having a wiring layer formed in a portion where the trench isolation portion is removed. The apparatus includes a p-type silicon substrate, a shallow trench isolation portion formed on the p-type silicon substrate, and partitioning the first and second element regions on the substrate, a recess formed in the shallow trench isolation portion, and the recess portion. It has a conductive layer formed in it. The n-type source / drain region formed in the first element region is connected to the n-type source / drain region formed in the second element region using this conductive layer.

Description

Semiconductor integrated circuit device {SEMICONDUCTOR INTEGRATED CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a wiring layer formed in a portion from which an element isolation region is removed, and more particularly to a nonvolatile semiconductor memory device having a source line formed in a portion from which an STI element isolation region is removed.

1 is a perspective view of a memory cell array of a NOR type EEPROM having a source line formed by using a self matching source (hereinafter referred to as SAS) method.

The SAS method uses a word line WL, a resist, or the like as a mask to remove the element isolation insulating film 109 between the sources of each cell transistor, thereby exposing the p-type silicon substrate 101 between the word lines WL. It is a technique of forming the source line SL which consists of an n type diffused layer by introducing n type impurity into it.

Specifically, as shown in Fig. 1, the structure 114 including the floating gate FG, the word line WL, and the nitride film 113 and the sidewall insulating film 115 formed on the sidewall thereof are used as a mask in order from the lowest surface. Thus, the element isolation insulating film 109 present in the source line forming region is removed, and the p-type silicon substrate 101 is exposed to form a source line SL made of an n-type diffusion layer.

This SAS method can form the source line SL self-aligned with respect to the word line WL, and can fill the pitch between the word lines WL, which is advantageous for high integration.

The element isolation region 109 in the conventional NOR type EEPROM memory cell array is a LOCOS type formed using the LOCOS method, as shown in FIG.

On the other hand, in recent years, the shallow trench isolation portion STI has attracted attention as an element isolation for improving the degree of integration of a memory cell array. STI can reduce the occupied area on the chip as compared with the conventional LOCOS type device isolation region so that buzz big does not occur.

Fig. 2 is a perspective view of a memory cell array of NOR type EEPROMs separated by STI.

However, as shown in Fig. 2, when the source line SL is formed in the memory cell array element-separated by the STI 209 using the SAS method, the n-type diffusion layer 219 which must constitute the source line SL is formed. It may be segmented along the sidewall of the trench 207 for isolation. The reason for this is that n-type impurities are not sufficiently introduced into the sidewall of the trench 207.

As described above, in the NOR-type EEPROM device separated by STI, if the trench isolation portion is removed and then a wiring layer, that is, a source line is formed thereon, the source line is often disconnected, resulting in a decrease in manufacturing yield.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor integrated circuit device having a structure in which the wiring layer is not easily disconnected even when the wiring layer is formed in the portion where the trench isolation portion is removed.

1 is a perspective view of a memory cell array of a NOR type EEPROM having a source line formed by using a self-matching source method.

Fig. 2 is a perspective view of a memory cell array of shallow trench isolation NOR type EEPROMs having a source line formed using a self-matching source method.

3 is a circuit diagram of a NOR type EEPROM.

4A is a plan view of a NOR type EEPROM according to the first embodiment of the present invention.

4B is a cross-sectional view taken along a line 4B-4B in FIG. 4A.

4C is a cross-sectional view taken along a 4C-4C line in FIG. 4A.

4D is a cross-sectional view taken along a 4D-4D line in FIG. 4A.

5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K, and 5L, respectively, illustrate a NOR type EEPROM according to the first embodiment of the present invention. Perspective view in one manufacturing process.

6A, 6B, 6C, 6D, 6E, and 6F are perspective views in one manufacturing step of a NOR type EEPROM according to the second embodiment of the present invention, respectively.

7A is a plan view of a NOR type EEPROM according to the third embodiment of the present invention.

FIG. 7B is a sectional view taken along a line 7B-7B in FIG. 7A. FIG.

FIG. 7C is a cross-sectional view taken along a line 7C-7C in FIG. 7A. FIG.

FIG. 7D is a sectional view taken along a line 7D-7D in FIG. 7A; FIG.

8A, 8B, 8C, 8D, 8E, and 8F are perspective views in one manufacturing process of a NOR type EEPROM according to the third embodiment of the present invention, respectively.

9A and 9B are cross-sectional views of a NOR type EEPROM according to a modification of the third embodiment of the present invention, respectively.

10A is a plan view of a NOR type EEPROM according to the fourth embodiment of the present invention.

10B is a cross-sectional view taken along a line 10B-10B in FIG. 10A.

10C is a cross-sectional view taken along the line 10C-10C in FIG. 10A.

10D is a cross-sectional view taken along a line 10D-10D in FIG. 10A.

11A, 11B, 11C, and 11D are perspective views, each of which is a manufacturing step of a NOR type EEPROM according to a fourth embodiment of the present invention.

12A and 12B are cross-sectional views of a NOR type EEPROM according to a modification of the fourth embodiment of the present invention, respectively.

Fig. 13A is a plan view of a NOR type EEPROM according to the fifth embodiment of the present invention.

FIG. 13B is a cross-sectional view taken along a line 13B-13B in FIG. 13A.

13C is a cross-sectional view taken along a line 13C-13C in FIG. 13A.

13D is a cross-sectional view taken along a line 13D-13D in FIG. 13A.

14A, 14B, 14C, 14D, 14E, 14F, 14G, 14H, 14I, 14J, 14K and 14L are NOR types according to the fifth embodiment of the present invention, respectively. Perspective view in one manufacturing process of EEPROM.

Fig. 15A is a plan view of a NOR type EEPROM according to the sixth embodiment of the present invention.

15B is a cross-sectional view taken along a line 15B-l5B in FIG. 15A.

15C is a cross-sectional view taken along a line 15C-15C in FIG. 15A.

15D is a cross-sectional view taken along a line 15D-15D in FIG. 15A.

16A and 16B are cross-sectional views of a NOR type EEPROM according to a modification of the sixth embodiment of the present invention, respectively.

17A is a plan view of a NOR type EEPROM according to the seventh embodiment of the present invention.

FIG. 17B is a sectional view along 17B-17B in FIG. 17A; FIG.

FIG. 17C is a cross-sectional view taken along a line 17C-17C in FIG. 17A. FIG.

17D is a cross-sectional view taken along a line 17D-17D in FIG. 17A.

18A and 18B are cross-sectional views of a NOR type EEPROM according to a modification of the seventh embodiment of the present invention.

Fig. 1A is a plan view of a NOR type EEPROM according to the eighth embodiment of the present invention.

19B is a cross-sectional view taken along a line 19B-19B in FIG. 19A.

20 is a perspective view showing a first manufacturing method of a NOR type EEPROM according to the eighth embodiment of the present invention.

Fig. 2L is a perspective view showing a second manufacturing method of EEPROM according to the eighth embodiment of the present invention.

Fig. 22 is a cross-sectional view for explaining the purpose of a ninth embodiment of the present invention.

Fig. 23 is a sectional view of a NOR type EEPROM according to the ninth embodiment of the present invention.

24a, 24b, 24c, 24d, 24e, 24f, 24g, 24h, 24i, 24j, 24k, 24l, 24m, 24n, 24o, 24p, 24q Fig. 24R is a perspective view of one manufacturing step of a NOR type EEPROM according to the ninth embodiment of the present invention, respectively.

25 is a sectional view of a NOR type EEPROM according to a modification of the ninth embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

101: p-type silicon substrate

102: word line driver circuit

103: Y selector

104: Y select line drive circuit

106: source line driving circuit

109: device isolation insulating film

113: nitride film

115: sidewall insulating film

207: trench

209: STI

219 n-type diffusion layer

FG: Floating Gate

WL: word line

In order to achieve the above object, the present invention provides a trench formed in a semiconductor substrate of a first conductivity type, the trench partitioning first and second device regions in the semiconductor substrate; A first insulator formed in said trench, said first insulator electrically insulating said first and second device regions; First and second semiconductor regions of a second conductivity type formed in the first element region; Third and fourth semiconductor regions of a second conductivity type formed in the second element region; A gate electrode formed on the first device region between the first and second semiconductor regions, on the first insulator, and on the second device region between the third and fourth semiconductor regions; A recess formed in the first insulator-the recess exposes at least one of the first and second semiconductor regions from one sidewall of the trench, and exposes at least one of the third and fourth semiconductor regions to the other of the trench. Exposing from sidewalls; A conductive region formed in the recess, wherein the conductive region electrically connects at least one of the first and second semiconductor regions to at least one of the third and fourth semiconductor regions; There is provided a semiconductor integrated circuit device comprising a.

In the semiconductor integrated circuit device having the above structure, at least one of the first and second semiconductor regions is exposed from one sidewall of the trench, and at least one of the third and fourth semiconductor regions is exposed from the other sidewall of the trench. A part is formed in a 1st insulator. A conductive material is formed in the recess, and at least one of the first and second semiconductor regions is electrically connected to at least one of the third and fourth semiconductor regions by the conductive material.

In this manner, by connecting at least one of the first and second semiconductor regions to the third and fourth semiconductor regions through the conductive material formed in the recess, disconnection of the wiring layer along the sidewalls of the trench can be eliminated.

Moreover, the lowest surface of a recessed part is made lower than the surface of a 1st, 2nd element area | region. For this reason, the electrically conductive material formed in a recessed part can be formed using the maskless etch back method. That is, the semiconductor integrated circuit device has a structure in which a conductive material for electrically connecting semiconductor regions can be formed while suppressing an increase in the number of manufacturing steps.

Example

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described, referring drawings. In all the drawings, common parts are denoted by common reference numerals.

(1st embodiment)

First, an example of a circuit configuration of a NOR type EEPROM to which an embodiment of the present invention is applied will be described.

3 is a circuit diagram of a NOR type EEPROM.

As shown in FIG. 3, in the memory cell array 100 of the NOR type EEPROM, a plurality of nonvolatile memory cells MC are arranged in a matrix form. The plurality of nonvolatile memory cells MC are connected between one bit line BL and one source line SL. Gates of the plurality of nonvolatile memory cells MC arranged in the row direction are connected to different word lines WL1 to WL8, respectively. Word lines WL1 to WL8 are connected to word line driver circuits 102, respectively. The word line driver circuit 102 selectively drives any one of the word lines WL1 to WL8. The nonvolatile memory cells MC, which are connected to the selectively driven word line WL, are electrically connected to the bit lines BL1 to BL8, respectively. The bit lines BL1 to BL8 are connected to the Y selector 103. The Y selector 103 has a plurality of transistors YG whose one end of the current path is connected to the bit lines BL1 to BL8, respectively. Gates of the transistor YG are connected to different Y select lines YSLl to YSL4, respectively. The Y select lines YSL1 to YSL4 are connected to the Y select line driver circuit 104, respectively. The Y select line driver circuit 104 selectively drives any of the Y select lines YSL1 to YSL4. By selectively driving the transistor YG, in the circuit shown in Fig. 3, any one of the bit lines BL1 to BL4 is electrically connected to the read / write node 105-1, and any one of the bit lines BL5 to BL8 is read. It is electrically connected to the recording node 105-2. The read / write nodes 105-1, 105-2 are connected to read circuits and write circuits, not shown, respectively. As a result, data read / write is performed for the nonvolatile memory cell selected by the Y select line driver circuit 104 and the word line driver circuit 102.

In the memory cell array 100 of the EEPROM according to the first embodiment, the source lines SL include the local source lines SL1 to SL5 extending along the direction in which the word lines WL1 to WL8 extend (hereinafter referred to as ROW.D.). And a global source line GSL extending along the direction in which the bit lines BL1 to BL8 extend (hereinafter referred to as column direction: C0L.D.). The global source line GSL is connected to the source line driver circuit 106. The global source line GSL is connected to each of the local source lines SLl to SL5. The source potential of the nonvolatile memory cell MC is supplied from the source line driver circuit 106 to the local source lines SL1 to SL5 via the global source line GSL. 4A is a plan view of the broken line frame A1 shown in FIG.

4A is a plan view of a memory cell array of a NOR type EEPROM according to the first embodiment of the present invention, FIG. 4B is a sectional view taken along a line 4B-4B in FIG. 4A, FIG. 4C is a sectional view taken along a 4C-4C line in FIG. 4A, 4D is a cross-sectional view taken along line 4D-4D in FIG. 4A.

As shown in FIGS. 4A to 4D, the shallow trench 7 is formed in the p-type silicon substrate 1. This shallow trench 7 partitions the element region 8 formed in a stripe shape along the column direction on the p-type silicon substrate 1. In the shallow trench 7, TEOS for electrically insulating the element region 8 is embedded. This TEOS constitutes a shallow trench isolation section (hereinafter STI) 9. On each of the element regions 8 and the STIs 9, a plurality of stacked structures 14 are formed along the row direction crossing in the column direction. The laminated structure 14 includes a gate oxide film (SiO ₂ ) 2, a floating gate FG, a SiO ₂ / SiN / SiO ₂ (hereinafter, an ONO film 11), a word line WL, and a nitride film (SiN) 13, respectively. Include. The sidewall insulating film (SiN) 15 is formed on the sidewall of the laminated structure 14, and the laminated structure 14 is covered by an insulator different from the TEOS constituting the STI 9. In each of the device regions 8, n-type source regions S and n-type drain regions D of the memory cells MC are formed with the stacked structure 14 interposed therebetween. In the STI 9 adjacent to the n-type source region S, a concave portion 22 exposing the n-type source region S is formed. The lowest surface of the concave portion 22 is lower than the surface of the element region 8. In the recessed part 22, the electrically conductive layer 19 for connection which electrically connects n-type source regions S is formed. The local source line SL is configured by connecting the n-type source regions S along the row direction using the connection conductive layer 19. The bit line BL formed along the column direction is electrically connected to the n-type drain region D through the opening 21D formed in the interlayer insulating film 20. The global source line GSL formed along the column direction like the bit line BL is connected to the n-type source region S through the opening 21S formed in the interlayer insulating film 20.

The n-type drain region D of the memory cell MC under the global source line GSL is in an electrically floating state. That is, the memory cell MC under the global source line GSL does not function as a memory cell.

Next, an example of the manufacturing method of the NOR type EEPROM which concerns on 1st Embodiment is demonstrated.

5A to 5L are perspective views each showing a NOR-type EEPROM according to the first embodiment in order of major manufacturing steps. The perspective views shown in Figs. 5A to 5L respectively correspond to the parts in the frame A2 shown in Fig. 4A.

First, as shown in FIG. 5A, on the p-type silicon substrate 1, a gate oxide film (SiO ₂ ) 2, a conductive polysilicon film 3L serving as a floating gate, a nitride film (SiN) 4, The TEOS film 5 is formed in order. The TEOS film 5 is a silicon dioxide film formed using TEOS gas. In this specification, a silicon dioxide film formed using TEOS gas is conventionally called a TEOS film. Subsequently, the openings 6 along the STI formation region are formed in the TEOS film 5.

Next, as shown in FIG. 5B, the nitride film 4, the conductive polysilicon film 3L, the gate oxide film 2, and the p-type silicon substrate 1 are sequentially used using the TEOS film 5 as a mask. Etching is performed to form a shallow trench 7 in the p-type silicon substrate 1. As a result, the element region 8 is partitioned into the p-type silicon substrate 1.

Next, as shown in FIG. 5C, an insulator, for example, a TEOS film, which is an element isolation insulating film, is formed on the structure shown in FIG. 5B. Subsequently, the TEOS film is embedded in the shallow trench 7 by etching the RIE method using the nitride film 4 as a stopper, or by polishing the CMP method using the nitride film 4 as a stopper. As a result, the STI 9 is formed. Subsequently, the nitride film 4 is removed on the conductive polysilicon film 3L to expose the surface of the conductive polysilicon film 3L.

Next, as shown in FIG. 5D, on the structure shown in FIG. 5C, a conductive polysilicon film 3U serving as a floating gate is formed. Subsequently, in the conductive polysilicon film 3U, slits 10 for separating floating gates adjacent to the row direction are formed. Thereby, the conductive polysilicon film 3 which becomes a floating gate which consists of a laminated structure of the conductive polysilicon film 3U and the conductive polysilicon film 3L is formed along a column direction.

Next, as shown in FIG. 5E, on the structure shown in FIG. 5D, an insulating film for capacitively coupling the control gate (word line) to the floating gate, for example, SiO ₂ / SiN / SiO ₂ (hereinafter: ONO) A film 11, a conductive film serving as a control gate, for example, a conductive polysilicon film 12 and a nitride film (SiN) 13 are formed in this order.

Next, as shown in FIG. 5F, the nitride film 13, the conductive polysilicon film 12, the ONO film 11, the conductive polysilicon film 3, and the gate oxide film 2 are patterned. As a result, a stacked structure 14 including word lines WL (WL3, WL4) and floating gate FG is formed along the row direction.

Next, as shown in FIG. 5G, a nitride film (SiN) is formed on the structure shown in FIG. 5F, and the formed nitride film is etched using the RIE method. As a result, the sidewall insulating film 15 is formed along the sidewall of the laminated structure 14.

Next, as shown in FIG. 5H, the photoresist film 16 is formed on the structure shown in FIG. 5G. Subsequently, the opening 17 corresponding to the source line formation region is formed in the photoresist film 16. The opening 17 is formed in the row direction along the laminated structure 14 while exposing the nitride region 13, the sidewall insulating film 15, the element region 8 and the STI 9 between the laminated structure 14. do. Subsequently, using the photoresist film 16 as a mask, a part of the STI 9 exposed from the opening 17 is etched to form a recess 22 in the STI 9. The surface of the element region 8 is exposed from the recess 22. Moreover, the lowest surface (surface of STI9 in 1st Embodiment) of the recessed part 22 will become lower than the surface of the element area | region 8. FIG. In the figure, the part shown with 8E is the exposed surface of the element area | region 8 exposed by the recessed part 22. As shown in FIG. This step corresponds to the SAS method.

Next, as shown in FIG. 5I, after removing the photoresist film 16, the conductive material is deposited so that the recess 22 is completely filled to form the conductive film 18-1. In this first embodiment, the conductive material is deposited so that the thickness t of the conductive film 18-1 is the thickest on the recess 22. Examples of the conductive material constituting the conductive film 18-1 are silicides of a high melting point metal or a high melting point metal represented by titanium (T1), tungsten (W).

Next, as shown in FIG. 5J, the conductive film 18-1 is retracted by etching by the RIE method, and the conductive material is embedded in the recess 22. At this time, the conductive material may be embedded in the recess 22 by maskless etching using the thickness difference between the conductive films 18-1. Since the recessed part 22 is filled with the electrically conductive material, the connection conductive layer 19 which electrically connects the element regions 8 with each other via the exposed surface 8E is formed.

Next, as shown in FIG. 5K, n-type impurities are ion-implanted in the element region 8 using the stacked structure l4, the sidewall insulating film 15, and the STI 9 exposed on the surface as a mask. The n-type drain region D and the n-type source region S are formed, respectively. In addition, the n-type source regions S adjacent to the row direction are electrically connected by the connection conductive layer 19. As a result, source lines SL2 and SL3 are formed along the row direction. In addition, the depth of the n-type source region S is made deeper than the exposed surface 8E. This is to prevent a short circuit between the conductive layer 19 for connection and the p-type silicon substrate 1.

Next, as shown in FIG. 5L, an interlayer insulating film 20 is formed on the structure shown in FIG. 5K. Subsequently, the interlayer insulating film 20 is formed with the bit line opening 21D through the drain region D and the source line opening 21S through the source region S. Subsequently, the bit lines BL (BL4, BL5) electrically connected to the drain region D through the bit line opening 21D, and the global source line GSL electrically connected to the source region S through the source line opening 21S. Are formed along the column direction, respectively. Thereby, the NOR type EEPROM which concerns on 1st Embodiment of this invention is completed.

In the first embodiment thus formed, as shown in FIGS. 4A to 4D, the connection conductive layer 19 is embedded in the recess 22 formed by removing a part of the STI 9. have. The connection conductive layer 19 electrically connects n-type source regions S formed in the element region 8 via the exposed surface 8E. By having such a connection conductive layer 19, the disconnection of the local source line SL by the isolation | separation trench 7 can be suppressed. Therefore, even if the SAS method is used, the local source line SL can be reliably formed in the memory cell array separated by the STIs 9.

In addition, the connection conductive layer 19 is a structure embedded in the recessed part 22. According to this structure, when the conductive film 18-1 for forming the connection conductive layer 19 is deposited so as to be thickest on the concave portion 22, the connection conductive layer 19 can be formed without a mask. There is an advantage to being present.

(2nd embodiment)

The manufacturing process of the first embodiment is in the order of formation of the recess 22, deposition of the conductive material, etch back of the conductive material, formation of the n-type drain region D and the n-type source region S. FIG. However, this manufacturing process can also be changed in order of formation of n-type drain region D and n-type source region S, formation of recessed part 22, deposition of an electrically conductive material, and etchback of an electrically conductive material.

2nd Embodiment is the example which changed the order of a manufacturing process in this way.

6A to 6F are perspective views each showing a NOR type EEPROM according to the second embodiment in the order of major manufacturing steps. 6A to 6F respectively correspond to portions in the frame A2 shown in FIG. 4A.

First, according to the manufacturing method demonstrated by FIG. 5A-FIG. 5G, the structure shown in FIG. 6A is obtained.

Next, as shown in FIG. 6B, the n-type impurity is ion-implanted in the device region 8 using the stacked structure 14, the sidewall insulating film 15, and the STI 9 exposed on the surface as a mask. The n-type drain region D and the n-type source region S are formed, respectively.

Next, as shown in Fig. 6C, a photoresist film 16 is formed on the structure shown in Fig. 6B. Subsequently, the opening 17 corresponding to the source line formation region is formed in the photoresist film 16. The opening 17 is formed in the row direction along the laminated structure 14, exposing the nitride film 13, the sidewall insulating film l5, the element region 8 and the STI 9 between the stacked structure 14. . Subsequently, using the photoresist film 16 as a mask, a part of the STI 9 exposed from the opening 17 is etched to form a recess 22 in the STI 9. The surface of the element region 8 is exposed from the recess 22. Moreover, the lowest surface (surface of STI9 in 2nd Embodiment) of the recessed part 22 will become lower than the surface of the element area | region 8. FIG. In the figure, the part shown with 8E is the exposed surface of the element area | region 8 exposed by the recessed part 22. As shown in FIG.

Next, as shown in FIG. 6D, after the photoresist film 16 is removed, the conductive material is deposited to completely fill the recess 22 to form the conductive film 18-1. In this second embodiment, the conductive material is deposited so that the thickness t of the conductive film 18-1 is the thickest on the recess 22. Examples of the conductive material constituting the conductive film 18-1 are silicides of high melting point metals or high melting point metals represented by titanium (Ti) and tungsten (W).

Next, as shown in FIG. 6E, the conductive film 18-1 is retracted by etching by the RIE method, and the conductive material is embedded in the recess 22. At this time, the conductive material may be embedded in the concave portion 22 by the maskless etch back using the thickness difference of the conductive film 18-1. Since the recessed part 22 is filled with a electrically conductive material, the connection conductive layer 19 which electrically connects n-type source regions S through the exposed surface 8E is formed.

Next, as shown in FIG. 6F, an interlayer insulating film 20 is formed on the structure shown in FIG. 6E. Subsequently, in the interlayer insulating film 20, a bit line opening 21D through the drain region D and a source line opening 21S through the source region S are formed. Subsequently, the bit lines BL (BL4, BL5) electrically connected to the drain region D through the bit line opening 21D, and the global source line GSL electrically connected to the source region S through the source line opening 21S. Are formed along the column direction, respectively.

The NOR type EEPROM which concerns on 1st Embodiment can be formed also by the manufacturing process which concerns on such 2nd Embodiment.

(Third embodiment)

7A is a plan view of a NOR-type EEPROM according to the third embodiment of the present invention, FIG. 7B is a sectional view taken along a line 7B-7B in FIG. 7A, FIG. 7C is a sectional view taken along a line 7C-7C in FIG. 7A, and FIG. 7D is a view. It is sectional drawing along the 7D-7D line in 7a.

7A to 7D, the third embodiment differs from the first embodiment in that the p-type or undoped silicon film 18-2 is formed in the recess 22, and the silicon The n-type silicon region 29 for connection is formed in the film 18-2. The n-type silicon region 29 for connection electrically connects the n-type source regions S to each other.

Hereinafter, the NOR type EEPROM according to the third embodiment will be described in more detail according to an example of the manufacturing method thereof.

8A to 8F are perspective views each showing a NOR type EEPROM according to the third embodiment in order of major manufacturing steps. The perspective views shown in FIGS. 8A to 8F correspond to the parts in the frame A2 shown in FIG. 7A, respectively.

First, according to the manufacturing method demonstrated by FIGS. 5A-5G, the structure shown in FIG. 8A is obtained.

Next, as shown in FIG. 8B, the photoresist film 16 is formed on the structure shown in FIG. 8A. Subsequently, the opening 17 corresponding to the source line formation region is formed in the photoresist film 16. The opening 17 is formed in the row direction along the laminated structure 14 while exposing the nitride region 13, the sidewall insulating film 15, the element region 8 and the STI 9 between the laminated structure 14. do. Subsequently, using the photoresist film 16 as a mask, all of the STIs 9 exposed from the openings 17 are etched to form recesses 22 in the STIs 9. The surface of the element region 8 is exposed from the recess 22. In addition, the lowest surface (the surface of the p-type silicon substrate 1 exposed to the bottom of the trench 7 in the third embodiment) of the recess 22 is lower than the surface of the element region 8. In the figure, the part shown with 8E is the exposed surface of the element area | region 8 exposed by the shallow trench 7. This step corresponds to the SAS method.

Next, as shown in Fig. 8C, after removing the photoresist film 16, silicon is deposited to form a silicon film 18-2. The silicon film 18-2 is p-type silicon or undoped silicon. In addition, silicon may be either monocrystalline or polycrystalline.

Next, as shown in FIG. 8D, the silicon film 18-2 is etched back by the RIE method, and silicon is embedded in the shallow trench 7. As a result, the element regions 8 are connected by the same silicon film 18-2 as the p-type silicon substrate 1.

Next, as shown in FIG. 8E, the stacked structure 14, the sidewall insulating film 15, and the STI 9 exposed to the surface are used as the mask in the device region 8 and the silicon film 18-2. The n-type impurity is ion implanted to form an n-type drain region D, an n-type source region S, and an n-type silicon region 29 for connection, respectively. At this time, the n-type source regions S adjacent to the row direction are electrically connected by the connection n-type silicon region 29 formed in the silicon film 18-2. As a result, source lines SL2 and SL3 are formed along the row direction.

Next, as shown in FIG. 8F, an interlayer insulating film 20 is formed on the structure shown in FIG. 8E. Subsequently, the interlayer insulating film 20 is formed with the bit line opening 21D through the drain region D and the source line opening 21S through the source region S. Subsequently, the bit lines BL (BL4, BL5) electrically connected to the drain region D through the bit line opening 21D, and the global source line GSL electrically connected to the source region S through the source line opening 21S. Are formed along the column direction, respectively. Thereby, the NOR type EEPROM which concerns on 3rd Embodiment of this invention is completed.

In the third embodiment thus formed, as shown in FIGS. 7A to 7D, the silicon film 18-2 is embedded in the recess 22 between the element regions 8, and the silicon film ( An n-type silicon region 29 for connection is formed in 18-2). The n-type silicon region 29 for connection electrically connects the n-type source regions S formed in the element region 8 via the exposed surface 8E. By having such a connection n type silicon region 29, the disconnection of the local source line SL by the isolation | separation trench 7 can be suppressed like 1st Embodiment. Therefore, even if the SAS method is used, the local source line SL can be formed more reliably in the memory cell array separated by the STI 9.

Next, a modification of the NOR type EEPROM according to the third embodiment will be described.

9A and 9B are cross-sectional views of a NOR type EEPROM according to a modification of the third embodiment, respectively. In addition, the cross section shown in FIG. 9A corresponds to the cross section along the 7B-7B line in FIG. 7A, and the cross section shown in FIG. 9B corresponds to the cross section along the 7D-7D line in FIG. 7A.

In the third embodiment, although all of the STIs 9 in the shallow trenches 7 present in the source line forming region are removed, as shown in FIGS. 9A and 9B, the STI ( A part of 9) may be removed. Also, the silicon film 18-2 is embedded in a portion from which a part of the STI 9 is removed, and the n-type silicon region 29 for connection is formed in the embedded silicon film 18-2. Similarly, disconnection of the local source line SL by the isolation trench 7 can be suppressed.

In the first embodiment, the depth for removing the STI 9 is made shallower than the depth of the n-type source region S in order to prevent a short circuit between the connection conductive layer 19 and the p-type silicon substrate 1. In this modified example of the third embodiment, the depth from which the STI 9 is removed can be made deeper than the depth of the n-type source region S. Therefore, compared with the first embodiment, it is not necessary to monitor the removal of the STI 9 with high accuracy, which is advantageous for improving the production yield.

(4th embodiment)

Fig. 10A is a plan view of a NOR type EEPROM according to a fourth embodiment of the present invention, Fig. 10B is a sectional view taken along the line 10B-10B in Fig. 10A, Fig. 10C is a sectional view taken along the line 10C-10C in 10A, and Fig. 10D is Fig. 10A. It is sectional drawing along the 10D-10D line | wire in the inside.

As shown in Figs. 10A to 10D, the fourth embodiment uses the surfaces of the n-type silicon region 29 for connection described in the third embodiment to the n-type source region S and the n-type drain region D. At the same time silicided. In the figure, the part shown with 39 is the silicide layer of a high melting point metal.

Hereinafter, the NOR type EEPROM which concerns on 4th Embodiment is demonstrated in detail according to an example of the manufacturing method.

11A to 11D are perspective views each showing a NOR type EEPROM according to the fourth embodiment in order of major manufacturing steps. 11A-11D correspond to the part in the frame A2 shown to FIG. 10A, respectively.

First, according to the manufacturing method demonstrated by FIG. 5A-FIG. 5G and FIG. 8A-FIG. 8E, the structure shown in FIG. 8E demonstrated by 3rd Embodiment is obtained.

Next, as shown in Fig. 11A, a high melting point metal is deposited on the structure shown in Fig. 8E to form a high melting point metal film 18-3. Examples of the high melting point metals include titanium (Ti) and cobalt (Co).

Next, as shown in FIG. 11B, the structure shown in FIG. 11A is heat-treated, and the high melting metal film 18-3 is n-type drain region D, n-type source region S, and n-type silicon region for connection. (19) The silicide layer 39 is formed by reacting with each other. The silicidation at this time occurs only on the exposed surface of silicon and not on the STI 9 or the laminated structure 14 covered by the nitride films 13 and 15. This step of selectively silicidating only the exposed surface of silicon is also called salicide process.

If necessary, the nitride film 13 may be removed to expose the polysilicon gate to be suicided.

Next, as shown in Fig. 11C, the unreacted portion of the high melting point metal film 18-3 is removed.

Next, as shown in FIG. 11D, an interlayer insulating film 20 is formed on the structure shown in FIG. 11C. Subsequently, the interlayer insulating film 20 is provided with the bit line opening 21D through the silicide layer 38 on the drain region D and the source line opening 21S through the silicide layer 39 on the source region S. do. Subsequently, through the bit lines BL (BL4, BL5) and the source line openings 21S and the silicide layer 39 electrically connected to the drain region D through the bit line openings 21D and the silicide layer 39. Global source lines GSL electrically connected to the source region S are formed along the column direction, respectively. Thereby, the NOR type EEPROM which concerns on 4th Embodiment of this invention is completed.

In the fourth embodiment thus formed, as shown in FIGS. 10A to 10D, the silicon film 18-2 is disposed in the shallow trench 7 between the element regions 8 as in the third embodiment. The buried n-type silicon region 29 is formed in the silicon film 18-2. The n-type silicon region 29 for connection electrically connects the n-type source regions S formed in the element region 8 via the exposed surface 8E. The silicide layer 39 is formed over the n-type silicon region 29 for connection on the n-type source region S. The silicide layer 39 is lower in resistance than the n-type source region S and the n-type silicon region 29 for connection.

Thus, not only the n-type silicon region 29 for connection but also the silicide layer 39 formed on the n-type silicon region 29 for connection on the n-type source region S are provided in the isolation trench 7. The resistance of the local source line SL can be reduced while suppressing disconnection of the local source line SL. Therefore, according to the fourth embodiment, even if the SAS method is used, the local source line SL and the low resistance local source line SL can be formed more reliably in the memory cell array separated by the STIs 9.

Next, a modification of the NOR type EEPROM according to the fourth embodiment will be described.

12A and 12B are cross-sectional views of a NOR type EEPROM according to a modification of the fourth embodiment, respectively. 12A corresponds to the cross section taken along the line 10B-10B in FIG. 10A, and the cross section shown in FIG. 12B corresponds to the cross section taken along the line 10D-10D in FIG. 10A.

As shown in FIG. 12A and FIG. 12B, also in 4th Embodiment, it is possible to deform so that a part of STI9 may be removed similarly to 3rd Embodiment. A silicon film 18-2 is embedded in a portion from which a part of the STI 9 is removed, and an n-type silicon region 29 for connection is formed in the embedded silicon film 18-2, and the n-type source region S The silicide layer 39 is formed over the n-type silicon region 29 for connection. As a result, as described above, suppression of disconnection of the local source line SL and isolation of the local source line SL can be achieved simultaneously by the isolation portion trench 7.

(5th embodiment)

Although the first to fourth embodiments are examples of the case where the SAS method is used for the memory cell array, the present invention can also be applied to a memory cell array that does not use the SAS method. The fifth embodiment is an example of a memory cell array that does not use the SAS method.

13A is a plan view of a NOR type EEPROM according to the fifth embodiment of the present invention, FIG. 13B is a sectional view taken along a line 13B-13B in FIG. 13A, FIG. 13C is a sectional view taken along a line 13C-13C in 13A, and FIG. It is sectional drawing along the 13D-13D line | wire of the inside.

Hereinafter, the NOR type EEPROM which concerns on 5th Embodiment is demonstrated according to an example of the manufacturing method.

14A to 14L are perspective views each showing a NOR type EEPROM according to the fifth embodiment in order of major manufacturing steps. The perspective views shown in Figs. 14A to 14L respectively correspond to the parts in the frame A2 shown in Fig. 13A.

First, according to the manufacturing method demonstrated by FIGS. 5A-5C, the structure shown in FIG. 14A is obtained.

Next, as shown in FIG. 14B, a photoresist film 46 is formed on the structure shown in FIG. 14A. Subsequently, the opening 47 corresponding to the source line formation region is formed in the photoresist film 46. The opening 47 is formed in the row direction along the laminated structure 14 while exposing the conductive polysilicon film 3L and the STI 9.

Next, as shown in FIG. 14C, using the photoresist film 46 as a mask, all of the STIs 9 exposed from the openings 47 are etched, and the recesses 22 are formed in the STIs 9. ). The surface of the element region 8 is exposed from the recess 22. In addition, the lowest surface (the surface of the p-type silicon substrate 1 exposed to the bottom of the trench 7 in the fifth embodiment) of the recess 22 is lower than the surface of the element region 8. In the figure, the part shown with 8E is the exposed surface of the element area | region 8 exposed by the recessed part 22. As shown in FIG.

Next, as shown in Fig. 14D, the photoresist film 46 is removed.

Next, as shown in Fig. 14E, silicon is deposited on the structure shown in Fig. 14D so that the recesses 22 are completely filled to form the silicon film 18-2. In the fifth embodiment, silicon is deposited so that the thickness t of the silicon film 18-2 is the thickest on the recess 22. The silicon film 18-2 is p-type silicon or undoped silicon. In addition, silicon may be either monocrystalline or polycrystalline.

Next, as shown in FIG. 14F, the silicon film 18-2 is retracted by etching by a maskless RIE method, and silicon is embedded in the recess using the thickness difference of the silicon film 18-2. . In the fifth embodiment, the silicon film 18-2 is retracted by the CMP method so that the silicon can be embedded in the recess 22.

Next, as shown in Fig. 14G, on the structure shown in Fig. 14F, a conductive polysilicon film 3U serving as a floating gate is formed. Next, in the conductive polysilicon film 3U, slits 10 for separating floating gates adjacent to the row direction are formed. Thereby, the conductive polysilicon film 3 which becomes a floating gate which consists of a laminated structure of the conductive polysilicon film 3U and the conductive polysilicon film 3L is formed along a column direction.

Next, as shown in FIG. 14H, an insulating film for capacitively coupling the control gate (word line) to the floating gate, for example, the ONO film 11 and the conductive film serving as the control gate, on the structure shown in FIG. 14G. For example, the conductive polysilicon film 12 and the nitride film (SiN) 13 are sequentially formed.

Next, as shown in FIG. 14I, the nitride film 13, the conductive polysilicon film 12, the ONO film 11, the conductive polysilicon film 3, and the gate oxide film 2 are patterned. As a result, a stacked structure 14 including word lines WL (WL3, WL4) and floating gate FG is formed along the row direction.

Next, as shown in FIG. 14J, a nitride film (SiN) is formed on the structure shown in FIG. 14I, and the formed nitride film is etched using the RIE method. As a result, the sidewall insulating film 15 is formed along the sidewall of the laminated structure 14.

In the first to fourth embodiments, since the concave portion 22 is formed using the side wall insulating film 15 as a mask, the end portion of the concave portion 22 along the side wall insulating film 15 has a side wall insulating film ( Substantially coincides with the end of 15).

In contrast, in the fifth embodiment, as shown in the broken line source A3, the end portion of the concave portion 22 along the sidewall insulating film 15 can be present under the sidewall insulating film 15. According to this structure, the width | variety along the column direction of the recessed part 22 can be made larger than the space | interval between the side wall insulating films 15. As shown in FIG. For this reason, the cross-sectional area of the n-type silicon region 29 for connection formed in the silicon film 18-2 can be made larger than in the first to fourth embodiments, and there is an advantage that the resistance thereof can be lowered.

Next, as shown in FIG. 14K, n-type impurities are ion implanted in the element region 8 using the stacked structure 14, the sidewall insulating film 15, and the STI 9 exposed on the surface as a mask. Then, n-type drain region D, n-type source region S, and n-type silicon region 29 for connection are formed, respectively. At this time, the n-type source regions S adjacent to the row direction are electrically connected by the connection n-type silicon region 29 formed in the silicon film 18-2. As a result, source lines SL2 and SL3 are formed along the row direction.

Next, as shown in Fig. 14L, an interlayer insulating film 20 is formed on the structure shown in Fig. 14K. Subsequently, the interlayer insulating film 20 is formed with the bit line opening 21D through the drain region D and the source line opening 21S through the source region S. Subsequently, the bit lines BL (BL4, BL5) electrically connected to the drain region D through the bit line opening 21D, and the global source line GSL electrically connected to the source region S through the source line opening 21S. Are formed along the column direction, respectively. Thereby, the NOR type EEPROM which concerns on 5th Embodiment of this invention is completed.

In the fifth embodiment thus formed, as shown in FIGS. 13A to 13D, the silicon film 18-2 is embedded in the recess 22 formed by removing all of the STIs 9. have. Since the n-type silicon region 29 for connection is formed in the silicon film 18-2, disconnection of the local source line SL by the isolation trench 7 is performed as in the first to fourth embodiments. It can be suppressed. Therefore, the local source line SL can be formed more reliably in the memory cell array separated by the STI 9.

In addition, in the fifth embodiment, as shown by the broken line source A3 shown in FIG. 13D, the end portion of the recess 22 in the row direction can be positioned below the sidewall insulating film 15. According to this structure, the width | variety along the column direction of the connection n type silicon region 29 can be made larger than the width between the side wall insulating films 15, and the cross-sectional area of the connection n type silicon region 29 increases. . Therefore, there is an advantage that the resistance value of the source line SL can be lowered.

(6th Embodiment)

The sixth embodiment is an example in which the NOR type EEPROM described in the first embodiment is a memory cell array that does not use the SAS method as in the fifth embodiment.

15A is a plan view of a NOR-type EEPROM according to a sixth embodiment of the present invention, FIG. 15B is a sectional view taken along a line 15B-L5B in FIG. 15A, FIG. 15C is a sectional view taken along a line 15C-15C in FIG. 15A, and FIG. 15D is a view. It is sectional drawing along the 15D-15D line in 15a.

As shown in Figs. 5A to 15D, according to the sixth embodiment, similarly to the fifth embodiment, the end portion in the row direction of the recess 22 can be positioned below the sidewall insulating film 15. (See especially broken line A3 in Fig. 15D), the cross-sectional area of the conductive layer 19 for connection can be increased. Therefore, the resistance value of the source line SL can be lowered.

Further, the conductive material for the connection conductive layer 19 is selected by selecting a substance that is difficult to be etched in the etching at the time of forming the laminated structure 14 and the etching at the time of forming the sidewall insulating film 15. The lowest surface of the layer 19 can be made higher than the surface of the element region 8. According to this structure, since the connection conductive layer 19 can be brought into contact with the entire surface of the exposed surface 8E, the n-type source region S and the connection conductive layer 19 formed later in the element region 8 and There is an advantage that can lower the contact resistance.

Next, a modification of the NOR type EEPROM according to the sixth embodiment will be described.

16A and 16B are cross-sectional views of a NOR type EEPROM according to a modification of the sixth embodiment, respectively. In addition, the cross section shown in FIG. 16A corresponds to the cross section along the 15B-15B line in FIG. 15A, and the cross section shown in FIG. 16B corresponds to the cross section along the 15D-15D line in FIG. 15A.

As shown in Figs. 16A and 16B, the silicon film 18-2 may be formed in place of the connection conductive layer 19, and the n-type silicon region 29 for connection may be formed therein.

(Seventh embodiment)

The seventh embodiment is an example in which the NOR type EEPROM described in the fourth embodiment is a memory cell array that does not use the SAS method as in the fifth embodiment.

17A is a plan view of a NOR type EEPROM according to the seventh embodiment of the present invention, FIG. 17B is a sectional view taken along line 17B-17B in 17A, FIG. 17C is a sectional view taken along line 17C-17C in FIG. 17A, and FIG. 17D is FIG. 17A. It is sectional drawing along the 17D-17D line of the figure.

As shown in FIGS. 17A to 17D, according to the seventh embodiment, similarly to the fifth embodiment, an end portion in the row direction of the concave portion 22 can be positioned below the sidewall insulating film 15. (Especially see dashed line A3 in FIG. 17D), in particular, the cross-sectional area of the silicide layer 39 can be increased respectively. Therefore, the resistance value of the silicide layer 39 can be lowered.

Next, a modification of the NOR type EEPROM according to the seventh embodiment will be described.

18A and 18B are cross-sectional views of a NOR type EEPROM according to a modification of the seventh embodiment, respectively. In addition, the cross section shown in FIG. 18A corresponds to the cross section along the 17B-17B line in FIG. 17A, and the cross section shown in FIG. 18B corresponds to the cross section along the 17D-17D line in FIG. 17A.

As shown in FIGS. 18A and 18B, the recessed portion 22 of the seventh embodiment does not remove all the STIs 9, but as described in the modification of the fourth embodiment, It may be formed by removing a part.

(8th Embodiment)

In the first to seventh embodiments, the example in which the local source lines SL are connected in the row direction is illustrated, but the local source lines SL may be divided in the middle of the memory cell array.

In the eighth embodiment, the local source line SL is divided in the middle along the row direction of the memory cell array.

FIG. 19A is a plan view of a NOR type EEPROM according to an eighth embodiment of the present invention, and FIG. 19B is a sectional view taken along line 19B-19B in FIG. 19A.

In particular, as shown in FIG. 19B, the local source line SL3 is divided into the local source line SL3-1 and the local source line SL3-2 by the STI 9.

In this eighth embodiment, the local source line SL3-1 and the local source line SL3-2 are insulated by the STI9. From this structure, if the global source line connected to the local source line SL3-1 and the global source line connected to the local source line SL3-2 are separated, the local source line SL3-1 and the local source line SL3-1 are independent of each other. It is possible to obtain the advantage that it can be driven.

Next, a first example of a manufacturing method of the NOR type EEPROM according to the eighth embodiment will be described.

20 is a perspective view illustrating a first manufacturing method of the NOR type EEPROM according to the eighth embodiment. The process shown in FIG. 20 corresponds to the process shown in FIG. 5H especially of 1st Embodiment.

As shown in FIG. 20, the photoresist film 16 covers the STI 9 and the two openings 17-1 and 17-2 are formed along the row direction using the coated portion. If it can be obtained, the structure shown to FIG. 19A and 19B can be obtained.

Next, a second example of the manufacturing method of the NOR type EEPROM according to the eighth embodiment will be described.

21 is a perspective view illustrating a second manufacturing method of the NOR type EEPROM according to the eighth embodiment. The process shown in FIG. 21 corresponds to the process shown to FIG. 14B-14C especially of 5th Embodiment.

As shown in Fig. 21, the photoresist film 46 covers the STI 9, and as in the first manufacturing method, the two openings 47 are arranged along the row direction using this coated portion. -1,47-2) can be obtained to obtain the structure shown in Figs. 19A and 19B.

In addition, although 8th Embodiment demonstrated the apparatus which connects n type source region S by the connection conductive layer 19 like the 1st Embodiment as an example, 8th Embodiment is n type silicon for connection. The present invention can also be applied to each of the third embodiment in which the n-type source regions S are connected by the layer 29 and the fourth embodiment in which the silicide layer 39 is provided on the surface of the n-type silicon layer 29 for connection. Of course.

(Ninth embodiment)

It is sectional drawing for demonstrating the objective of 9th Embodiment of this invention.

As shown in FIG. 22, in the first embodiment, the connection conductive layer 19 is made of a conductive material in ohmic contact with the p-type silicon substrate 1, and the depth of the recess 22 is increased. When deeper than the n-type source region S, the connection conductive layer 19 is short-circuited to the p-type silicon substrate 1.

In this ninth embodiment, the connection conductive layer 19 is made of a conductive material in ohmic contact with the p-type silicon substrate 1, and the depth of the recess 22 is deeper than the n-type source region S. Even if it is, the semiconductor integrated circuit device which has a structure which can prevent the connection conductive layer 19 from short-circuiting to the p-type silicon substrate 1 is provided.

Fig. 23 is a sectional view of a NOR type EEPROM according to the ninth embodiment of the present invention. The cross section shown in FIG. 23 corresponds to the cross section taken along line 4B-4B shown in FIG. 4A.

As shown in FIG. 23, in the ninth embodiment, the nitride film 81 defining the exposed surface 8E is formed on the sidewall of the shallow trench 7.

Hereinafter, the NOR type EEPROM according to the ninth embodiment will be described in more detail according to an example of the manufacturing method thereof.

24A to 24R are perspective views each showing a NOR-type EEPROM according to the ninth embodiment in order of major manufacturing steps. The perspective views shown in FIGS. 24A to 24R respectively correspond to the parts in the frame A2 shown in FIG. 4A.

First, as shown in FIG. 24A, on the p-type silicon substrate 1, a gate oxide film (SlO ₂ ) 2, a conductive polysilicon film 3L serving as a floating gate, a nitride film (SiN) 4, The TEOS film 5 is formed in order. Subsequently, the openings 6 along the STI formation region are formed in the TEOS film 5.

Next, as shown in FIG. 24B, using the TEOS film 5 as a mask, the nitride film 4, the conductive polysilicon film 3L, the gate oxide film 2, and the p-type silicon substrate 1 are sequentially ordered. Etching is performed to form a shallow trench 7 in the p-type silicon substrate 1. As a result, the element region 8 is partitioned into the p-type silicon substrate 1.

Next, as shown in FIG. 24C, a nitride film (SiN) 81 is formed on the structure shown in FIG. 24B.

Next, as shown in FIG. 24D, a photoresist film 82 is formed on the structure shown in FIG. 24C.

Next, as shown in FIG. 24E, the photoresist film 82 is exposed to expose the surface portion thereof. At this time, the part in the shallow trench 7 of the photoresist film 82 is made into unexposed.

Next, as shown in FIG. 24F, the photosensitive portion of the photoresist film 82 is removed to leave the photoresist film 82 in the shallow trench 7.

Next, as shown in FIG. 24G, the nitride film is obtained by using the TEOS film 5 and the photoresist film 82 as a stopper until the exposed surface 8E of the element region 8 is obtained by the RIE method. Etch 81.

Next, as shown in FIG. 24H, the photoresist film 82 is removed. As a result, the sidewalls of the shallow trenches 7 are covered by the nitride film 81 except for the exposed surface 8E.

Next, as shown in FIG. 24I, on the structure shown in FIG. 24H, an insulator, for example, TEOS, which is an element isolation insulating film, is deposited to form a TEOS film. Subsequently, the TEOS film is etched by RIE using the nitride film 4 as a stopper, or polished by CMP using the nitride film 4 as a stopper, and the TEOS is embedded in the shallow trench 7. do. As a result, the STI 9 is formed. Subsequently, the nitride film 4 is removed from the conductive polysilicon film 3L to expose the surface of the conductive polysilicon film 3L.

Next, as shown in FIG. 24J, a conductive polysilicon film 3U serving as a floating gate is formed on the structure shown in FIG. 24I. Subsequently, in the conductive polysilicon film 3U, slits 10 for separating floating gates adjacent to the row direction are formed. Thereby, the conductive polysilicon film 3 used as a floating gate which consists of a laminated structure of the conductive polysilicon film 3U and the conductive polysilicon film 3L is formed along the column direction.

Next, as shown in FIG. 24K, on the structure shown in FIG. 24J, an insulating film for capacitively coupling the control gate (word line) to the floating gate, for example, the ONO film 11 and the conductive film serving as the control gate. For example, the conductive polysilicon film 12 and the nitride film (SiN) 13 are sequentially formed.

Next, as shown in FIG. 24L, the nitride film 13, the conductive polysilicon film 12, the ONO film 11, the conductive polysilicon film 3, and the gate oxide film 2 are patterned. Accordingly, the stacked structure 14 including the word lines WL (WL3, WL4) and the floating gate FG is formed along the row direction.

Next, as shown in FIG. 24M, a nitride film (SiN) is formed on the structure shown in FIG. 24L, and the formed nitride film is etched using the RIE method. As a result, the sidewall insulating film 15 is formed along the sidewall of the laminated structure 14.

Next, as shown in FIG. 24N, a photoresist film 16 is formed on the structure shown in FIG. 24M. Subsequently, the opening 17 corresponding to the source line formation region is formed in the photoresist film 16. The opening 17 is formed in the row direction along the laminated structure 14 while exposing the nitride region 13, the sidewall insulating film 15, the element region 8 and the STI 9 between the laminated structure 14. do. Subsequently, using the photoresist film 16 as a mask, all of the STIs 9 exposed from the openings 17 are etched to form recesses 22 in the STIs 9. The surface of the element region 8 is exposed from the recess 22. In addition, the lowest surface (the surface of the nitride film 81 in the ninth embodiment) of the recess 22 is lower than the surface of the element region 8. This step corresponds to the SAS method.

Next, as shown in FIG. 24O, after the photoresist film 16 is removed, the conductive material is deposited to completely fill the recess 22 to form the conductive film 18-1. In the ninth embodiment, the conductive material is deposited so that the thickness t of the conductive film 18-1 is the thickest on the recess 22. Examples of the conductive material constituting the conductive film 18-1 are silicides of high melting point metals or high melting point metals represented by titanium (Ti) and tungsten (W).

Next, as shown in FIG. 24P, the conductive film 18-1 is retracted by etching by a maskless RIE method, and the conductive material is recessed using the thickness difference of the conductive film 18-1. Landfill in 22). Thereby, the connection conductive layer 19 which electrically connects the element regions 8 with each other via the exposed surface 8E is formed.

Next, as shown in FIG. 24Q, an n-type impurity is ion-implanted in the element region 8 using the stacked structure 14, the sidewall insulating film 15, and the STI 9 exposed on the surface as a mask. Then, n-type drain region D and n-type source region S are formed, respectively. In addition, the n-type source regions S adjacent to the row direction are electrically connected by the connection conductive layer 19. As a result, source lines SL2 and SL3 are formed along the row direction. In addition, the depth of the n-type source region S is made deeper than the exposed surface 8E. This is to prevent a short circuit between the conductive layer 19 for connection and the p-type silicon substrate 1.

Next, as shown in FIG. 24R, the interlayer insulating film 20 is formed on the structure shown in FIG. 24Q. Subsequently, the interlayer insulating film 20 is formed with the bit line opening 21D through the drain region D and the source line opening 21S through the source region S. Subsequently, the bit lines BL (BL4, BL5) electrically connected to the drain region D through the bit line opening 21D, and the global source line GSL electrically connected to the source region S through the source line opening 21S. Are formed along the column direction, respectively. Thereby, the NOR type EEPROM which concerns on 9th Embodiment of this invention is completed.

In the ninth embodiment thus formed, the portion where the connection conductive layer 19 and the element region 8 contact can be defined as the exposed surface 8E obtained by removing the nitride film 81. Therefore, even if the depth of the recessed part 22 becomes deeper than n type source region S, the connection conductive layer 19 and the board | substrate 1 will not short-circuit. Therefore, compared with the first embodiment, it is not necessary to monitor the removal amount of the STI 9 with high accuracy, which is advantageous for improving the production yield.

Next, a modification of the NOR type EEPROM according to the ninth embodiment will be described.

25 is a sectional view of a NOR type EEPROM according to a modification of the ninth embodiment of the present invention. The cross section shown in FIG. 25 is corresponded to the cross section along the 4B-4B line shown to FIG. 4A.

In the ninth embodiment, although all of the STIs 9 in the shallow trenches present in the source line forming region are removed, a portion of the STIs 9 may be removed as shown in FIG.

In this case, the nitride film 81 may be formed only on the sidewalls of the shallow trenches 7, and when the nitride film 81 is etched, a photoresist film is formed to cover the nitride film 81 at the bottom of the shallow trenches 7. It is also possible to omit the step of leaving the photoresist film in the shallow trench 7.

In addition, in the ninth embodiment, as in the eighth embodiment, the source line SL can be divided in the middle along the row direction of the memory cell array.

As mentioned above, although this invention was demonstrated by 1st-9th embodiment, this invention is not limited to these embodiment and can be variously modified in the range which does not deviate from the meaning.

For example, in the above embodiment, an example in which the present invention is applied to the source line of the NOR type EEPROM has been described, but the present invention can also be applied to the source line of the NAND type EEPROM.

In addition, the present invention can be applied as long as it is not only the source line but also the wiring layer formed in the portion where the STI 9 is removed.

In the above embodiment, as a transistor, a MOSFET having a threshold variable type having a floating gate FG for accumulating electric charges between the word line WL and the element region 8 and changing the threshold voltage by the amount of electric charges accumulated therein. Illustrated. However, the transistor may be changed to a normal MOSFET having no floating gate.

As described above, according to the present invention, even if the wiring layer is formed in the portion where the trench isolation portion is removed, the semiconductor integrated circuit device having the structure in which the wiring layer is not easily disconnected can be provided.

Claims (23)

A trench formed in a semiconductor substrate of a first conductivity type and separating first and second device regions from the semiconductor substrate; A first insulator formed in the trench to electrically insulate the first and second device regions from each other; First and second semiconductor regions of a second conductivity type formed in the first element region; Third and fourth semiconductor regions of a second conductivity type formed in the second element region; A gate electrode formed on the first device region between the first and second semiconductor regions, on the first insulator, and on the second device region between the third and fourth semiconductor regions; A recess formed in the first insulator-the recess exposes at least one of the first and second semiconductor regions from one sidewall of the trench, and exposes at least one of the third and fourth semiconductor regions to the other of the trench. Exposing from sidewalls; And A conductive region formed in said recess and electrically connecting at least one of said first and second semiconductor regions to at least one of said third and fourth semiconductor regions; Semiconductor integrated circuit device comprising a. The semiconductor integrated circuit device according to claim 1, wherein the gate electrode is covered with a second insulator having an etching rate different from that of the first insulator. The semiconductor integrated circuit device according to claim 2, wherein the second insulator is formed on the first insulator. 4. The semiconductor integrated circuit device according to claim 3, wherein a part of said second insulator is formed in said recessed portion. The semiconductor integrated circuit device according to claim 1, wherein the uppermost surface of the conductive material is at a position higher than the surfaces of the first and second device regions. 3. The semiconductor integrated circuit device according to claim 2, wherein the uppermost surface of the conductive material is at a position higher than the surfaces of the first and second device regions. The semiconductor device of claim 1, further comprising a third insulator formed along a bottom surface of the trench, one sidewall of the trench, and another sidewall of the trench. The third insulator may include a first exposed part exposing at least one of the first and second semiconductor regions through one sidewall of the trench, and And a second exposed portion exposing at least one of the third and fourth semiconductor regions through the other sidewall of the trench. The method of claim 1, wherein the conductive material includes at least one of a high melting point metal, a high melting point metal silicide, a second conductivity type silicon, and a laminated structure of a second conductivity type silicon and a high melting point metal silicide. A semiconductor integrated circuit device, characterized in that. The semiconductor device of claim 1, further comprising: a first charge storage layer formed between the gate electrode and the first device region; A second charge accumulation layer formed between the gate electrode and the second device region Semiconductor integrated circuit device further comprising. The semiconductor device of claim 2, further comprising: a first charge storage layer formed between the gate electrode and the first device region; A second charge accumulation layer formed between the gate electrode and the second device region Semiconductor integrated circuit device further comprising. The semiconductor device of claim 3, further comprising: a first charge accumulation layer formed between the gate electrode and the first device region; A second charge accumulation layer formed between the gate electrode and the second device region Semiconductor integrated circuit device further comprising. The semiconductor device of claim 4, further comprising: a first charge storage layer formed between the gate electrode and the first device region; A second charge accumulation layer formed between the gate electrode and the second device region Semiconductor integrated circuit device further comprising. The semiconductor device of claim 5, further comprising: a first charge storage layer formed between the gate electrode and the first device region; A second charge accumulation layer formed between the gate electrode and the second device region Semiconductor integrated circuit device further comprising. The semiconductor device of claim 6, further comprising: a first charge storage layer formed between the gate electrode and the first device region; A second charge accumulation layer formed between the gate electrode and the second device region Semiconductor integrated circuit device further comprising. The semiconductor device of claim 7, further comprising: a first charge storage layer formed between the gate electrode and the first device region; A second charge accumulation layer formed between the gate electrode and the second device region Semiconductor integrated circuit device further comprising. The semiconductor device of claim 8, further comprising: a first charge storage layer formed between the gate electrode and the first device region; A second charge accumulation layer formed between the gate electrode and the second device region Semiconductor integrated circuit device further comprising. A trench formed in the semiconductor substrate of the first conductivity type; An insulator formed in the trench; A gate electrode formed on the semiconductor substrate; A recess formed in the insulator; A semiconductor formed in the recess; A semiconductor region of a second conductivity type formed in the semiconductor substrate and the semiconductor Semiconductor integrated circuit device comprising a. Forming a trench in the first conductive semiconductor substrate; Forming an insulator in the trench; Forming a gate electrode on the semiconductor substrate; Forming a recess in the insulator; Forming a semiconductor in the recess; Forming a semiconductor region of a second conductivity type in the semiconductor substrate and the semiconductor Method of manufacturing a semiconductor integrated circuit device comprising a. A trench formed in the semiconductor substrate of the first conductivity type; A first insulator formed in said trench; A gate electrode formed on the semiconductor substrate; A second insulator formed on said gate electrode, said second insulator having an etch rate different from that of said first insulator; A recess formed in the first insulator; A semiconductor formed in the recess; A semiconductor region of a second conductivity type formed in the semiconductor substrate and the semiconductor Semiconductor integrated circuit device comprising a. Forming a trench in the first conductive semiconductor substrate; Forming a first insulator in the trench; Forming a gate electrode on the semiconductor substrate; Forming a second insulator on the gate electrode, the second insulator having an etch rate different from that of the first insulator; Forming a recess in the first insulator using at least the second insulator as a mask; Forming a semiconductor in the recess; Forming a semiconductor region of a second conductivity type in the semiconductor substrate and the semiconductor Method of manufacturing a semiconductor integrated circuit device comprising a. Forming a trench in the first conductive semiconductor substrate; Forming a first insulator in the trench; Forming a recess in the first insulator; Forming a semiconductor in the recess; Forming a gate electrode on the semiconductor substrate after forming a semiconductor in the recess; Forming a second insulator on the gate electrode, the second insulator having an etch rate different from that of the first insulator; Forming a semiconductor region of a second conductivity type in the semiconductor substrate and the semiconductor Method of manufacturing a semiconductor integrated circuit device comprising a. A trench formed in the semiconductor substrate of the first conductivity type; A first insulator formed along a bottom surface of the trench, one sidewall of the trench, and another sidewall of the trench, wherein the first insulator includes a first exposed portion exposing the semiconductor substrate through one sidewall of the trench and a portion of the trench. Having a second exposed portion exposing the semiconductor substrate through another sidewall; A second insulator formed in said trench; A gate electrode formed on the semiconductor substrate; A recess formed in the second insulator; A semiconductor formed in the recess; A semiconductor region of a second conductivity type formed in the semiconductor substrate and the semiconductor Semiconductor integrated circuit device comprising a. Forming a trench in the first conductive semiconductor substrate; Forming a first insulator along a bottom surface of the trench, one sidewall of the trench, and another sidewall of the trench, wherein the first insulator comprises: a first exposed portion exposing the semiconductor substrate through one sidewall of the trench; And a second exposed portion exposing the semiconductor substrate through another sidewall of the trench; Forming a second insulator in the trench; Forming a gate electrode on the semiconductor substrate; Forming a recess in the second insulator; Forming a semiconductor in the recess; Forming a semiconductor region of a second conductivity type in the semiconductor substrate and the semiconductor Method of manufacturing a semiconductor integrated circuit device comprising a.