CN1267091A

CN1267091A - Semiconductor IC device

Info

Publication number: CN1267091A
Application number: CN00104057.XA
Authority: CN
Inventors: 北村章太
Original assignee: Toshiba Corp
Current assignee: Toshiba Corp
Priority date: 1999-03-16
Filing date: 2000-03-16
Publication date: 2000-09-20
Also published as: KR20000076879A; TW463168B; JP2000269467A

Abstract

The present invention discloses a kind of semiconductor integrated circuit that includes the wiring layer formed on a portion where trench isolations are removed. The present apparatus includes the followings: p-type silicon substrate; shallow trench isolations, which are formed on the p-type silicon substrate where the first and the second devices are formed; recess portions, which are formed on the shallow trench isolation; and the conduction layer, which is formed on the recess portion. The conduction layer is used to connect n-type source/drain region formed in the first device region with n-type source/drain region formed in the second device region.

Description

Conductor integrated circuit device

The background of invention

The present invention relates to have the conductor integrated circuit device of the wiring layer that on the part of having removed device isolation regions, forms, specifically, relate to Nonvolatile semiconductor memory device with the source electrode line that on the part of having removed the STI device isolation regions, forms.

Fig. 1 is the oblique view with NOR type EEPROM memory cell array of the source electrode line that forms with autoregistration source electrode method (below, be called SAS).

So-called SAS method, be a kind of like this technology: adopt with word line WL and photoresist etc. as mask, remove the way of the device isolation dielectric film 109 between the source electrode of each cell transistor, make and between word line WL, expose p type silicon substrate 101, by to the way that imports n type impurity here, form the source electrode line SL that constitutes by n type diffusion layer again.

Specifically, as shown in Figure 1, from bottom surface, with structure 114 that comprises floating grid FG, word line WL, nitride film 113 and the side wall insulating film 115 that forms on its sidewall is mask, remove and be present in source electrode line and form device isolation film 109 in the zone, p type silicon substrate 101 is exposed, form the source electrode line SL that constitutes by the n diffusion layer here.

Such SAS method can form source electrode line SL with respect to word line WL oneself coupling ground, can shorten the pitch between word line WL, for highly integrated be favourable.

Device isolation regions 109 in the memory cell array of existing NOR type EEPROM as shown in Figure 1, is the LOCOS type that forms with the LOCOS method.

To this, in the last few years, as the device isolation that improves the memory cell array integrated level, shallow-trench isolation (STI) had been subjected to people and had noted.The device isolation regions ratio of STI and existing LOCOS type, the occupied area of chip top can dwindle the so big amount corresponding with the amount that does not produce beak.

Fig. 2 is the oblique view that carries out NOR type EEPROM memory cell array with STI.

But as shown in Figure 2, if form source electrode line SL with the SAS method on the memory cell array of carrying out device isolation with STI209, the n type diffusion layer 219 that then should constitute source electrode line SL sometimes can be along isolation channel 207 disjunctions of isolating usefulness.Its reason is to import n type impurity on the sidewall of isolation channel 207 fully.

So, carry out if after having removed slot liner, forming wiring layer here among the NOR type EEPROM with STI, promptly form source electrode line, then such situation can take place: this source electrode line usually can break, and the rate that manufactures a finished product is reduced.

The general introduction of invention

The present invention because above-mentioned situation and inventing, even if its objective is that providing a kind of has formed wiring layer having removed on the part that groove isolates, also has the conductor integrated circuit device of the structure that is difficult to make this wiring layer broken string,

For achieving the above object, in the present invention, conductor integrated circuit device possesses:

The groove that forms in the Semiconductor substrate of the 1st conduction type, this groove are isolated the 1st, the 2nd device area in above-mentioned Semiconductor substrate;

The 1st insulant that forms in above-mentioned groove, the 1st insulant make above-mentioned the 1st, the 2nd device area carry out electric insulation to each other;

The the 1st, the 2nd semiconductor regions of the 2nd conduction type that in above-mentioned the 1st device area, forms;

The the 3rd, the 4th semiconductor regions of the 2nd conduction type that in above-mentioned the 2nd device area, forms;

The gate electrode that the 2nd device area top between above-mentioned the 1st device area top of above-mentioned the 1st, the 2nd semiconductor regions, above-mentioned the 1st insulant top and above-mentioned the 3rd, the 4th semiconductor regions forms;

The recess that on above-mentioned the 1st insulant, forms, at least one side that this recess makes above-mentioned the 1st, the 2nd semiconductor regions exposes from a sidewall of above-mentioned groove, at least one side who makes above-mentioned the 3rd, the 4th semiconductor regions from another sidewall of above-mentioned groove expose and

The conductive region that forms in above-mentioned recess, this conductive region are electrically connected at least one side of above-mentioned the 3rd, the 4th semiconductor regions at least one side of above-mentioned the 1st, the 3rd semiconductor regions.

If have the conductor integrated circuit device of above-mentioned formation, then in the 1st insulant, form at least one side make above-mentioned the 1st, the 2nd semiconductor regions and expose, the recess that expose of at least one side who makes above-mentioned the 3rd, the 4th semiconductor regions from another sidewall of above-mentioned groove from a sidewall of above-mentioned groove.Then, in this recess, form conducting objects, and at least one side of above-mentioned the 1st, the 3rd semiconductor regions is electrically connected at least one side of above-mentioned the 3rd, the 4th semiconductor regions with this conducting objects.

So, exist in the conducting objects ground that forms in the recess in the middle of adopting at least one side of the 1st, the 2nd semiconductor regions be connected to way on the 3rd, the 4th semiconductor regions, just can eliminate wiring layer along the sidewall of groove break phenomenon.

In addition, the bottom surface of this recess forms also lowlyer than the surface of the 1st, the 2nd device area.Therefore, the conducting objects that forms in recess can form with maskless etching method.That is, above-mentioned conductor integrated circuit device has such structure: can be in the increase that suppresses the worker ordinal number, and form and be used for conducting objects that semiconductor regions is electrically connected to each other.

The simple declaration of accompanying drawing

Fig. 1 is the oblique view of memory cell array with NOR type EEPROM of the source electrode line that forms with autoregistration source electrode method.

Fig. 2 is the oblique view of memory cell array of NOR type EEPROM with shallow-trench isolation type of the source electrode line that forms with autoregistration source electrode method.

Fig. 3 is the circuit diagram of NOR type EEPROM.

Fig. 4 A is the plane graph of the NOR type EEPROM of embodiments of the invention 1.

Fig. 4 B is the profile along the 4B-4B line among Fig. 4 A.

Fig. 4 C is the profile along the 4C-4C line among Fig. 4 A.

Fig. 4 D is the profile along the 4D-4D line among Fig. 4 A.

Fig. 5 A, Fig. 5 B, Fig. 5 C, Fig. 5 D, Fig. 5 E, Fig. 5 F, Fig. 5 G, Fig. 5 H, Fig. 5 I, Fig. 5 J, Fig. 5 K and Fig. 5 L are respectively the oblique views in the manufacturing process of NOR type EEPROM of embodiments of the invention 1.

Fig. 6 A, Fig. 6 B, Fig. 6 C, Fig. 6 D, Fig. 6 E and Fig. 6 F are respectively the oblique views in the manufacturing process of NOR type EEPROM of embodiments of the invention 2.

Fig. 7 A is the plane graph of the NOR type EEPROM of embodiments of the invention 3.

Fig. 7 B is the profile along the 7B-7B line among Fig. 7 A.

Fig. 7 C is the profile along the 7C-7C line among Fig. 7 A.

Fig. 7 D is the profile along the 7D-7D line among Fig. 7 A.

Fig. 8 A, Fig. 8 B, Fig. 8 C, Fig. 8 D, Fig. 8 E and Fig. 8 F are respectively the oblique views in the manufacturing process of NOR type EEPROM of embodiments of the invention 3.

Fig. 9 A and Fig. 9 B are respectively the profiles of NOR type EEPROM of a variation of embodiments of the invention 3.

Figure 10 A is the plane graph of the NOR type EEPROM of embodiments of the invention 4.

Figure 10 B is the profile along the 10B-10B line among Figure 10 A.

Figure 10 C is the profile along the 10C-10C line among Figure 10 A.

Figure 10 D is the profile along the 10D-10D line among Figure 10 A.

Figure 11 A, Figure 11 B, Figure 11 C and Figure 11 D are respectively the oblique views in the manufacturing process of NOR type EEPROM of embodiments of the invention 4.

Figure 12 A and Figure 12 B are respectively the profiles of NOR type EEPROM of a variation of embodiments of the invention 4.

Figure 13 A is the plane graph of the NOR type EEPROM of embodiments of the invention 5.

Figure 13 B is the profile along the 13B-13B line among Figure 13 A.

Figure 13 C is the profile along the 13C-13C line among Figure 13 A.

Figure 13 D is the profile along the 13D-13D line among Figure 13 A.

Figure 14 A, Figure 14 B, Figure 14 C, Figure 14 D, Figure 14 E, Figure 14 F, Figure 14 G, Figure 14 H, Figure 14 I, Figure 14 J, Figure 14 K and Figure 14 L are respectively the oblique views in the manufacturing process of NOR type EEPROM of embodiments of the invention 5.

Figure 15 A is the plane graph of the NOR type EEPROM of embodiments of the invention 6.

Figure 15 B is the profile along the 15B-15B line among Figure 15 A.

Figure 15 C is the profile along the 15C-15C line among Figure 15 A.

Figure 15 D is the profile along the 15D-15D line among Figure 15 A.

Figure 16 A and Figure 16 B are respectively the profiles of NOR type EEPROM of a variation of embodiments of the invention 6.

Figure 17 A is the plane graph of the NOR type EEPROM of embodiments of the invention 7.

Figure 17 B is the profile along the 17B-17B line among Figure 17 A.

Figure 17 C is the profile along the 17C-17C line among Figure 17 A.

Figure 17 D is the profile along the 17D-17D line among Figure 17 A.

Figure 18 A and Figure 18 B are respectively the profiles of NOR type EEPROM of a variation of embodiments of the invention 7.

Figure 19 A is the plane graph of the NOR type EEPROM of embodiments of the invention 8.

Figure 19 B is the profile along the 19B-19B line among Figure 19 A.

The oblique view of Figure 20 shows the manufacture method 1 of the NOR type EEPROM of embodiments of the invention 8.

The oblique view of Figure 21 shows the manufacture method 2 of the EEPROM of embodiments of the invention 8.

Figure 22 is the profile that is used for illustrating the purpose of embodiments of the invention 9.

Figure 23 is the profile of the NOR type EEPROM of embodiments of the invention 9.

Figure 24 A, Figure 24 B, Figure 24 C, Figure 24 D, Figure 24 E, Figure 24 F, Figure 24 G, Figure 24 H, Figure 24 I, Figure 24 J, Figure 24 K, Figure 24 L, Figure 24 M, Figure 24 N, Figure 24 O, Figure 24 P, Figure 24 Q and 24R are respectively the oblique views in the manufacturing process of NOR type EEPROM of embodiments of the invention 9.

The oblique view of Figure 25 shows the NOR type EEPROM of a variation of embodiments of the invention 9.

The detailed description of invention

Below, the limit is with reference to accompanying drawing limit explanation embodiments of the invention.In addition, in all figure, all give common for common part with reference to label.

(embodiment 1)

At first, begin to describe from a circuit formation using NOR type EEPROM of the present invention.

Fig. 3 is the circuit diagram of NOR type EEPROM.

As shown in Figure 3, the memory cell array 100 of NOR type EEPROM is configured to a plurality of non-volatile memory cells MC rectangular.A plurality of non-volatile memory cells MC are connected between a bit lines BL and the source electrode line SL.Grid at a plurality of non-volatile memory cells MC that arrange on the line direction is connected respectively on different word line WL1～WL8.Word line WL1～WL8 is connected respectively on the word line driving circuit 102.Word line driving circuit 102 selects to drive any among word line WL1～WL8.Be connected to the non-volatile MC on the word line WL of selected driving, be electrically connected to respectively on bit line BL1～BL8.Bit line BL1～BL8 is connected on the Y selector 103.Y selector 103 has a plurality of transistor YG that are connected respectively on bit line BL1～BL8.The grid of transistor YG is connected respectively on different separately Y selecting line YSL1～YSL4.Selection wire YSL1～YSL4 is connected respectively on the Y selecting line drive circuit 104.Y selecting line drive circuit 104 selects to drive any among Y selecting line YSL1～YSL4.Adopt to select the way of driving transistors YG, in circuit shown in Figure 3, any one among bit line BL1～BL4 is electrically connected to and reads/write on the ingress 105-1, and any one among bit line BL5～BL8 is electrically connected to and reads/write on the ingress 105-2.Reading/write ingress 105-1,105-2 is connected respectively on the reading circuit and write circuit that does not draw.By means of this, just can carry out reading/writing of data to the non-volatile memory cells of being selected drive circuit 104 and word line driving circuit 102 to select by Y.

In the memory cell array 100 of the EEPROM of embodiment 1, source electrode line SL by the direction of being extended along word line WL1～WL8 (below, be called line direction: ROW.D.) the localized source polar curve SL1～SL5 of Yan Shening and the direction of extending along bit line BL1～BL8 (below, be called column direction: COL.D.) the global source polar curve GSL that extends constitutes.Global source polar curve GSL is connected on the source line driving circuit 106.Global source polar curve GSL is connected respectively on localized source polar curve SL1～SL5.The source potential of non-volatile memory cells MC is passed through global source polar curve GSL in the middle of source electrode drive circuit 106, supply with localized source polar curve SL1～SL5.Fig. 4 A shows the plane graph in the frame of broken lines A1 shown in Figure 3.

Fig. 4 A is the plane graph of the NOR type EEPROM memory cell array of embodiments of the invention 1, and Fig. 4 B is the profile along the 4B-4B line among Fig. 4 A.Fig. 4 C is the profile along the 4C-4C line among Fig. 4 A.Fig. 4 D is the profile along the 4D-4D line among Fig. 4 A.

Shown in Fig. 4 A～Fig. 4 D, on p type silicon substrate 1, formed shallow slot 7.This shallow slot 7 is divided the device area 8 that forms striated along column direction on p type silicon substrate 1.In shallow slot 7, imbed the TEOS that is used for making device area 8 electric insulations.This TEOS formation shallow-trench isolation (below, be abbreviated as STI) 9.In the top of device area 8 and the top of STI9, form a plurality of stromatolithic structures 14 respectively along the line direction that intersects with column direction.This stromatolithic structure 14 contains grid oxidation film (SiO respectively ₂) 2, floating grid FG, SiO ₂/ SiN/SiO ₂(below, be abbreviated as ONO) film 11, word line WL, nitride film (SiN) 13.In addition, on the sidewall of this stromatolithic structure 14, also be formed with side wall insulating film (SiN) 15, stromatolithic structure 14 becomes to being covered by the insulant different with the TEOS of STI9.Device area 8 forms stromatolithic structure 14 respectively n type source region S and the n type drain region D of memory cell MC with being clipped in the middle.On the STI9 adjacent, form the recess 22 that this n type source region S is exposed with n type source region S.The bottom surface of recess 22 forms also lowlyer than the surface of device area 8.In recess 22, be formed with the connection conductive layer 19 that n type source region S is electrically connected to each other.Localized source polar curve SL adopts with connecting with conductive layer 19 and along line direction the way that n type source region S couples together is constituted respectively.Along the bit line BL that column direction forms, the centre exists in the perforate part 21D that forms on the interlayer dielectric 20 and is electrically connected on the n type drain region D.In addition, with the global source polar curve GSL that bit line BL similarly forms along column direction, the centre exists at the perforate part 21S that forms on the interlayer dielectric 20 and is connected on the n type source region S.

In addition, become at the n type drain region D of the memory cell MC of the bottom of global source polar curve GSL and be electric suspended state.That is, the memory cell MC of the bottom of global source polar curve GSL does not have the effect of memory cell.

Secondly, the example of manufacture method of the NOR type EEPROM of embodiment 1 is described.

The oblique view of Fig. 5 A～Fig. 5 L shows the NOR type EEPROM of embodiment 1 respectively according to main manufacturing process.Oblique view shown in Fig. 5 A～Fig. 5 L is corresponding with the part in the frame A2 shown in Fig. 4 A respectively.

At first, shown in Fig. 5 A,, form grid oxidation film (SiO successively in p silicon substrate 1 top ₂) 2, will become conductivity polysilicon film 3L, nitride film (SiN) 4 and TEOS film 5 for floating grid.In addition, TEOS film 5 is the silicon dioxide films that form with TEOS gas.In this manual, by convention, the silicon dioxide film that forms with TEOS gas is called the TEOS film.Then, formation forms the corresponding perforate part 6 in zone with STI on TEOS film 5.

Secondly, shown in Fig. 5 B, be mask with TEOS film 5, successively nitride film 54, conductivity polysilicon film 3L, grid oxidation film 2, p type silicon substrate 1 are carried out etching, on p type silicon substrate 1, form shallow slot 7.By means of this, on p type silicon substrate, divide device area 8.

Secondly, shown in Fig. 5 C, in the top of the structure shown in Fig. 5 B, formation will become the insulant of device isolation dielectric film, for example the TEOS film.Then, adopting the RIE method, is the way of barrier etch TEOS film with nitride film 4, is the barrier layer with nitride film 4 perhaps, with the way that the CMP method is ground the TEOS film, imbeds the TEOS film in shallow slot 7.By means of this, form STI9.Then, remove nitride film 4, the surface of conductivity polysilicon film 3L is exposed from conductivity polysilicon film 3L top.

Secondly, shown in Fig. 5 D, in the top of the structure shown in Fig. 5 C, formation will become the conductivity polysilicon film 3U of floating grid.Then, on conductivity polysilicon film 3U, form and to be used for the barrier layer 10 that adjacent floating grid is separated to each other on line direction.By means of this, just can form the conductivity polysilicon film 3 that will become floating grid that the stromatolithic structure by conductivity polysilicon film 3U and conductivity polysilicon film 3L constitutes along column direction.

Secondly, shown in Fig. 5 E,, form successively and be used for making control gate to be capacitively coupled to dielectric film on the floating grid, for example SiO in the top of the structure shown in Fig. 5 D ₂/ SiN/SiO ₂(below, be abbreviated as ONO) film 11, will become the conducting film of control gate, for example conductivity polysilicon film 12 and nitride film (SiN) 13.

Secondly, shown in Fig. 5 F, make nitride film 13, conductivity polysilicon film 12, ONO film 11 and conductivity polysilicon film 3 and grid oxidation film 2 graphical.By means of this, just can form the stromatolithic structure 14 that comprises word line WL (WL3, WL4), floating grid FG along line direction.

Secondly, shown in Fig. 5 G,, form nitride film (SiN), formed nitride film is carried out etching with the RIE method in the top of the structure shown in Fig. 5 F.By means of this, just can form side wall insulating film 15 along the sidewall of stromatolithic structure 14.

Secondly, shown in Fig. 5 H,, form photoresist film 16 in the top of the structure shown in Fig. 5 G.Then, formation forms the corresponding perforate part 17 in zone with source electrode line on photoresist 16.Perforate part 17 forms on line direction along stromatolithic structure 14 when the device area 8, the STI9 that make 14 of nitride films 13, side wall insulating film 15, stromatolithic structure expose.Then, be mask with photoresist film 16, the part of the STI9 that exposes from perforate part 17 is carried out etching, on STI9, form recess 22.Expose from recess 22 on the surface of device area 8.In addition, the bottom surface (being the surface of STI9 in embodiment 1) of recess 22 forms also lowlyer than the surface of device area 8.In the drawings, with the part that 8E represents, the device area 8 that in recess 22, exposes exactly expose face.In addition, this operation is equivalent to the SAS method.

Secondly, shown in Fig. 5 I, after having removed photoresist film 16, the deposit conducting objects makes recess 22 is nuzzled fully, forms conducting film 18-1.In the present embodiment, the thickness t of conducting film 18-1 makes in the top of recess 22 deposit conducting objects and becomes to the thickest.Constituting the example of conducting film 18-1, is to be the refractory metal of representative with titanium (Ti), tungsten (W), or the silicide of refractory metal.

Secondly, shown in Fig. 5 J, conducting film 18-1 is retreated, in recess, imbed conducting objects by means of the etching of using the RIE method to carry out.At this moment, also can utilize the difference of the thickness of conducting film 18-1,, in recess 22, imbed conducting objects by means of maskless lithographic technique.Employing just can middlely exist and expose the connection conductive layer 19 that the formation of face 8E ground is electrically connected device area 8 to each other with the way of conducting objects landfill recess 22.

Secondly, shown in Fig. 5 K, be mask with side wall insulating film 15 and the STI9 that exposes from the teeth outwards, to device area 8 injection n type foreign ions, form n type drain region D and n type source region S respectively.In addition, the n type source region S adjacent with line direction connects with conductive layer 19 with connecting to each other.By means of this, just can form source electrode line SL (SL2, SL3) along line direction.In addition, the degree of depth of n type source region S forms also deeplyer than exposing face 8E.Because prevent to connect short circuit with between conductive layer 19 and the p type silicon substrate 1.

Secondly, shown in Fig. 5 L,, form interlayer dielectric 20 in the top of the structure shown in Fig. 5 K.Then, on interlayer dielectric 20, form bit line perforate part 21D that leads to drain region D and the source electrode line perforate part 21S that leads to source region S.Then, respectively along column direction, form the bit line BL (BL4, BL5) be electrically connected on the drain region D and be electrically connected to global source polar curve GSL on the source region S by source electrode line perforate part 21S by bit line perforate part 21D.By means of this, finish the NOR type EEPROM of embodiments of the invention 1.

If the embodiment 1 of Xing Chenging in this wise, then shown in Fig. 4 A～4D, in the recess 22 that forms to a part of having removed STI9, imbed and connect with conductive layer 19.Connect with conductive layer 19, the centre exists the n type source region S that exposes in the face of forming and is electrically connected to each other on device area 8.Owing to have such connection with conductive layer 19, so can suppress to isolate the broken string of using groove 7 caused localized source polar curve SL.Therefore, even if use the SAS method, also can positively form localized source polar curve SL for the memory cell array of carrying out device isolation with STI9.

And connecting with conductive layer 19 is the structures that are embedded in the recess.If adopt this structure,, then have to form the advantage that connects with conductive layer 19 with maskless process if make and become in recess 22 tops to the thickest deposit like that is used for forming the conducting film 18-1 that connects with conductive layer 19.

(embodiment 2)

The order of the manufacturing process of embodiment 1 is: the formation of recess 22, the formation of the interior etching of the deposit of conducting objects, conducting objects, n type drain region D and n type source region S.But this manufacturing process also can change to following order: n type drain region D and the formation of n type source region S, the formation of recess 22, the interior etching of the deposit of conducting objects, conducting objects.

Embodiment 2 changes the example of manufacturing process with coming to this.

The oblique view of Fig. 6 A～Fig. 6 F shows the NOR type EEPROM of embodiment 2 respectively according to main manufacturing process's order.Oblique view shown in Fig. 6 A～Fig. 6 F is corresponding with the part in the frame A2 shown in Fig. 4 A respectively.

At first, the manufacture method of abideing by with Fig. 5 A～Fig. 5 G explanation obtains the structure shown in Fig. 6 A.

Secondly, shown in Fig. 6 B, be mask with stromatolithic structure 14, side wall insulating film 15 and the STI9 that exposes from the teeth outwards, inject n type impurity to device area 8, form n type drain region D and n type source region S respectively.

Secondly, shown in Fig. 6 C,, form photoresist film 16 in the top of the structure shown in Fig. 6 B.Then, on photoresist film 16, form and the corresponding perforate part 17 in source electrode line zone.Perforate part 17, limit are exposed device area 8, the STI9 of 14 of nitride films 13, side wall insulating film 15, stromatolithic structure, and the edge stromatolithic structure 14 and forms on line direction.Then, be mask with photoresist film 16, the part of the STI9 that etching is exposed from perforate part 17 forms recess 22 on STI9.Expose from recess 22 on the surface of device area 8.In addition, the bottom surface (being the surface of STI9 in embodiment 2) of recess 2 forms also lowlyer than the surface of device area 8.Among the figure, with reference to the part shown in the label 8E face that exposes of the device area that in recess 22, exposes.

Secondly, shown in Fig. 6 D, after having removed photoresist film 16, the deposit conducting objects makes recess 22 is fully nuzzled, and forms conducting film 18-1.In present embodiment 2, the thickness t of conducting film 18-1 makes in the top of recess 22 deposit conducting objects and becomes to the thickest.Constituting the example of conducting film 18-1, is to be the refractory metal of representative with titanium (Ti), tungsten (W), or the silicide of refractory metal.

Secondly, shown in Fig. 6 E, conducting film 18-1 is retreated, in recess, imbed conducting objects by means of the etching of using the RIE method to carry out.At this moment, also can utilize the difference of the thickness of conducting film 18-1,, in recess, imbed conducting objects by means of maskless lithographic technique.Adopt way with conducting objects landfill recess 22, just can in the middle of exist and expose face 8E and form the device area 8 connection to each other conductive layer 19 that is electrically connected.

Secondly, shown in Fig. 6 F,, form interlayer dielectric 20 in the top of the structure shown in Fig. 6 E.Then, on interlayer dielectric 20, form bit line perforate part 21D that leads to drain region D and the source electrode line perforate part 21S that leads to source region S.Then, respectively along column direction, form the bit line BL (BL4, BL5) be electrically connected on the drain region D and be electrically connected to global source polar curve GSL on the source region S by source electrode line perforate part 21S by bit line perforate part 21D.

The NOR type EEPROM of embodiment 1 also can form with the manufacturing process of such embodiment 2.

(embodiment 3)

Fig. 7 A is the plane graph of the NOR type EEPROM of embodiments of the invention 3.Fig. 7 B is the profile along the 7B-7B line among Fig. 7 A.Fig. 7 C is the profile along the 7C-7C line among Fig. 7 A.Fig. 7 D is the profile along the 7D-7D line among Fig. 7 A.

Shown in Fig. 7 A～7D, embodiment 3 with the difference of embodiment 1 is: form the silicon fiml 18-2 of p type or non-doping in recess 22, form to connect on this silicon fiml 18-2 and use n type silicon area 29.Connect with n type silicon area 29, n type source region S is electrically connected to each other mutually.

Below, according to an example of this manufacture method, the NOR type EEPROM of embodiment 3 is described in more detail.

The oblique view of Fig. 8 A～Fig. 8 F shows the NOR type EEPROM of embodiment 3 respectively according to main manufacturing process order.Oblique view shown in Fig. 8 A～Fig. 8 F is corresponding with the part in the frame A2 shown in Fig. 7 A respectively.

At first, abide by manufacture method, obtain the structure shown in Fig. 8 A with Fig. 5 A～Fig. 5 G explanation.

Secondly, shown in Fig. 8 B,, form photoresist film 16 in the top of the structure shown in Fig. 8 A.Then, formation forms the corresponding perforate part 17 in zone with source electrode line on photoresist 16.Perforate part 17 forms on line direction along stromatolithic structure 14 when the device area 8, the STI9 that make 14 of nitride films 13, side wall insulating film 15, stromatolithic structure expose.Then, be mask with photoresist film 16, to whole etchings of carrying out of the STI9 that exposes from perforate part 17, on STI9, form recess 22.Expose from recess 22 on the surface of device area 8.In addition, the bottom surface of recess 22 (being the surface of the p type silicon substrate 1 that exposes on the end of groove 7 in embodiment 3) forms also lowlyer than the surface of device area 8.In the drawings, the part of being represented by reference label 8E is exactly the face that exposes of the device area 8 that exposes in shallow slot 7.In addition, this operation is equivalent to SAS.

Secondly, shown in Fig. 8 C, after having removed photoresist film 16, deposit silicon forms silicon fiml 18-2.Silicon fiml 18-2 is the silicon of p type or the silicon of non-doping.In addition, no matter silicon is that monocrystalline, polycrystalline are all right.

Secondly, shown in Fig. 8 D, adopt way, silicon fiml 18-2 is retreated, in shallow slot 7, imbed silicon with RIE method etching.By means of this, use the silicon fiml 18-2 identical that device area 8 is coupled together to each other with p type silicon substrate 1.

Secondly, shown in Fig. 8 E, with stromatolithic structure 14, side wall insulating film 15 and the STI9 that exposes from the teeth outwards is mask, injects n type impurity to device area 8 and silicon fiml 18-2, ion, forms n type drain region D, n type source region S respectively and is connected usefulness n type silicon area 29.At this moment, the n type source region S adjacent with line direction is used in silicon fiml 18-2 to each other and goes up and connect being connected with type silicon area 29 of forming.By means of this, just can form source electrode line SL (SL2, SL3) along line direction.

Secondly, shown in Fig. 8 F,, form interlayer dielectric 20 in the top of the structure shown in Fig. 8 E.Then, on interlayer dielectric 20, form bit line perforate part 21D that leads to drain region D and the source electrode line perforate part 21S that leads to source region S.Then, respectively along column direction, form the bit line BL (BL4, BL5) be electrically connected on the drain region D and be electrically connected to global source polar curve GSL on the source region S by source electrode line perforate part 21S by bit line perforate part 21D.By means of this, finish the NOR type EEPROM of embodiments of the invention 3.

If the embodiment 3 of Xing Chenging in this wise then shown in Fig. 7 A～7D, in the recess 22 of 8 of device areas, imbeds silicon fiml 18-2, on this silicon fiml 18-2, form and connect with n type silicon area 29.Connect with silicon area 29, middle existence is exposed face 8E the n type source region S that forms on device area 8 is electrically connected to each other.Since have such connection n type silicon area 29, the same with embodiment 1, can suppress to isolate broken string with groove 7 caused localized source polar curve SL.Therefore, even if use the SAS method, also can more positively form localized source polar curve SL for the memory cell array of carrying out device isolation with STI9.

Secondly, the variation of the NOR type EEPROM of embodiment 3 is described.

Fig. 9 A and Fig. 9 B are respectively the profiles of NOR type EEPROM of a variation of embodiments of the invention 3.In addition, the profile shown in Fig. 9 A is equivalent to along the profile of the 7B-7B line among Fig. 7 A, and the profile shown in Fig. 9 B is equivalent to along the profile of the 7D-7D line among Fig. 7 A.

In the foregoing description 3, though removed source electrode line form region memory shallow slot 7 in STI9 whole,, shown in Fig. 9 A, 9B, also can make to become a part with the embodiment 1 the same STI9 of removing.So, even if adopt and imbed silicon fiml 18-2 to the part of a part of having removed STI9, on the silicon fiml 18-2 that imbeds, form to connect way,, also can suppress the broken string of the localized source polar curve SL that causes by the groove 7 of isolating usefulness with above-mentioned same with n type silicon area 29.

In addition, in embodiment 1, in order to prevent to connect short circuit with between conductive layer 19 and the p type substrate 1, must form the degree of depth of removing STI9 also more shallowly than n type source region S, but in a variation of present embodiment 3, then can form the degree of depth of removing STI9 also deeplyer than the degree of depth of n type source region S.Therefore, with embodiment 1 ratio, need not monitor removing of STI9 accurately, this raising for the rate of manufacturing a finished product is favourable.

(embodiment 4)

Figure 10 A is the plane graph of the NOR type EEPROM of embodiments of the invention 4.Figure 10 B is the profile along the 10B-10B line among Figure 10 A.Figure 10 C is the profile along the 10C-10C line among Figure 10 A.Figure 10 D is the profile along the 10D-10D line among Figure 10 A.

Shown in Figure 10 A～Figure 10 D, to be connections of making in embodiment 3 explanation carry out the embodiment of suicided with the surface of the surface of n type silicon area 29 and n type source region S or n type drain region D to embodiment 4 simultaneously.With reference to the part shown in the label 39, be the silicide layer of refractory metal among the figure.

Below, according to an example of this manufacture method, the NOR type EEPROM of embodiment 4 is described in more detail.

The oblique view of Figure 11 A～Figure 11 D, according to main manufacturing process respectively order show the NOR type EEPROM of embodiment 4.Oblique view shown in Figure 11 A～Figure 11 D is corresponding with the part in the frame A2 shown in Figure 10 A respectively.

At first, abide by manufacture method, the structure shown in Fig. 8 E that obtains in embodiment 3, illustrating with Fig. 5 A～Fig. 5 G, Fig. 8 A～Fig. 8 E explanation.

Secondly, shown in Figure 11 A, in the top of the structure shown in Fig. 8 E, the deposit refractory metal forms high melting point metal film 18-3.The example of refractory metal is titanium (Ti), cobalt (Co) etc.

Secondly, shown in Figure 11 B, the structure shown in Figure 11 A is heat-treated, make high melting point metal film 18-3 respectively with n type drain region D, n type source region S, is connected with 19 reactions of n type silicon area, formation silicide layer 39.At this moment suicided only produces in the face top of exposing of silicon, does not then produce in the STI9 top or by stromatolithic structure 14 tops of

nitride film

13,15 coverings.Resemble only make silicon in this wise expose the optionally operation of suicided of face, also can the polysilicon gate top be exposed, carry out suicided again.

Secondly, shown in Figure 11 C, within refractory metal, remove unreacted portion.

Secondly, shown in Figure 11 D,, form interlayer dielectric 20 in the top of the structure shown in Figure 11 C.Then, on interlayer dielectric 20, form the bit line perforate part 21D and the source electrode line perforate part 21S that leads to the silicide layer 39 of source region S top of the silicide layer 39 that leads to drain region D top.Then, respectively along column direction, form the bit line BL (BL4, BL5) that is electrically connected on the drain region D and be electrically connected to global source polar curve GSL on the source region S by source electrode line perforate part 21S and silicide layer 39 by bit line perforate part 21D and silicide layer 39.By means of this, finish the NOR type EEPROM of embodiments of the invention 4.

If the embodiment 4 of Xing Chenging in this wise is then shown in Figure 10 A～Figure 10 D, the same with embodiment 3, in the shallow slot 7 of 8 of device areas, imbed silicon fiml 18-2, on this silicon fiml 18-2, form and connect with n type silicon area 29.Connect with n type silicon area 29, the centre is electrically connected the n type source region S that forms by exposing face 8E to each other on device area 8.In addition, form silicide layer 39 from n type source region S top to connecting with n type silicon area 29 tops.The resistance ratio n type source region S of silicide layer 39 or connection are also low with the resistance of n type silicon area 29.

As mentioned above, adopt not only to have and connect with n type silicon area 29, also have from n type source region S top to the way that connects the silicide layer 39 that forms with n type silicide layer 29 tops, just can in the broken string of the localized source polar curve SL that suppresses to produce, can also reduce the resistance value of localized source polar curve SL because of the groove 7 of isolating usefulness.Therefore,,, also can undertaken by STI9 on the memory cell array of device isolation, more positively form localized source polar curve SL, but also can form low-resistance localized source polar curve SL even if then use the SAS method if adopt embodiment 4.

Secondly, the variation of the NOR type EEPROM of embodiment 4 is described.

Figure 12 A and Figure 12 B are respectively the profiles of NOR type EEPROM of the variation of embodiment 4.In addition, the profile shown in Figure 12 A is equivalent to along the profile of the 10B-10B line among Figure 10 A, and the profile shown in Figure 12 B is equivalent to along the profile of the 10D-10D line among Figure 10 A

Shown in Figure 12 A and Figure 12 B, in embodiment 4, also can be deformed into a part of removing STI9 with embodiment 3 the samely.Imbed silicon fiml 18-2 to the part of a part of having removed STI9, on the silicon fiml 18-2 that is imbedded, form to connect and use n type silicon area 29, in addition, form silicide layer 39 from n type source region S top to connecting with n type silicide layer 29 tops.By means of this, can be with above-mentioned the same, suppress the broken string of the localized source polar curve SL that produced because of the groove 7 of isolating usefulness, can also realize the low resistanceization of localized source polar curve SL simultaneously.

(embodiment 5)

Though embodiment 1～embodiment 4 is to the example under the situation of memory cell array use SAS method,, the present invention also can use for the memory cell array of not using the SAS method.Embodiment 5 is exactly the example that does not use under the situation of memory cell array of SAS method.

Figure 13 A is the plane graph of the NOR type EEPROM of embodiments of the invention 5.Figure 13 B is the profile along the 13B-13B line among Figure 13 A.Figure 13 C is the profile along the 13C-13C line among Figure 13 A.Figure 13 D is the profile along the 13D-13D line among Figure 13 A.

Below, an example of abideing by its manufacture method illustrates the NOR type EEPROM of embodiment 5.

Figure 14 A～Figure 14 L is respectively the oblique view that shows the NOR type EEPROM of embodiment 5 according to main manufacturing process in proper order.Oblique view shown in Figure 14 A～Figure 14 L is corresponding with the part in the frame A2 shown in Figure 13 A respectively.

At first, the manufacture method of abideing by with Fig. 5 A～Fig. 5 C explanation obtains the structure shown in Figure 14 A.

Secondly, as shown in Figure 14B,, form photoresist film 46 in the top of the structure shown in Figure 14 A.Then, on photoresist film 46, form with source electrode line and form the corresponding perforate part 47 in zone.Perforate part 47, limit are exposed conductivity polysilicon film 3L, STI9, and the edge stromatolithic structure 14 and forms on line direction.

Secondly, shown in Figure 14 C, be mask with photoresist film 46, the whole etchings of carrying out to the STI9 that exposes from perforate part 47 form recess 22 on STI9.Expose from recess 22 on the surface of device area 8.In addition, the bottom surface of recess 22 (being the surface of the p type silicon substrate 1 that exposes on the end of groove 7 in embodiment 5) forms also lowlyer than the surface of device area 8.In the drawings, by the part that reference label 8E represents, the device area 8 that in shallow slot 7, exposes exactly expose face.

Secondly, shown in Figure 14 D, remove photoresist film 46.

Secondly, shown in Figure 14 E, make in the top deposit silicon of the structure shown in Figure 14 D and recess 22 fully to be nuzzled formation silicon fiml 18-2.In present embodiment 5, the thickness t of conducting film 18-2 makes in the top of recess 22 deposit silicon and becomes to the thickest.Silicon fiml 18-2 is a p type silicon, or the silicon of non-doping.In addition, no matter silicon is that monocrystalline or polycrystalline are all right.

Secondly, shown in Figure 14 F, with the etching of utilizing maskless RIE method to carry out silicon fiml 18-2 is retreated, and utilize the difference of the thickness of silicon fiml 18-2 in recess, to imbed silicon.In addition, in embodiment 5, also can adopt the way that silicon fiml 18-2 is retreated with the CMP method in recess 22, to imbed silicon.

Secondly, shown in Figure 14 G, in the top of the structure shown in Figure 14 F, formation will become the conductivity polysilicon film 3U of floating grid.Then, on conductivity polysilicon film 3U, form and be used for the slit 10 that adjacent floating grid is separated to each other on line direction.By means of this, just can form the conductivity polysilicon film 3 that will become floating grid that the stromatolithic structure by conductivity polysilicon film 3U and conductivity polysilicon film 3L constitutes along column direction.

Secondly, shown in Figure 14 H,, form successively and be used for making control gate to be capacitively coupled to dielectric film on the floating grid in the top of the structure shown in Figure 14 G, for example ONO film 11, will become the conducting film of control gate, conductivity polysilicon film 12 and nitride film (SiN) 13 for example.

Secondly, shown in Figure 14 I, make nitride film 13, conductivity polysilicon film 12, ONO film 11 and conductivity polysilicon film 3 and grid oxidation film 2 graphical.By means of this, just can form the stromatolithic structure 14 that comprises word line WL (WL3, WL4), floating grid FG along line direction.

Secondly, shown in Figure 14 J,, form nitride film (SiN), formed nitride film is carried out etching with the RIE method in the top of the structure shown in Figure 14 I.By means of this, just can form side wall insulating film 15 along the sidewall of stromatolithic structure 14.

In addition, in embodiment 1～4, owing to be mask formation recess 22, so become in fact to consistent with the end of side wall insulating film 15 along the end of the recess 22 of side wall insulating film 15 with side wall insulating film 15.

To this, in embodiment 5, shown in broken circle A3, can make the bottom that is present in side wall insulating film 15 along the end of the recess 22 of side wall insulating film 15.If adopt this formation, then can make the width along column direction of recess 22 form also widelyer than the interval of 15 of side wall insulating films.For this reason, with embodiment 1～embodiment 4 ratios, have and to make the connection that on silicon fiml 18-2, forms form greatly, the advantage that its resistance value is descended with the sectional area of n type silicon area 29.

Secondly, shown in Figure 14 K, be mask with stromatolithic structure 14, side wall insulating film 15 and the STI9 that exposes from the teeth outwards, ion injects n type impurity to device area 8 in, forms n type drain region D, n type source region S respectively and is connected usefulness n type silicon area 29.At this moment, the n type source region S adjacent with line direction is used in the last connection that forms of silicon fiml 18-2 and connects with n type silicon area 29 to each other.By means of this, just can form source electrode line SL (SL2, SL3) along line direction.

Secondly, shown in Figure 14 L,, form interlayer dielectric 20 in the top of the structure shown in Figure 14 K.Then, on interlayer dielectric 20, form bit line perforate part 21D that leads to drain region D and the source electrode line perforate part 21S that leads to source region S.Then, respectively along column direction, form the bit line BL (BL4, BL5) be electrically connected on the drain region D and be electrically connected to global source polar curve GSL on the source region S by source electrode line perforate part 21S by bit line perforate part 21D.By means of this, finish the NOR type EEPROM of embodiments of the invention 5.

If the embodiment 5 of Xing Chenging in this wise then shown in Figure 13 A～13D, in the recesses 22 that whole backs of having removed STI9 form, imbeds silicon fiml 18-2.Since on this silicon fiml 18-2, formed to connect and used n type silicon area 29, the same with embodiment 1～4, can suppress to isolate broken string with groove 7 caused localized source polar curve SL.Therefore, can carry out with STI9 on the memory cell array of device isolation, more positively form localized source polar curve SL.

In addition, in embodiment 5, shown in the broken circle A3 shown in Figure 13 D, also can make the bottom that is present in side wall insulating film 15 along the end of the recess 22 of side wall insulating film 15.If adopt this formation, the width along column direction that then can recess 22 forms also widelyer than the interval of 15 of side wall insulating films, increases the sectional area that connects with n type silicon area 29.Therefore, the advantage that has the resistance value decline that makes source electrode line SL.

(embodiment 6)

Embodiment 6 is that a NOR type EEPROM with embodiment 1 explanation makes to become the example without the memory cell array of SAS method as embodiment 5.

Figure 15 A is the plane graph of the NOR type EEPROM of embodiments of the invention 6.Figure 15 B is the profile along the 15B-15B line among Figure 15 A.Figure 15 C is the profile along the 15C-15C line among Figure 15 A.Figure 15 D is the profile along the 15D-15D line among Figure 15 A.

Shown in Figure 15 A～Figure 15 D, if adopt embodiment 6, then the same with embodiment 5, can make the end along line direction of recess 22 be positioned at the bottom (especially with reference to Figure 15 D broken circle A3) of side wall insulating film 15, can increase the sectional area that connects with conductive layer 19.Therefore, can reduce the resistance value of source electrode line SL.

In addition, in the etching when etching when stromatolithic structure 14 forms and the formation of side wall insulating film 15, employing is constitute connecting the way that is chosen as the material that is difficult to be etched with the conducting objects of conductive layer 19, just can form connection also highlyer than the surface of device area 8 with the bottom surface of conductive layer 19.If adopt this structure and since can make connect with conductive layer 19 with contact to whole that exposes face 8E, can make the advantage of using the contact resistance decline between the conductive layer 19 in the n type source region S and the connection of formation on the device area 8 in the back so have.

Secondly, the variation of the NOR type EEPROM of embodiment 6 is described.

Figure 16 A and Figure 16 B are respectively the profiles of NOR type EEPROM of a variation of embodiments of the invention 6.In addition, the profile shown in Figure 16 A is equivalent to along the profile of the line 15B-15B among Figure 15 A, and the profile shown in Figure 16 B is equivalent to along the profile of the line 15D-15D among Figure 15 A.

Shown in Figure 16 and Figure 16 B, also can form silicon fiml 18-2, and formation connection here replaces connection conductive layer 19 with n type silicon area 29.

(embodiment 7)

Embodiment 7 is that a NOR type EEPROM with embodiment 1 explanation makes to become the example without the memory cell array of SAS method as embodiment 5.

Figure 17 A is the plane graph of the NOR type EEPROM of embodiments of the invention 7.Figure 17 B is the profile along the 17B-17B line among Figure 17 A.Figure 17 C is the profile along the 17C-17C line among Figure 17 A.Figure 17 D is the profile along the 17D-17D line among Figure 17 A.

Shown in Figure 17 A～Figure 17 D, if adopt embodiment 7, then the same with embodiment 5, can make the end along line direction of recess 22 be positioned at the bottom (especially with reference to Figure 17 D broken circle A3) of side wall insulating film 15, can increase the sectional area of silicide layer 39 respectively.Therefore, can reduce the resistance value of silicide layer 39.

Secondly, the variation of the NOR type EEPROM of embodiment 7 is described.

Figure 18 A and Figure 18 B are respectively the profiles of NOR type EEPROM of a variation of embodiments of the invention 6.In addition, the profile shown in Figure 18 A is equivalent to along the profile of the line 17B-17B among Figure 17 A, and the profile shown in Figure 18 B is equivalent to along the profile of the line 17D-17D among Figure 17 A.

Shown in Figure 18 A, 18B, the recess 22 of embodiment 7 even if all do not remove STI 9, as illustrating in the variation of embodiment 4, also can adopt the way of a part of removing STI9 to form.

(embodiment 8)

Though shown in the foregoing description 1～7 be the example that connects localized source polar curve SL along line direction, localized source polar curve SL also can be cut apart in the way of memory cell array.

Embodiment 8 is at the example of cutting apart localized source polar curve SL along the line direction of memory cell array on the way.

Figure 19 A is the plane graph of the NOR type EEPROM of embodiments of the invention 8.Figure 19 B is the profile along the 19B-19B line among Figure 19 A.

Particularly shown in Figure 19 B, localized source polar curve SL3 is divided into localized source polar curve SL3-1 and local source electrode line SL3-2 by STI9.

If such embodiment 8, then localized source polar curve SL3-1 and local source electrode line SL3-2 are insulated by STI9.From this structure, can obtain following advantage:, then can drive localized source polar curve SL3-1 and local source electrode line SL3-2 independently of each other if global source polar curve that is connected on the localized source polar curve SL3-1 and the global source polar curve that is connected on the localized source polar curve SL3-2 are separated.

Secondly, the example 1 of manufacture method of the NOR type EEPROM of embodiment 8 is described.

The oblique view of Figure 20 shows the 1st manufacture method of manufacture method of the NOR type EEPROM of embodiment 8.Manufacturing process shown in Figure 20 is corresponding to the operation shown in particularly Fig. 5 H of embodiment 1.

As shown in figure 20,,, obtain 2 perforate part 17-1,17-2, then can obtain the structure shown in Figure 19 A and Figure 19 B along line direction with this part that covers if film 16 covers the top of STI9 with photoresist.

Secondly, the example 2 of manufacture method of the NOR type EEPROM of embodiment 8 is described.

The oblique view of Figure 21 shows the 2nd manufacture method of the NOR type EEPROM of embodiment 8.Operation shown in Figure 21 is corresponding to the operation shown in particularly Figure 14 B～Figure 14 C of embodiment 5.

As shown in figure 21, the same if film 16 covers the top of STI9 with photoresist with the 1st manufacture method, with this part that covers, obtain 2 perforate part 47-1,47-2 along line direction, then can obtain the structure shown in Figure 19 A and Figure 19 B.

In addition, embodiment 8, though resemble the embodiment 1 being the device that n type source region S couples together to each other the explanation that example is carried out with connecting with conductive layer 19, self-evident embodiment 8 also can be applied to respectively with connection with n type silicon layer 29 n type source region S embodiment 3 that couples together to each other and the embodiment 4 that has silicide layer 39 on the surface that is connected with n type silicon layer 29.

(embodiment 9)

As shown in figure 22, in embodiment 1, use and carry out the ohmic contact conducting objects with p type silicon substrate 1 and constitute and to be connected, and under the also dark situation of the depth ratio n of recess 22 type source region S, connect with

conductive layer

19 and 1 short circuit of p type silicon substrate with conductive layer 19.

Present embodiment 9 provides the conductor integrated circuit device with such structure: carry out the ohmic contact conducting objects with p type silicon substrate 1 and constitute and to be connected usefulness conductive layer 19 even if use, and under the also dark situation of the depth ratio n of recess 22 type source region S, also can prevent to connect with

conductive layer

19 and 1 short circuit of p type silicon substrate.

Figure 23 is the profile of the NOR type EEPROM of embodiments of the invention 9.Profile shown in Figure 23 is equivalent to along the profile of the 4B-4B line shown in Fig. 4 A.

As shown in figure 23, embodiment 9 has formed the embodiment that regulation is exposed the nitride film 81 of face 8E on the sidewall of shallow slot 7.

Below, in accordance with an example of its manufacture method, the NOR type EEPROM of embodiment 9 is described in more detail.

Figure 24 A～Figure 24 R is respectively the oblique view that shows the NOR type EEPROM of embodiment 9 according to main manufacturing process in proper order.Oblique view shown in Figure 24 A～Figure 24 R is corresponding with the part in the frame A2 shown in Fig. 4 A respectively.

At first, shown in Figure 24 A,, form grid oxidation film (SiO successively in p type silicon substrate 1 top ₂) 2, will become conductivity polysilicon film 3L, nitride film (SiN) 4 and the TEOS film 5 of floating grid.Then, formation forms the corresponding perforate part 6 in zone with STI on TEOS film 5.

Secondly, shown in Figure 24 B, be mask with TEOS film 5, etching nitride film 4, conductivity polysilicon film 3L, grid oxidation film 2 and p type silicon substrate 1 on p type silicon substrate 1, form shallow slot 7 successively.By means of this, on p type silicon substrate 1, divide device area 8.

Secondly, shown in Figure 24 C,, form nitride film (SiN) 81 in the top of the structure shown in Figure 24 B.

Secondly, shown in Figure 24 D,, form photoresist film 82 in the top of the structure shown in Figure 24 C.

Secondly, shown in Figure 24 E, make photoresist film 81 exposures, make its surface portion sensitization.At this moment, the not sensitization of part in the shallow slot 7 of photoresist film 82.

Secondly, shown in Figure 24 F, remove the sensitization part of photoresist film 82, in shallow slot 7, remaining photoresist film 82.

Secondly, shown in Figure 24 G, be the barrier layer with TEOS film 5, photoresist film 82, with RIE method etching nitride film 81, up to obtain device area 8 expose face 8E till.

Secondly, shown in Figure 24 H, remove photoresist film 82.By means of this, the sidewall of shallow slot 7 is removed and is exposed outside the face 8E, is covered by nitride film 81.

Secondly, shown in Figure 24 I, in the top of the structure shown in Figure 24 H, deposit will become the insulant of device isolation dielectric film, for example the TEOS film.Then, using the RIE method, is the way of barrier etch TEOS film with nitride film 4, is the barrier layer with nitride film 4 perhaps, and the way with the CMP method is ground the TEOS film retreats TEOS film 5, imbeds the TEOS film in shallow slot 7.By means of this, form STI9.Then, remove nitride film 4, the surface of conductivity polysilicon film 3L is exposed from conductivity polysilicon film 3L top.

Secondly, shown in Figure 24 J, in the top of the structure shown in Figure 24 I, formation will become the conductivity polysilicon film 3U of floating grid.Then, on conductivity polysilicon film 3U, form and be used for the barrier layer 10 that adjacent floating grid is separated to each other on line direction.By means of this, just can form the conductivity polysilicon film 3 that will become floating grid that the stromatolithic structure by conductivity polysilicon film 3U and conductivity polysilicon film 3L constitutes along column direction.

Secondly, shown in Figure 24 K,, form successively and be used for making control gate to be capacitively coupled to dielectric film on the floating grid in the top of the structure shown in Figure 24 J, for example ONO film 11, will become the conducting film of control gate, conductivity polysilicon film 12 and nitride film (SiN) 13 for example.

Secondly, shown in Figure 24 L, make nitride film 13, conductivity polysilicon film 12, ONO film 11 and conductivity polysilicon film 3 and grid oxidation film 2 graphical.By means of this, just can form the stromatolithic structure 14 that comprises word line WL (WL3, WL4), floating grid FG along line direction.

Secondly, shown in Figure 24 M,, form nitride film (SiN), formed nitride film is carried out etching with the RIE method in the top of the structure shown in Figure 24 L.By means of this, along the sidewall formation side wall insulating film 15 of stromatolithic structure 14.

Secondly, shown in Figure 24 N,, form photoresist film 16 in the top of the structure shown in Figure 24 M.Then, formation forms the corresponding perforate part 17 in zone with source electrode line on photoresist film 16.Perforate part 17 forms on line direction along stromatolithic structure 14 when the device area 8, the STI9 that make 14 of nitride films 13, side wall insulating film 15, stromatolithic structure expose.Then, be mask with photoresist film 16, to whole etchings of carrying out of the STI9 that exposes from perforate part 17, on STI9, form recess 22.Expose from recess 22 on the surface of device area 8.In addition, the bottom surface (being the surface of nitride film 81 in embodiment 9) of recess 22 forms also lowlyer than the surface of device area 8.In addition, this operation is equivalent to the SAS method.

Secondly, shown in Figure 24 O, after having removed photoresist film 16, the deposit conducting objects makes recess 22 is nuzzled fully, forms conducting film 18-1.In present embodiment 9, the thickness t of conducting film 18-1 makes in the top of recess 22 deposit conducting objects and becomes to the thickest.Constituting the example of conducting film 18-1, is to be the refractory metal of representative with titanium (Ti), tungsten (W), or the silicide of refractory metal.

Secondly, shown in Figure 24 P, conducting film 18-1 is retreated, utilize the difference of the thickness of conducting film 18-1, in recess 22, imbed conducting objects with the etching of using the RIE method to carry out.By means of this, the middle existence exposed the connection conductive layer 19 that face 8E formation is electrically connected device area 8 to each other.

Secondly, shown in Figure 24 Q, be mask with side wall insulating film 15 and the STI9 that exposes from the teeth outwards, to device area 8 injection n type foreign ions, form n type drain region D and n type source region S respectively.In addition, the n type source region S adjacent with line direction connects with conductive layer 19 with connecting to each other.By means of this, just can form source electrode line SL (SL2, SL3) along line direction.In addition, the degree of depth of n type source region S forms also deeplyer than exposing face 8E.Because prevent to connect short circuit with between conductive layer 19 and the p type silicon substrate 1.

Secondly, shown in Figure 24 R,, form interlayer dielectric 20 in the top of the structure shown in Figure 24 Q.Then, on interlayer dielectric 20, form bit line perforate part 21D that leads to drain region D and the source electrode line perforate part 21S that leads to source region S.Then, respectively along column direction, form the bit line BL (BL4, BL5) be electrically connected on the drain region D and be electrically connected to global source polar curve GSL on the source region S by source electrode line perforate part 21S by bit line perforate part 21D.By means of this, finish the NOR type EEPROM of embodiments of the invention 9.

If the embodiment 9 of Xing Chenging in this wise then can connect with conductive layer 19 and the part that device area 8 contacts making, be defined as obtain by means of removing nitride film 81 expose face 8E.Therefore, the degree of depth of recess 22, even if dark unlike n type source region S, connecting can short circuit with conductive layer 19 and substrate 1 yet.Therefore, with embodiment 1 ratio, need not monitor accurately the amount of removing of STI9, be favourable for the raising of the rate of manufacturing a finished product.

Secondly, the variation of the NOR type EEPROM of embodiment 9 is described.

Figure 25 is the profile of NOR type EEPROM of a variation of embodiments of the invention 9.Profile shown in Figure 25 is equivalent to along the profile of the 4B-4B line shown in Fig. 4 A.

In the foregoing description 9, though removed source electrode line form region memory shallow slot 7 in whole STI9, as shown in figure 25, also can make to become a part of removing STI9.

In addition, in this case,, when etching nitride film 81, also can omit the photoresist film of the nitride film 81 that forms the bottom surface that is used for covering shallow slot 7, in shallow slot 7, be left the operation of photoresist film as long as only on the sidewall of shallow slot 7, form nitride film 81.

In addition, embodiment 9, also can cut apart localized source polar curve SL on the way along the line direction of memory cell array as embodiment 8.

More than, though with embodiment 1～9 the present invention has been described, the present invention is not limited to these embodiment.In the scope that does not depart from its aim, can carry out all distortion.

For example, in the above-described embodiments, though explanation is that the present invention is applied to the example that goes in the source electrode line of NOR type EEPROM,, also can be applied to the present invention in the source electrode line of NAND type EEPROM and go.

The wiring layer that forms in addition, is not limited to source electrode line, so long as can be used the present invention on the part of having removed STI9.

In addition, in the above-described embodiments, illustratively be: as transistor, between word line WL and device area 8, have to be used for the floating grid FG of stored charge, make the MOSFET of the threshold value changeable type of threshold voltage variation with charge stored amount here.But transistor also can change to the common MOSFET with floating grid.

As mentioned above, if adopt the present invention, then can provide the conductor integrated circuit device with this following structure: even if form wiring layer on the part of having removed the groove isolation, this wiring layer also is difficult to broken string.

Claims

1, a kind of conductor integrated circuit device is characterized in that possessing:

At least one side that the recess that forms on above-mentioned the 1st insulant, this recess make above-mentioned the 1st, the 2nd semiconductor regions exposes from a sidewall of above-mentioned groove, at least one side who makes above-mentioned the 3rd, the 4th semiconductor regions from another sidewall of above-mentioned groove expose and

The conductive region that forms in above-mentioned recess, this conductive region are electrically connected at least one side of above-mentioned the 3rd, the 4th semiconductor regions at least one side of above-mentioned the 1st, the 2nd semiconductor regions.

2, the described conductor integrated circuit device of claim 1 is characterized in that: the 2nd insulant that above-mentioned gate electrode is had the etch rate different with the etch rate of above-mentioned the 1st insulant covers.

3, the described conductor integrated circuit device of claim 2 is characterized in that: above-mentioned the 2nd insulant forms in above-mentioned the 1st insulant top.

4, the described conductor integrated circuit device of claim 3, it is characterized in that: the part of above-mentioned the 2nd insulant forms in above-mentioned recess.

5, the described conductor integrated circuit device of claim 1 is characterized in that: the top of above-mentioned conducting objects is positioned at the position also higher than the surface of above-mentioned the 1st, the 2nd device area.

6, the described conductor integrated circuit device of claim 2 is characterized in that: the top of above-mentioned conducting objects is positioned at the position also higher than the surface of above-mentioned the 1st, the 2nd device area.

7, the described conductor integrated circuit device of claim 1, it is characterized in that: the 3rd insulant that also possesses another sidewall formation of a sidewall of the bottom surface along above-mentioned groove, above-mentioned groove, above-mentioned groove, the 3rd insulant has a sidewall by above-mentioned groove, the 1st exposed portions serve that at least one side in above-mentioned the 1st, the 2nd semiconductor regions is exposed, with another sidewall by above-mentioned groove, the 2nd exposed portions serve that at least one side in above-mentioned the 3rd, the 4th semiconductor regions is exposed.

8, the described conductor integrated circuit device of claim 1, it is characterized in that: above-mentioned conducting objects contains any at least in the stromatolithic structure of the silicon of the silicon of refractory metal, refractory metal silicide, the 2nd conduction type and the 2nd conduction type and refractory metal silicide.

9, the described conductor integrated circuit device of claim 1 is characterized in that also possessing:

The 1st charge storage layer that between above-mentioned gate electrode and above-mentioned the 1st device area, forms; With

The 2nd charge storage layer that between above-mentioned gate electrode and above-mentioned the 2nd device area, forms.

10, the described conductor integrated circuit device of claim 2 is characterized in that also possessing:

11, the described conductor integrated circuit device of claim 3 is characterized in that also possessing:

12, the described conductor integrated circuit device of claim 4 is characterized in that also possessing:

13, the described conductor integrated circuit device of claim 5 is characterized in that also possessing:

14, the described conductor integrated circuit device of claim 6 is characterized in that also possessing:

15, the described conductor integrated circuit device of claim 7 is characterized in that also possessing:

16, the described conductor integrated circuit device of claim 8 is characterized in that also possessing:

17, a kind of conductor integrated circuit device is characterized in that possessing:

The groove that in the Semiconductor substrate of the 1st conduction type, forms;

The insulant that in above-mentioned groove, forms;

The gate electrode that above above-mentioned Semiconductor substrate, forms;

The recess that in above-mentioned insulant, forms;

The semiconductor that in above-mentioned recess, forms; With

The semiconductor regions of the 2nd conduction type that in above-mentioned Semiconductor substrate and above-mentioned semiconductor, forms.

18, a kind of manufacture method of conductor integrated circuit device is characterized in that possessing:

In the Semiconductor substrate of the 1st conduction type, form groove;

In above-mentioned groove, form insulant;

Above above-mentioned Semiconductor substrate, form gate electrode;

In above-mentioned insulant, form recess;

In above-mentioned recess, form semiconductor;

In above-mentioned Semiconductor substrate and above-mentioned semiconductor, form the semiconductor regions of the 2nd conduction type.

19, a kind of conductor integrated circuit device is characterized in that possessing:

The 1st insulant that in above-mentioned groove, forms;

The gate electrode that above above-mentioned Semiconductor substrate, forms;

The 2nd insulant that forms in above-mentioned gate electrode top, the 2nd insulant has the etch rate different with the etch rate of above-mentioned the 1st insulant;

The recess that in above-mentioned the 1st insulant, forms;

The semiconductor that in above-mentioned recess, forms; With

20, a kind of manufacture method of conductor integrated circuit device is characterized in that possessing:

In the Semiconductor substrate of the 1st conduction type, form groove;

In above-mentioned groove, form the 1st insulant;

Above above-mentioned Semiconductor substrate, form gate electrode;

Form the 2nd insulant in above-mentioned gate electrode top, the 2nd insulant has the etch rate different with the etch rate of above-mentioned the 1st insulant;

In above-mentioned the 1st insulant, be that mask forms recess with above-mentioned the 2nd insulant at least;

In above-mentioned recess, form semiconductor; With

21, a kind of manufacture method of conductor integrated circuit device is characterized in that possessing:

In the Semiconductor substrate of the 1st conduction type, form groove;

In above-mentioned groove, form the 1st insulant;

In above-mentioned the 1st insulant, form recess;

In above-mentioned recess, form semiconductor;

After in above-mentioned recess, having formed semiconductor, above above-mentioned Semiconductor substrate, form gate electrode;

Form the 2nd insulant in above-mentioned gate electrode top, the 2nd insulant has the etch rate different with the etch rate of above-mentioned the 1st insulant; With

22, a kind of conductor integrated circuit device is characterized in that possessing:

The 1st insulant that forms along another sidewall of a sidewall of the bottom surface of above-mentioned groove, above-mentioned groove, above-mentioned groove, the 1st insulant has a sidewall by above-mentioned groove, the 1st exposed portions serve that above-mentioned Semiconductor substrate is exposed, with another sidewall by above-mentioned groove, the 2nd exposed portions serve that above-mentioned Semiconductor substrate is exposed;

The 2nd insulant that in above-mentioned groove, forms;

The gate electrode that above above-mentioned Semiconductor substrate, forms;

The recess that in above-mentioned the 2nd insulant, forms;

The semiconductor that in above-mentioned recess, forms; With

23, a kind of manufacture method of conductor integrated circuit device is characterized in that possessing:

In the Semiconductor substrate of the 1st conduction type, form groove;

Form the 1st insulant along a sidewall of the bottom surface of above-mentioned groove, above-mentioned groove, another sidewall of above-mentioned groove, the 1st insulant has a sidewall by above-mentioned groove, the 1st exposed portions serve that above-mentioned Semiconductor substrate is exposed, with another sidewall by above-mentioned groove, the 2nd exposed portions serve that above-mentioned Semiconductor substrate is exposed;

In above-mentioned groove, form the 2nd insulant;

Above above-mentioned Semiconductor substrate, form gate electrode;

In above-mentioned the 2nd insulant, form recess;

In above-mentioned recess, form semiconductor; With