CN1430264A - Non-volatile storage structure and its manufacturing method - Google Patents

Abstract

A non-volatile memory structure features that its selection gate is the self-aligned spacing wall formed above the side wall of float/control gate stack, and a single mask is used for removing selection gate layer, etching the channel insulating layer in source region, and doping source wire. Its advantages are no short circuit, sector erasing of memory cells or chip erasing of all memory cells, and use of virtual structure to protecting circuit elements on grinding insulating layer.

Description

Non-volatile memory structure and manufacture method thereof

Technical field

The invention relates to a kind of semiconductor technology, refer to a kind of non-volatile memory structure and manufacture method thereof especially

Background technology

In the past when making the Nonvolatile flash memory; regular meeting uses a kind of very typical processing procedure-local silicon oxidation (local oxidation of Silicon; L0C0S) processing procedure; to isolate and to come each element (as the bit line) on the wafer; but the processing procedure of local silicon oxidation tends to generate the oxide layer of beak shape; we must headspace to the structure of this protrusion; but the size of this projective structure has accounted for sizable ratio in the bit distance between centers of tracks; make interelement distance further to dwindle, the misalignment step becomes the principal element of limiting element size.In view of this, a kind of so-called shallow trench isolation from (shallow trench isolation, STI) technology in response to and give birth to, effectively improve this situation in self aligned mode.

Fig. 1 illustrates the U.S. Patent number 6,013,551 of people such as J.Chen at bulletin on January 11st, 2000, the traditional non-volatile manufacture method of piling up the lock flash memory of content description to Fig. 8.Growth silicon layer 108 above P doping silicon substrate 150 (also can be described as tunnel oxide (tunnel oxide layer), can abbreviate oxide layer as in the following description), deposit a doping polysilicon layer 124 again at oxide layer 108 end faces, this polysilicon layer 124 will form the floating gate (floating gate) of memory cell electric crystal.

Then, form shade 106 on the surface of structure,, cause formation a plurality of grooves 910 (as shown in Figure 2) substrate 150 in via shade Open Side Down etching polysilicon layer 124, oxide layer 108 and substrate 150.

As shown in Figure 3, insert dielectric material in the groove 910 and cover total, its details step is: earlier with hot evaporating method growth silicon layer 90, strengthen chemical vapour deposition technique (plasma enhanced chemical vapor deposion with the electricity slurry then, PECVD) deposition one silicon layer 94, the following again atmospheric chemical vapor deposition (subatomspheric chemicalvapor deposition, SACVD) the thicker silicon layer 96 of deposition one layer thickness.

Then to structure carry out cmp (chemical mechanical polishing, CMP) step, as shown in Figure 4, to expose polysilicon layer 124.

About cmp, we are in this explanation especially a little.Under patterned insulation layer maybe will deposit before one deck, the upper surface that needs planarization insulating layer, because so do the requirement that to relax the little shadow equipment depth of focus that is used for patterned insulation layer or upper layers, if the upper surface of insulating barrier is smooth, then we can accept the depth of focus bigger variability, and this is to being particular importances with little shadow device fabrication small size article.

And chemical mechanical milling method is widely used in the planarization processing procedure, because chemical mechanical milling method is very quick, does not also need at high temperature to carry out.

Handle insulating barrier with chemical mechanical milling method and normally stop at the harder one deck in insulating barrier below, give an example, when handling the silicon layer with chemical mechanical milling method, can before forming the silicon layer, deposit one deck silicon oxide layer earlier, as stopping layer, see also in the U.S. Patent number 5,909,628 " REDUCING NON-UNIFORMITY IN A REFILLLAYER THICKNESS FOR A SEMICONDUCTOR DEVICE " of bulletin on June 1st, 1999.

Then as shown in Figure 5, structurally form an ONO (oxidation silicon, silicon nitride, oxidation silicon) layer 98, deposit a silicon layer 99 then up, then deposit a silicon tungsten layer 100.

Form shade (not drawing) then, and above-mentioned 100,99,98,124 each layers (as shown in Figure 6) of patterning, polysilicon layer 124 will become floating gate at this moment, and silicon layer 99 and silicon tungsten layer 100 will become control sluice (control gate) and character line (wordline) respectively.

As shown in Figure 8, then structurally form shade 101, utilize shade 101 etchings to remove the oxide layer 90,94,96 (as shown in Figure 7) of part, after the etching, keep shade 101, be used to implant alloy to form source electrode line 103.

The implantation step of carrying out other then is with suitable doped source zone and drain zone.

Though said method can dwindle the size of memory,, still need dwindle the size of memory again along with the evolution of processing procedure and the restriction of live width.

Summary of the invention

Therefore, the object of the present invention is to provide a kind of manufacturing to comprise the method for the integrated circuit of non-volatility memorizer, utilize autoregistration step repeatedly to form polysilicon layer (floating gate, control sluice, selection lock), autoregistration and mutual arrangement mode by three's lock, can further reduce bit cable brake distance, the size of dwindling memory more significantly.

According to above-mentioned purpose, the method that the embodiment of the invention provides a kind of manufacturing to comprise the integrated circuit of non-volatility memorizer, this method may further comprise the steps:

(a) form a ground floor on semiconductor regions S1, wherein integrated circuit comprises a plurality of non-volatile memory cell unit, and each memory cell has one by the formed floating gate of part ground floor;

(b) opening via above-mentioned ground floor forms groove in region S 1, and with the filling insulating material groove;

(C) form a ground floor on region S 1, wherein each cell element has one by the formed conduction lock of the part second layer, and the lock (conductive gate) that wherein conducts electricity is isolated with the floating gate of cell element;

(d) the above-mentioned second layer of patterning stretches to rectangular (strip) of specific direction with formation, and each rectangular meeting is across a plurality of grooves;

(e) remove not part ground floor on the region S 1 that is covered by the second layer, to form a plurality of first structures, each first structure comprise one from the second layer form rectangular, and comprise the part ground floor of rectangular below, each first structure also has a first side wall;

(f) on the ground floor and the second layer, form one the 3rd layer, and utilize the 3rd layer of removing part to etching step such as non-, form partition at least a portion the first side wall of each first structure, each partition can be isolated with the first structural ground floor and the second layer;

(g) remove the 3rd layer of the part of subregion S1 top, not exclusively remove partition, wherein each cell element comprises a formed conduction lock of part partition by first structure the first side wall top;

(h) in the region S 1 of at least a portion, mix alloy;

Step (g) and (h) be to utilize single little shadow shade technology to carry out wherein.

Other features and advantages of the present invention can have detailed introduction in the embodiment explanation, the real interest field of the present invention is defined by appended claim certainly.

Description of drawings

Fig. 1 to Fig. 7 is the processing procedure profile of known flash memory;

Fig. 8 is the vertical view of Fig. 1 to Fig. 7 memory;

Fig. 9 A is the vertical view of the memory embodiment according to the present invention;

Fig. 9 B and Fig. 9 C are the profile of Fig. 9 A memory;

Figure 10 A is the circuit diagram of Fig. 9 A memory;

Figure 10 B is the vertical view of Fig. 9 A memory;

Figure 11 and Figure 12 A are the processing procedure profile of Fig. 9 A memory;

Figure 12 B is the vertical view of Figure 12 A structure;

Figure 13 to Figure 15 is the processing procedure profile of Fig. 9 A memory;

Figure 16 is the perspective view of Fig. 9 A memory in processing procedure;

Figure 17 A to Figure 22 B is the processing procedure profile of Fig. 9 A memory;

Figure 22 C is the vertical view of Figure 22 A and Figure 22 B structure;

Figure 23 A to Figure 24 C is the profile of memory embodiment of the present invention in processing procedure;

Figure 25 to Figure 26 C is the profile of memory embodiment of the present invention;

Figure 27 to Figure 29 is the vertical view of memory embodiment of the present invention;

Figure 30 A and Figure 30 B are the profile of memory embodiment of the present invention;

Figure 30 C shows the shade layout of memory embodiment of the present invention;

Figure 31 A to Figure 33 B is the profile of memory embodiment of the present invention;

Figure 34 is the vertical view of memory embodiment of the present invention;

Figure 35 and Figure 36 are the processing procedure profile of Figure 34 memory;

Figure 37 and Figure 38 are the vertical view of Figure 34 memory in processing procedure

Figure 39 to Figure 41 is the processing procedure profile of Figure 34 memory;

Figure 42 is the vertical view of memory embodiment of the present invention in processing procedure;

Figure 43 is the calcspar that is used for the voltage generator of memory embodiment of the present invention;

Figure 44 to Figure 61 is the processing procedure profile of memory embodiment of the present invention.

The figure number explanation:

98,1010,1810,2901,2903,3003: insulating barrier

98.1,98.3,1510,1810,2710,4408,4410: the silicon layer

98.2,720,903,1203,2607: the silicon nitride layer

103: source electrode line

108: tunnel oxide (can be the silicon layer)

110: semiconductor structure

113: dielectric layer

120: memory cell

120S: select electric crystal

120F: floating gate electric crystal

124: floating gate (form by polysilicon, for cooperation illustrates, some the time can be called the polysilicon layer, or unsteady brake cable)

128: control sluice (illustrate for cooperating, some the time be called the control brake cable)

128.1: the polysilicon layer

128.2: the silicon tungsten layer

128A: part

130: the bit line

133: source/drain areas

134,312: bit line zone

138: bit line contact area

141: empty interposed structure

144: source electrode line

144C, 29003C: contact openings

150: substrate regions

520: the character line (form by polysilicon, for cooperation illustrates, some the time can be called the polysilicon layer, or select lock)

520E: lateral projection

710: the stacked structure (or being called array structure) that comprises floating gate and control sluice

901: memory array

904,1014,1710,2501,2810,4501,4601,4801: the photoresistance shade

905: substrate

910: isolated groove

1103,1105:N-zone

1107,2709: the zone

1603: the neighboring area

1810: gate pole oxidation layer

2110,2401: implant

2605: electric conducting material

2701,3010: the gap

2703.1,2703.2: the memory array section

2903: metal tape

3301: petrificating layer

4201: voltage generator

4402,4404,4406,4404D: active area

Embodiment

The narration of relevant preferred embodiment is to illustrate and unrestricted usefulness, unless Wen Zhongyou indicates especially, not so the present invention is not limited to any special size, material, program step, alloy, doping content, crystallization position to, each layer thickness, layout or other element characteristics.

Fig. 9 A is the vertical view of the fast-flash memory display of autoregistration three lock memory cells 120, Fig. 9 B is the profile along the line 9B-9B incision of Fig. 9 A, Fig. 9 C is that Figure 10 A is the circuit diagram of array along the profile of the line 9C-9C incision of Fig. 9 A, and Figure 10 B is the vertical view of other newly-increased features of explanation.

Bit line among the figure (bit lines) the 130th, horizontal expansion, bit line 130 is (as aluminium or tungsten by the conductive layer that is positioned at memory cell 120 tops, do not draw) form, bit line 130 contacts in bit line contact area 138 with the bit line zone 134 of memory cell 120, source electrode line (source lines) the 144th extends longitudinally in 710 of adjacent array structures, each array structure 710 comprises one and controls brake cable (control gate Line) 128 longitudinally, control sluice as each row memory cell, control brake cable 128 in the present embodiment is made up of polysilicon layer 128.1 and silicon tungsten layer 128.2, polysilicon floating gate 124 is positioned at the below of control sluice 128, each floating gate is positioned at adjacent isolated groove 910 locks, and 910 of grooves are laterally to be positioned at 130 on bit line.

Each array structure 710 all is that autoregistration is piled up.

Character line 520 (as doping polysilicon layer) and bit line 130 vertical (or being a special angle), each bar character line 520 can be as the selection lock of a row memory cell, each character line 520 is the autoregistration partitions that form on the sidewall of corresponding stacked structure 710, character line 520 separates by oxidation silicon partition 903 and silicon layer 1510 and adjacent control sluice 128 and floating gate 124, and 903 and 1510 layers only do not need shade to generate.

Shown in Figure 10 A, the memory cell of each row has two cell elements 120 at 130 adjacent on two bit lines, wherein a control brake cable 128 and a character line 520 are shown in each memory, two adjacent memory row are shared a source electrode line 144, in each memory cell 120, a NMOS selects electric crystal 120s and a floating gate electric crystal 120F polyphone, select the gate of electric crystal 120s to be provided by character line 520, the control sluice of floating gate electric crystal 120F is then provided by control brake cable 128.

We can by from floating gate 124 through silicon layer 108 to the Fowler-Nordheim electrons tunnel of source electrode line 144 or substrate regions 150 with each cell element of erasing (zone 150 comprises the passage area of memory cell), and cell element is stylized by the hot electron injection of source terminal, this noun " injection of source terminal hot electron " is that the bit line zone 134 of hypothesis cell element is " source electrode ", in another case, if this zone is a drain, then source electrode line zone 144 is exactly a source electrode, the zone 134 and 144 can be called as source/drain areas, we especially term limit the present invention.

Memory is inside and the top (as shown in figure 11) that is formed at the independent p type island region territory 150 of silicon substrate 905, silicon substrate 905 is formed by monocrystalline silicon or other semi-conducting materials, in certain embodiments, the end face of substrate 905 has a crystal orientation＜100 〉, this substrate mixes with boron, and concentration is that 2E15 is to 2E16atom/cm ³

The generation method of above-mentioned zone 150 is as follows: in substrate 905, implant N type alloy via the shade opening with ionic-implantation, and forming N-zone 1103, can area of isolation 150 and following square structure, give an example, with energy and the 1.0E13atom/cm of 1.5MeV ²Dosage implant phosphorus.

In an independent ion implantation step or a series of ion implantation step, use other shade (not drawing) to implant N type alloy to form N-zone 1105, N-zone 1105 is surrounded zone 150 fully, in certain embodiments, this step can produce N well (not drawing) simultaneously, will form the periphery P MOS electric crystal of peripheral circuit within it, this class circuit has sensing amplifier, input/output driver, decoder, voltage generator or the like, in the CMOS technology, producing this class N well is known technology.

When memory operates, N-zone 1103 is identical or higher with the voltage of substrate regions 150 with 1105 voltage, the reference voltage of following table 1 viewing area 150, the voltage in the zone 1107 of the substrate 905 then voltage with zone 1103 and 1105 is identical or lower, in certain embodiments, make zone 150,1103, the 1105 formation short circuits that are connected together, make regional 1107 ground connection in addition.

The present invention is not particularly limited the isolation technology in zone 150, and also not limiting is the memory with separate substrates zone.

Shown in Figure 12 A, generate silicon layer (or be called tunnel oxide, below abbreviate oxide layer sometimes as) 108 at the end face of substrate regions 150 with thermal oxidation method, in certain embodiments, be the grow up oxide layer of thick 9um of about 800 ℃ dry type oxidation process.

Then, form polysilicon layer 124 at oxide layer 108 end faces, in certain embodiments, be with Low Pressure Chemical Vapor Deposition (low pressure chemical vapor deposition, LPCVD) the polysilicon layer 124 of deposition one bed thickness 120um slightly mixed by (N type) at that time or afterwards in deposition, and above-mentioned polysilicon layer 124 can be as floating gate, perhaps can be as other circuit elements of peripheral circuit, this class component has intraconnections, electric crystal gate, resistor, capacitor board or the like.

End face at polysilicon layer 124 continues deposition one silicon nitride layer 1203, in certain embodiments, it is the nitride that deposits a bed thickness 120nm with Low Pressure Chemical Vapor Deposition, if necessary, also can above polysilicon layer 124, form one deck silicon layer (not drawing) and so can lower stress in elder generation before the depositing nitride.

Above silicon nitride layer 1203, form photoresistance shade 904 then with little shadow technology, and from shade opening etching silicon nitride layer 1203 and polysilicon layer 124, form and equidirectional rectangular (strip) that passes memory array of bit line whereby, in the vertical view of Figure 12 B, " BL " axle points to the direction of bit line, and " WL " axle points to the direction of character line, in certain embodiments, be with reactive ion-etching (reactive ion etching process, RIE) etching polysilicon layer 124 and silicon nitride layer 1203.

Can not influence the cell element geometry even if photoresistance shade 904 is aimed at yet,, only need be adjusted at the part in array edges and neighboring area (zone at peripheral circuit place) yet even need to adjust.

After the etching polysilicon layer 124, opening etching oxide layer 108 and substrate regions 150 from photoresistance shade 904, to form isolated groove 910 (as shown in figure 13), the isolated groove of peripheral circuit (not drawing) also is to form in this step, etching mode then can be selected reactive ion-etching, and gash depth is about 0.25nm.

Remove photoresistance shade 904 then.

Utilize shade etching two-layer or sandwich construction as long as mention here, unless mention especially, otherwise be to utilize this shade only to understand the etching the superiors, after the superiors are etched, remove shade, and then with the superiors that retain as shade, the layer that etching is remaining, or do not need shade, for instance, behind the etching silicon nitride layer 1203, remove resistance shade 904 earlier, be used as shade with silicon nitride layer 1203 then, the polysilicon layer 124 under the etching, oxide layer 108, substrate 150, the silicon nitride layer 1203 that has part is simultaneously etched, but is not to remove fully.

With trench dielectric material filling groove 910 to form an insulating barrier 1010 and to cover wafer (as shown in figure 13), in certain embodiments, insulating barrier 1010 can be generated by following method: above the exposed surface of groove 910 with known rapid thermal oxidation method (rapid termal oxide, RTO) silicon oxide layer of generation one bed thickness 13.5um, and then use high-density electric slurry (highdensity plasma, HDP) chemical vapour deposition technique (chemical vapor deposition, CVD) the silicon layer of deposition one bed thickness 480nm.

Then utilize chemical mechanical milling method (CMP) and/or some comprehensive etch process (blanketetch process) etching to remove partial insulative layer 1010, till exposing silicon nitride layer 1203 (as shown in figure 14), wherein silicon nitride layer 1203 is as etching stopping layer in this step.Remove silicon nitride layer 1203 (as in the wet etching mode) then, or insulating barrier 1010 also etched away, this can utilize regularly wet etching (timed wet etch), last structure can be as shown in figure 15, one smooth superstructure is arranged, or be the sidewall that etching isolation layer 1010 can expose polysilicon layer 124, this can improve the efficient of memory cell, and we will be in hereinafter explanation.

Then, form insulating barrier 98 (shown in Fig. 9 B and Fig. 9 C) in certain embodiments, insulating barrier 98 is oxygen nitrogen oxide (oxide-nitride-oxide, 0N0) structure, its formation method is: at first, under 800 ℃ or lower temperature, adding thermosetting silicon layer 98.1 (as shown in figure 16) with dry type oxidation process above the polysilicon layer 124, the reference thickness of silicon layer 98.1 is 6um, deposit the silicon nitride layer 98.2 of a bed thickness 4um then with Low Pressure Chemical Vapor Deposition, then add thermosetting silicon oxide layer 98.3 being lower than under 850 ℃ the temperature with wet oxidation process.

In Figure 16,98.3 while of silicon layer are as the gate insulation layer of peripheral electric crystal, before forming silicon layer 98.3, on memory array, form photoresistance shade (not drawing) earlier, shade does not cover neighboring area 1603, etch away 98.2 of neighboring area 1603,98.1,124,108 each layers are to expose substrate 905, remove shade then, the oxidation wafer is to generate silicon layer 98.3, the reference thickness of 1603 silicon layer 98.3 is 24nm in the neighboring area, silicon oxide layer 98.3 above memory area silicon nitride layer 98.2 then is that 1nm is thick, silicon oxide layer 98.3 on silicon nitride layer 98.2 is thinner, and this is because the growth speed ratio of silicon on nitride wants slow on silicon substrate 905.

Above insulating barrier 98, form polysilicon layer 128.1, in certain embodiments, deposit the polysilicon layer 128.1 of a bed thickness 80um with Low Pressure Chemical Vapor Deposition, mixed with N+ or P+ at that time or afterwards in deposition, and deposited silicon tungsten layer 128.2 then, its reference thickness is 50nm, silicon tungsten layer 128.2 can form by chemical vapour deposition technique, then deposit ammonification silicon layer 720 above wafer, nitration case 720 can be formed by Low Pressure Chemical Vapor Deposition, and thickness is about 160um.

In certain embodiments, wherein one deck of polysilicon layer 128.1 and silicon tungsten layer 128.2 can omit, or is replaced by other materials.

Then, form photoresistance on silicon nitride layer 720 surface, little shadow patterning photoresistance forms rectangular, character line on itself and the memory array in the same way, this photoresistance shade 1014 will be used for forming stacked structure 710, photoresistance shade 1014 also can patterning neighboring area 1603 peripheral electric crystal gate 128.1,128.2, silicon nitride layer 720, photoresistance shade 1014 do not have to aim at a geometry that can't change memory cell, the border and the neighboring area that only need to adjust memory array get final product.

Etching 720; 128 (promptly 128.1 and 128.2); 98 each layers are with definition stacked structure 710; available etching mode has non-grade to reactive ion-etching; remove resistance shade 1014 earlier then; above neighboring area 1603, form another photoresistance shade (not drawing) again; with silicon nitride layer 720 be under the shade etching polysilicon layer 124 and oxide layer 108; photoresistance can be protected the silicon substrate 905 of peripheral active area; divest photoresistance then; Figure 17 A and Figure 17 B show the memory array profile that generates; its section and bit line parallel; these sections are obtained along arrow 17A and the 17B of Figure 16 respectively; section among Figure 17 B is to downcut along groove 910, and the section of Figure 17 A then is to downcut along the position between adjacent trenches.

Similarly, the section of Figure 18 A, Figure 19 A, Figure 20 A, Figure 21 A, Figure 22 A, Figure 23 A, Figure 24 A, Figure 31 A, Figure 32 A, Figure 33 A is to downcut along the position between adjacent trenches, and the section of Figure 18 B, Figure 19 B, Figure 20 B, Figure 21 B, Figure 22 B, Figure 23 B, Figure 24 B, Figure 31 B, Figure 32 B, Figure 33 B then is to downcut along groove 910.

In certain embodiments, do not form peripheral electric crystal gate with polysilicon layer 128.1 and silicon tungsten layer 128.2, peripheral electric crystal gate is formed by the polysilicon layer that deposits afterwards, and the character line also is formed by the polysilicon layer.This embodiment has omitted first etching 98.2 before forming silicon layer 98.3; 98.1; 124; the step of 108 each layers; and when etching, also omitted with the step of shade protection memory array; when forming photoresistance shade 1014; periphery active area top existing 108; 124; 98; 128; 720 each layers; cover those layers of memory array active area exactly; be etched in these layers in neighboring area and memory array zone simultaneously; so do not need to divest photoresistance shade 1014 after the intact silicon layer 98.3 of etching, above-mentionedly when etching polysilicon layer 124, be used to protect the shade of peripheral active area then can omit.

Oxidation structure (as under 1080 ℃ oxygen atmosphere, carrying out) with the rapid thermal oxidation method, so, can form the silicon layer 1510 (shown in Figure 18 A and Figure 18 B) of thick 5um at the exposed surface of substrate regions 150, the polysilicon layer 124 and 128.1 that this step can allow oxidation expose simultaneously has the horizontal breadth of 8nm at a silicon oxide layer 1510 of polysilicon sidewall.

Deposit the thin silicon nitride layer 903 (shown in Figure 19 A and Figure 19 B) of a bed thickness 20um with Low Pressure Chemical Vapor Deposition, do not need shade, the above-mentioned silicon nitride layer 903 of anisotropic etching promptly can form partition on the sidewall of stacked structure 710.

This etching step can remove simultaneously and be exposed to outer silicon layer 1510, be lower than the silicon layer 1810 of above substrate regions 150, growing up again under 800 ℃ the temperature with dry type oxidation process, this is designated as 1810 silicon layer in Figure 19 A will provide the gate insulation layer of selecting electric crystal, and the reference thickness of this silicon layer 1810 is 5nm.

In certain embodiments, can omit the step that forms silicon nitride layer 903 or silicon layer 1510.

Then, form polysilicon layer 520 (shown in Figure 20 A, Figure 20 B, Figure 21 A, Figure 21 B), in certain embodiments, deposit the polysilicon layer 520 of a bed thickness 300um with Low Pressure Chemical Vapor Deposition, deposition was carried out severe doping (N+ or P+) at that time or afterwards, above-mentioned polysilicon layer 520 is carried out comprehensive anisotropic etching (as reactive ion-etching), fortunately form partition on the sidewall of stacked structure 710, we can control the width of formed polysilicon partition by the vertical thickness of adjusting silicon nitride layer 720 and polysilicon layer 520.

On the stacked structure 710 two ends sidewalls among the embodiment polysilicon partition 520 is arranged all, in certain embodiments, source electrode line 144 is very narrow, so that polysilicon layer 520 can fill up the gap of 710 of source electrode line top stacked structures, and can not form partition on the sidewall near piling up of that end of source electrode line.

Except gate alternatively, polysilicon layer 520 can also be as the circuit element of other peripheral circuits such as intraconnections, electric crystal gate, for this purpose, before etching polysilicon layer 520, can form shade earlier in the neighboring area, above memory cell, then not need this shade.

Above part polysilicon layer 520, utilize little shadow to form photoresistance shade 1710 (shown in Figure 21 A and Figure 21 B), the polysilicon layer 520 of this part will form the character line, photoresistance shade 1710 also can cover part or whole neighboring areas, form the rectangular of character line direction, two adjacent stacks structures 710 that each rectangular and adjacent source polar curve is 144 are overlapping, and covering bit line zone 134, source electrode line 144 is not then covered by photoresistance shade 1710.

The longitudinal edge of photoresistance shade 1710 can be situated in the arbitrary position on the stacked structure 710, therefore if the error that shade is aimed at less than half of stacked structure 710 width, we are for the strictness so of requirement of position.In certain embodiments, minimum characteristic size is 0.14mm, and the admissible error that shade is aimed at is 0.07mm, and the width of each stacked structure 710 is 0.14mm, i.e. the alignment tolerance of twice.

Each stacked structure 710 of etching keeps the polysilicon partition 520 of each stacked structure 710 near that side of bit line near the polysilicon layer 520 (shown in Figure 22 A and Figure 22 B) of that side of source electrode line.

Etch away after the polysilicon layer 520, keep photoresistance shade 1710, implant the usefulness of wafer as N type alloy (as phosphorus), direction as 2110 ratios of arrow among Figure 22 A, severe doping (N+) source electrode line 144, this is to allow source electrode line have high voltage for erasing and/or " deeply " of the operating voltage that stylizes implants, and when alloy spreads to side, dark implantation can be suitable overlapping of 124 formation of doped source polar curve and floating gate.

In certain embodiments, alloy can not penetrate insulating barrier 1010, (shown in Figure 22 B) do not take place so this step does not have the situation of the bottom of doping groove 910, this step impure source line zone is labeled as " 144.0 " in Figure 22 C, no matter whether alloy can penetrate insulating barrier 1010, insulating barrier 1010 all can avoid alloy near or arrive 1103 (as shown in figure 11) of N-zone, therefore can avoid having high leakage current or situation of short circuit to take place at source electrode line 144 and 1103 in N-zone.In certain embodiments, finish back (after being heating steps) at processing procedure, substrate 905 upper surfaces in the territory, upper surface abscission zone 150 in N-zone 1103 are approximately 1mm, and groove 910 degree of depth are 0.25mm.

After the implantation; stay photoresistance shade 1710; and the insulating barrier 1010 that exposes has removed (shown in Figure 23 B) from the groove 910 that is positioned at source electrode line 144 wholly or in part; silicon nitride layer 903 and dioxide layer 1510 can protect for 124 and 128 two-layer unlikely exposing of sidewall; etching mode can be an anisotropic etching, as reactive ion etching.Remove the silicon layer 1810 (shown in Figure 23 A) that is positioned at source electrode line 144 end faces in an etching simultaneously in this step.

Remove shade 1710 then, and carry out comprehensive N+ and implant 2401 with doping bit line zone 134 and source electrode line 144 (shown in Figure 24 A, Figure 24 B, Fig. 9 B, Fig. 9 C), stacked structure 710 and polysilicon layer 520 cover substrate when implanting.In certain embodiments, the implant procedure step is included in the non-zero angle direction of vertical axis (axle of vertical wafer) and carries out the ion implantation, and with the doping trenched side-wall, in certain embodiments, angle is 7 °, 8 ° or 30 °, and alloy can be an arsenic.

Above-mentioned this implantation can't penetrate the insulating barrier 1010 near bit line zone 134, so bit line zone can not form short circuit.

Next can utilize known technology to finish the manufacturing of memory, similarly being can depositing insulating layer (not drawing), form contact openings 138 (shown in Fig. 9 A), deposition and patterning conductive material to be to form the bit line and other must part.

Explanation as the relevant Figure 15 in front, after grinding insulating barrier 1010, it can be etched with the sidewall that exposes polysilicon layer 124, Figure 24 C illustrates this embodiment, this figure is memory passes control sluice 128 along the character line a memory array profile, control sluice 128 comprises the part 128A near floating gate 124 sidewalls, so can improve the capacitive coupling of 124 of control sluice 128 and floating gates.In certain embodiments.Polysilicon layer 124 thick 120nm, wide 140nm, if the upper surface of polysilicon layer 124 greatly about the top 60um of insulating barrier 1010 upper surfaces, just can the be greatly improved coupling situation of 124 of control sluice 128 and floating gates that is petty.

It should be noted that the floating gate 124 autoregistration active area of bit line direction among the present invention especially, 128 autoregistration floating gates 124 of the control sluice of character line direction are selected 520 autoregistration control sluice 128 of lock (character line) then.Its implementation method is utilized the shallow trench isolation technology exactly, opens 124 definition active area (or directly defining floating gate 124 and active area simultaneously with the active area shade) to float, and so floating gate 124 is the autoregistration active area; Then utilize the control sluice 128 definition floating gates 124 when the thick dielectric layer of definition control sluice 128 tops (or also and then define simultaneously floating gate 124 and control sluice 128) of floating gate 124 tops, control sluice 128 like this and autoregistration floating gate 124; Lock 520 (partition) is selected in generation at last, because select lock 520 to generate along the thick dielectric layer of control sluice 128 tops, that is the control sluice 128 of 520 while of the selection lock also autoregistration thick dielectric layer below of character line direction.

Utilize autoregistration step repeatedly, not only can effectively reduce the size of memory, can also guarantee the electrical conductivity of each cell element, though select the misalignment of 128 of lock 520 and control sluice can't change the electrical conductivity of memory cell, but determined the electrical conductivity of memory cell because of the passage length of selecting 124 of lock 520 and floating gates, so selecting the misalignment of 124 of lock 520 and floating gates is the electrical conductivity that can have influence on memory cell, change design element electrically, utilize processing procedure of the present invention can effectively improve this class deviation.

In certain embodiments, the gate of periphery electric crystal is to be formed by 520 on polysilicon layer, rather than by 128 layers form, the part of the relevant Figure 16 in front was carried, so need before deposition control sluice layer 128, not cover memory array earlier, and 1603 remove polysilicon layer 124 and 98.2,98.1,108 each layers from the neighboring area.Forming among the embodiment of peripheral electric crystal gate with polysilicon layer 520, photoresistance shade 1014 can't cover neighboring area 1603, or can not cover the zone that peripheral electric crystal gate will form at least, therefore, when definition stacked structure 710, can etch away 108,124,98,128,720 each layers in neighboring area or peripheral at least electric crystal gate zone, expose the substrate 905 of peripheral active area.

Handle wafer (shown in Figure 17 A to Figure 19 B) as above-mentioned mode then, silicon layer 1810 will form the gate insulation layer of peripheral electric crystal.

Deposit polysilicon layer 520 as mentioned above, the structure of coming out as shown in figure 25, before anisotropic etching polysilicon layer 520, form photoresistance shade 2501 in the top, neighboring area that will form peripheral electric crystal gate and other elements (as intraconnections, resistor or the like) earlier, the anisotropic etching polysilicon 520 then, then remove photoresistance shade 2501, remove photoresistance shade 2501 neighboring area profile afterwards shown in Figure 26 A, the profile of memory array is then shown in Figure 20 A and Figure 20 B

In certain embodiments, can reduce the resistance of peripheral electric crystal gate by the following step, after deposition polysilicon layer 520 (as shown in figure 25), above polysilicon layer 520, form one deck silicon tungsten or other layer of low resistance material (not drawing), above the neighboring area, form photoresistance shade 2501 then, silicon tungsten or the other materials layer that is not covered by photoresistance shade 2501 on the polysilicon layer 520 removed in etching, then polysilicon layer 520 is carried out anisotropic etching, to form partition (shown in Figure 20 A and Figure 20 B), and define peripheral electric crystal gate and other peripheral elements, remove photoresistance shade 2501 then, so silicon tungsten or other electric conducting materials 2605 will cover the polysilicon layer 520 (shown in Figure 26 B) of neighboring area, if electric conducting material 2605 and polysilicon layer are by the while etching, then polysilicon layer 520 top of memory array also may stay some electric conducting materials 2605.

Removed polysilicon layer 520 at that time from source electrode line, photoresistance shade 1710 (shown in Figure 11 A) can the peripheral active area of protection.

In certain embodiments, before forming photoresistance shade 2501, above polysilicon layer 520, deposit one deck silicon nitride layer 2607 (shown in Figure 26 C) earlier, if electric conducting material 2605 is the resistance that is used to reduce peripheral electric crystal gate, then silicon nitride layer 2607 is deposited on electric conducting material 2605 tops, above peripheral electric crystal gate, form photoresistance shade 2501 then as mentioned above, etching is the silicon nitride layer of coated region not, mode according to Figure 25, Figure 26 A, Figure 26 B is handled wafer, and Figure 26 C is the profile that the neighboring area has the embodiment of electric conducting material 2605.When after a while structure being carried out cmp, silicon nitride layer 720 and 2607 can be as etching stopping layer, when the stage of Figure 24 A and Figure 24 B (after doped source polar curve and the bit line), when structure is insulated material (as vapour deposition oxide (vapor deposited oxide (vapox), do not draw) cover after, carrying out cmp can the planarization wafer.In certain embodiments; insulating barrier is as the last layer protective layer before wafer cutting or the encapsulation; and in certain embodiments; the material of insulating barrier can be to mix or the silicon layer that do not mix; as boron phosphorus silicon glass (borophosphosilicate glass; BPSG), can also use other material.

In certain embodiments, some peripheral electric crystal gates or other elements be by 128 layers form, other peripheral gate or element then are to be formed by 520 on polysilicon layer, the back will illustrate a this embodiment according to Figure 44 to Figure 50.

Reduce the resistance of polysilicon layer (character line) 520, can utilize metal tape, each strip metal band is positioned on the character line, and with certain all period interval contact with the character line (as per 128 the row), because character line 520 is narrow partitions, still have low resistance even there is small embossment to contact with metal tape, photoresistance shade 2501 can be used for forming this projection.Figure 27 is the vertical view of this embodiment, show and utilize anisotropic etching polysilicon layer 520 to form after the partition, memory array is blocked and a gap 2701 is arranged, gap 2701 and bit line are in the same way, so produce and to form the space of character line projection, gap 2701 can be used for groove 910, memory array section 2703.1 is positioned at a side (it seems that Figure 27 be to be positioned at the top, gap) in gap, memory array section 2703.2 then depends on the below, gap, character line 520 and stacked structure 710 be continual to stride across section 2703.1 and 2703.2 and the gap, part polysilicon layer 520 before carrying out etching formation partition in formed shade 2501 coverage gap 2701, Figure 28 shows the vertical view that removes photoresistance shade 2501 and form photoresistance shade 1710 post gaps 2701 zones.

Gap 2701 numbers of a memory array can be selected arbitrarily, give an example, and can a gap just be arranged every 128 row (bit line) in a memory array, and certainly, a memory also can have the memory array of arbitrary number.

In Figure 27, photoresistance shade 2501 comprises extend along the gap rectangular, photoresistance shade 2501 is blocked in the zone 2709 of 520 on adjacent character line, but the polysilicon layer 520 of etching character cable brake like this, therefore can avoid forming short circuit between adjacent character line, one can break can be continuous above source electrode line 144 for photoresistance shade 2501, and the photoresistance shade above source electrode line need not interrupt, this be stranded for the polysilicon layer 520 in etching source electrode line zone be to utilize photoresistance shade 1710 (as shown in figure 28).

Photoresistance shade 2501 also can cover peripheral electric crystal gate and other peripheral elements, as the narration of top relevant Figure 25.

Photoresistance shade 1710 (as shown in figure 28) can have identical geometry external form with the photoresistance shade that top relevant Figure 21 A is narrated to Figure 23 B, above-mentioned same purposes also can be arranged, be etching source electrode line 144 polysilicon layer 520, to source electrode line implant 2110 deeply, the insulating barrier 1010 of etched trench, Figure 29 shows the polysilicon layer 520 of etching source electrode line, and each polysilicon (character line) 520 has lateral projection 520E in gap 2701.

Handle wafer with reference to previous Figure 22 A to Figure 26 C then, if insulating barrier 1010 is to carry out etching with reference to the mode of figure 23B, then remove the insulating barrier 1010 in the gap 2701 that is positioned at source electrode line 144 wholly or in part, channel bottom and sidewall in the memory array intermediate gap simultaneously mix, so, source electrode line 144 can pass the gap and uninterrupted.

Figure 30 A shows the profile that is positioned at than gap of storage 2701 inside of back-end process, above memory cell, formed insulating barrier 2901, each metal tape 2903 is positioned at the top of corresponding character line 520, and the opening 2903C via insulating barrier 2901 contacts with character line 520 in lock crack 2701.In Figure 30 A, the upper surface of polysilicon layer 520 is high together with the upper surface of control control lock 128 top silicon nitride layers 720, and this is because polysilicon layer 520 is handled through chemical mechanical milling method, stops when running into the silicon nitride layer.Particularly, insulating barrier 2901 is made up of plural layer, and some layer is to deposit after the step of Figure 24 A and Figure 24 B, handles through cmp again, then forms other layers to finish a complete insulating barrier 2901.Polysilicon layer 520 and silicon nitride ply in other embodiments.

In certain embodiments, the do not use up width (be Figure 28 and Figure 29 heavy ruler cun) in whole gap 2701 of isolated groove 910, the composite bed isolated groove can be positioned at the gap, or also can be without any groove in the gap.

Figure 30 B and Figure 30 C are respectively memory section and the shade layouts of another embodiment, Figure 30 c shows photoresistance shade 904,1014,2501 (please also refer to Figure 12 A, Figure 12 B, Figure 16, Figure 27), bit line contact 138 can with the contact openings 290C etching simultaneously of polysilicon layer 520, also can be not simultaneously, the contact openings 144C of source electrode line 144 also can contact 138 or polysilicon contact 2903C etching simultaneously with the bit line.In certain embodiments, the contact openings (not drawing) of contact openings 138,2903C, 144C and control sluice 128 is to use same photoresistance shade to carry out etching synchronously, from shade Open Side Down etching silicon nitride layer 720 to expose control sluice, the contact openings 2903C of polysilicon layer 520 does not link to each other with control sluice 128, forms short circuit to avoid character line 520 and control sluice 128.

Contact openings 138 can use known technology to fill up with N+ doping polysilicon connector, if because the contact shade not have to aim at make contact openings 138 etch effects the interior insulating barrier 1010 of groove 910, the insulating barrier 1010 that then is removed in the groove will be received in the N+ polysilicon when forming connector, the polysilicon connector can avoid Metal Contact and 150 in P doped substrate zone to form short circuit.

In certain embodiments, can form short circuit between the adjacent source electrode line 144, for example, source electrode line can four is one group, four source electrode lines of each group can with the metal tape 2903 formation short circuit of joining, metal tape 2903 can contact with source electrode line via the 3010 inner opening 144C of the gap between the memory array adjacent lines, the source electrode line short circuit can be reduced needs to connect the zone of source electrode line to higher metal layers (not drawing), only need a contact openings (not drawing) because four source electrode line contacts with higher metal layers, the resistance that also can be used for reducing source electrode line that contacts with higher metal layers, can be formed at the source electrode line top by the formed metal tape of higher metal layers, contact at interval with metal tape 2903,3010 inner opening 144C contact metal tape 2903 in the gap with source electrode line, and memory array can have a plurality of gaps 3010.For four source electrode lines of each group, the formation short circuit that also can be connected together of eight of being followed control brake cable 128.

By photoresistance shade 1014 defined control brake cables 128 along source electrode line contact openings 144C bending, if it is very close in the bit line zone 312 of adjacent control brake cable 128 in gap 3010, polysilicon layer 520 may be inserted in the above-mentioned zone 312, cause character line 520 to form the short circuit of trouble in these zones, for fear of short circuit, can use photoresistance shade 1710 (Figure 28) to remove polysilicon layer 520 in the gap 3010, this can make that character line partition 520 is blocked in gap 3010, the particular character line in 3010 in lockage crack can not be electrically connected with metal tape 2903 (shown in Figure 30 B), and 2903 of metal tapes contact with the character line in gap 2701.

It is similar with Figure 24 B to Figure 24 A with 2703.2 section with 3010 memory array section 2703.1 to be positioned at lock crack 2701, and metal tape 2903 is positioned on the character line, but is not in contact with it in memory array section 2703.1 and 2703.2.

In certain embodiments, can be by silicon source electrode line 144 to reduce its resistance, for example, deposit cobalt or other suitable metals on the structure in stage (before or after the bit line zone 134 of promptly mixing) of Figure 24 A and Figure 24 B, heating wafer feasible exposed silicon and cobalt or other metal reactions, and the silicon compounds of formation conduction, remove unreacted cobalt or other metals then, this silicon compounds just can be stayed source electrode line 144 and character line 520 tops, above-mentioned silicon step therewith in the field known silicon processing procedure (being the autoregistration silicon compounds) identical.

In certain embodiments, insulating barrier 1810 may be not enough to avoid cobalt or other metals and 134 in bit line zone to form short circuit, therefore, character line 520 is to form short circuit with bit line zone 134, we can utilize following method to avoid this situation: after wafer is through Figure 20 A and the processing in Figure 20 B stage, just before deposition photoresistance shade 1710, first depositing insulating layer 3003 (as Figure 31 A and Figure 31 B), the material of above-mentioned insulating barrier 3003 can be a silicon.Aforesaid then method, form photoresistance shade 1710 in regular turn, then remove the insulating barrier 3003 that exposes in photoresistance shade 1710 outsides, again with the processing of wafer through Figure 21 A to Figure 23 B step, particularly be exactly etching polysilicon layer 520 and doped source polar curve 144 (promptly implanting 2110), remove photoresistance shade 1710 then, just the structure of generation is shown in Figure 32 A and Figure 32 B.

And then deposition layer of metal (as cobalt), the heating wafer makes the silicon in metal and the source electrode line zone react, and removes unreacted metal, and is last, just forms petrificating layer 3301 (shown in Figure 33 A and Figure 33 B) above source electrode line.

Under certain conditions, if there is not complete etching to remove the insulating barrier 1010 (shown in Figure 23 B) that is positioned at groove 910, then the silicon compounds 3301 in the groove 910 can be blocked.

Then, continue etching isolation layer 3003, implant 2401 (shown in Figure 24 A and Figure 24 B) in bit line zone 134 and source electrode line, or can pass insulating barrier 3003 and implant, insulating barrier 3003 also can be selected to be retained in the memory certainly.

And source electrode line silicon technology can be used with the embodiment (being that peripheral electric crystal gate is to be formed by 128 on control sluice layer) of Figure 16, also can use with the embodiment (being that peripheral electric crystal gate is to be formed by 520 on polysilicon layer) of Figure 25, Figure 26 A, Figure 26 B, Figure 26 C, or use with the embodiment ( polysilicon layer 128 and 520 all is used for as peripheral electric crystal gate) of Figure 44 to Figure 50, this part will illustrate that the silicon technology also can combine with protruding 520E (extremely shown in Figure 30 as Figure 27) in the back.

Figure 34 explanation is according to another fast-flash memory array of the present invention, and each isolated groove 910 protrudes between the adjacent source electrode line 144, but does not intersect with source electrode line, and we are denoted as 910B to the border of isolated groove.

The processing procedure of above-mentioned sort memory is as follows: doped substrate 905 forms area of isolation 150 (as shown in figure 11), form tunnel oxide 108, polysilicon layer 124, silicon nitride layer 1203, photoresistance shade 904 (shown in Figure 12 A and Figure 12 B) then in regular turn, patterning silicon nitride layer 1203 and polysilicon layer 124, but, this step does not have etching substrates zone 150, whether 108 of tunnel oxides can be decided in its sole discretion and will etch away, then remove photoresistance shade 904, the structure that obtains just as shown in figure 35.

Then, deposit the silicon oxide layer 2710 (as shown in figure 36) of the 300nm of a bed thickness with chemical vapour deposition technique, as boron phosphorus silicon glass, 2810 (as shown in figure 37) of little then shadow patterning photoresistance shade, making becomes the rectangular of character line direction, each is rectangular to be positioned at the zone that source electrode line 144 will form, other elements of photoresistance shade 2810 and memory (as control sluice 128) relevant (as shown in figure 38), and this step does not also form control sluice 128.

By the selection of photoresistance shade 2810 and silicon nitride layer 1203 is removed the dioxide layer 2710 and 108 that photoresistance shade and silicon nitride layer 1203 are surrounded than etching, remove photoresistance shade 2810 then, with dioxide layer 2710 and silicon nitride layer 1203 is shade etching substrates zone 150, forms rectangle groove 910; Or in etching substrates zone 150 o'clock, photoresistance shade 2810 can be kept, under this situation, do not need to deposit dioxide layer 2710.Figure 39 shows the section of the embodiment that uses dioxide layer 2710, and this section is the resultant plane by groove of line 39-39 cutting-out along Figure 37, and the plane section by groove is then not the same with Figure 36.

And then deposit an insulating barrier 1010 (as shown in figure 13), and remove partial insulative layer 1010 (as shown in figure 14) with chemical mechanical milling method, then removing silicon nitride layer 1203, selective etch insulating barrier 1010 causes upper surface to become a flat surfaces.Figure 40 B is a resulting structures at parallel character line and the section plan by groove, and Figure 40 A then is by the section plan between adjacent trenches, and some insulating barrier 1010 may cover the substrate regions 150 of source electrode line 144 parts.Source electrode line does not stride across groove (some dioxide layer 2710 can be stayed on the sidewall of polysilicon rectangular 124, and at this moment oxide layer seems can similarly to be the part of insulating barrier 1010).

In certain embodiments, can etching remove partial insulative layer 1010,, improve the capacitive coupling (shown in Figure 24 C) of 124 of control sluice 128 and floating gates whereby to expose the sidewall of polysilicon layer 124.

Remaining fabrication steps can be identical with aforementioned Figure 16 to Figure 33 B, as form steps such as insulating barrier (material can be oxygen nitrogen oxide layer, ONO layer) 98, control sluice layer 128, silicon nitride layer 720, photoresistance shade 1014 (being that peripheral electric crystal gate can be formed by 128 layers or 520 on character line layer).

Form silicon layer 1510 (shown in Figure 18 A) then, silicon nitride partition 903 and silicon layer 1810 (shown in Figure 19 A).

Deposition and anisotropic etching polysilicon layer 520 (shown in Figure 20 A), form photoresistance shade 1710 (shown in Figure 21 A) then, the polysilicon layer 520 at etching source electrode line 144 places (shown in Figure 22 A), but can not etching as for insulating barrier 1010 etchings at source electrode line 144 places, implant 2110 then, because source electrode line does not intersect with groove 910, the current implantation whole rectangular source electrode line that mixes, the structure that generates is identical with Figure 22 A, and Figure 41 shows the section (being that this profile is to suppose the insulating barrier 1010 at etching source electrode line place) along groove.

Explanation as the relevant Figure 24 A in front and Figure 24 B, remove photoresistance and invite cover 1710, carry out the N type and implant 2401 doping bit lines zone 134 and source electrode line 144, insulating barrier 1010 that can first etching source electrode line place before implanting 2410 steps, or between implantation 2110 and 2410 steps, carry out etching, or after implanting 2410 steps, carry out, or not etching.

In certain embodiments, the bossing 520E of Figure 27 to Figure 30 is taken as character line 520; In certain embodiments, shown in Figure 24 A, Figure 31 A to Figure 33 B, meeting silicon source electrode line 144 is to reduce its resistance.

In Figure 42, we have omitted dioxide layer 2710 and photoresistance shade 2810, isolated groove 910 shown in Figure 12 A be by photoresistance shade 904 definition, but because groove 910 is rectangular (as shown in figure 37), therefore silicon nitride layer 1203 and polysilicon layer 124 have same profile with the composite bed of Figure 37, groove 910 has same profile with the groove of Figure 34 to Figure 41, remove the insulating barrier 1010 (as shown in figure 15) of source electrode line 144 tops with chemical mechanical milling method, remaining fabrication steps is just the same with Figure 37 to Figure 41, when definition stacked structure 710, and the polysilicon layer 124 and the dioxide layer 108 of the source electrode line of etching simultaneously 144 tops, this step can expose source electrode line 144.

At Fig. 9 A in the embodiment of Figure 43, be to utilize source terminal hot electron injection method (make the become non-conductive) memory cell that stylizes, see also " the Nonvolatile Semiconductor Memory Technology " the 21st to 23 page that people such as W.D.Brown delivered in 1998, following table 1 is listed the memory reference voltage that drives with 1.8V external power source supply (VCC), oblique line is to be used for representing selecting/voltage of non-selection memory column or row, give an example, table 1 " stylizing " OK, " bit line zone 134 " row, it is 0V that the bit line is selected in project " 0V/V3 " expression, and not selected bit line is voltage V3, and we do not list all non-selection voltages.

The erasing of memory cell can use from floating gate 124 to source electrode line 144 " via the source electrode line sector of erasing " of table 1 (please refer to OK) or wear tunnel to the Fowler-Nordheim of substrate regions 150 (" via the substrate sector of erasing "), the latter is than preferable technology, because reduced band and interband (band-to-band) electric current.In the fast-flash memory array of Figure 10 B and Figure 34, the whole zone (sector) of can only erasing, and other cell element of can not erasing, a zone is meant row or an ordered series of numbers, the source electrode line 144 of their correspondence is connected to form short circuit via circuit, and corresponding control brake cable 128 also is connected to form short circuit via circuit.

Some embodiment provide the erase a plurality of zones or the selection of whole memory array in the single operation step, the cell element that wherein utilizes from floating gate 124 to substrate regions 150 Fowler-Nordheim electrons tunnel to be remained to be erased to erase synchronously, " wafer is erased " of Here it is table 1, zone 150 is a forward bias with respect to all control sluice, array is erased the speed that adopts the wafer erase mode can be faster than what come by the row erase mode, and this is particularly useful when testing memory.

Table 1

	Stylize	Via the source electrode line whole zone of erasing	Via the substrate whole zone of erasing	Wafer is erased	Read
						Control sluice
128	+10V/0V	-10V	-10V	-10V	1.8V
						Bit line zone 134	0V/V3 **(VCC＝1.8V)	V4 ***(VCC＝1.8V)	Float	Float	1.5
Source electrode line 144	6V	5V	Float	Float	0V
						Select gate
520	VTN+ΔV 1 *	0V	0V	0V	VCC+ΔV 2 *(VCC＝1.8V)
						Substrate regions 150	0V	0V	6V	6V	0V

Annotate:

* in an embodiment, VTN=0.6V, Δ V ₁=0.9V, Δ V ₂=1.4V.

* V3 is greater than 0V ₁Voltage.

* * V4 voltage range 0＜V4＜VCC.

Article one, memory can have a plurality of memory arrays, and each memory array all has bit line and the character line of oneself, and different arrays can be placed on identical substrate regions 150 or be placed on the different isolated substrates zone 150 of same integrated circuit." wafer is erased " operates the memory cell that can erase on some substrate regions 150, and can not erase at the cell element of other substrate regions 150.

Voltage generator and decoder block 4201 (as shown in figure 43) can use known technology in response to power supply supply voltage VCC, address signal " ADDR ", other the necessary voltages of generation such as order/controlling signal.

Figure 44 explanation is according to the thickness of the golden oxygen half electric crystal of the resultant difference of the memory embodiment gate insulation layer of Fig. 9 A to Figure 43, the gate insulation layer that need approach during high speed operation, on the contrary, the electric crystal that is exposed under the high voltage then needs thicker gate insulation layer, simultaneously, tunnel oxide 108 also will have enough thickness to remember long data.

In will narrating below among the embodiment at once, all gate insulation layer all are the silicon layers, but this is not certain, and the thickness of relevant gate insulation layer is hypothesis VCC=1.8V, and operating voltage as above table 1 is listed, these voltages only for the explanation but not be used for limiting the present invention.

In Figure 44, tunnel oxide 108 thick about 9um select 1810 of electric crystal gate pole oxidation layers will relatively approach (as 5nm), and are still also enough thick so that quick computing to be provided, and just withstand voltage 3.2V (the VCC+ Δ V in the example that is used as read operation in the table 1 ₂=3.2V).

Neighboring area 1603 comprises active area 4402,4404,4406, high voltage active area 4402 is to use to the electric crystal under-10V voltage (seeing also table 1) and other high voltages to being exposed to 10V, these electric crystals may be voltage generator 4201 parts of (as shown in figure 43), thicker on the gate pole oxidation layer 4408 in zone 4402, about 22 to 25nm is thick.

High speed active area 4404 is to use to being exposed to the electric crystal that is lower than under the VCC voltage, these electric crystals may be the parts of address decoder, sensing amplifier, time pulse signal generator, voltage generator, address and data buffer and other circuit, their gate pole oxidation layer 4410 is quite thin, and about 3.5nm is thick.

I/O active area 4406 is to using as the electric crystal that cuts off the wafer circuit interface, cutting off wafer circuit may operate under higher power supply supply voltage, as 2.5V or 3.3V, so the I/O electric crystal must have thicker gate pole oxidation layer to bear so high voltage, in Figure 44, I/O electric crystal gate pole oxidation layer 1810 is same one decks with selecting electric crystal gate pole oxidation layer 1810, and it is thick to be about 5um.

In Figure 44, the electric crystal gate in zone 4402 and 4404 is to be formed by 128 on control sluice layer, the I/O electric crystal gate in zone 4406 and the selection lock 520 (being the character line) of memory cell are to be formed by 520 on polysilicon layer, explanation as Figure 26 B and Figure 26 C, selecting can have metal level and/or silicon nitride layer on the lock 520, and control sluice 128 is formed by polysilicon polysilicon metal or other conductive layers.

The processing procedure of above-mentioned formation gate insulation layer is as follows: the tunnel oxide 108 (shown in Figure 12 A) that generates thick 9nm, above-mentioned oxide layer 108 is to be created on the entire wafer (to comprise neighboring area 1603), deposit then and patterning polysilicon layer 124, then form isolated groove 910, and fill up groove 910 with insulating material 1010, see also Figure 12 A to Figure 15, Figure 37, Figure 42 and relevant explanatory note.

Form silicon layer 98.1 and silicon nitride layer 98.2 (as shown in figure 16), the reference thickness of above-mentioned these layers is respectively 1nm and 5nm.

Deposition and little shadow patterning photoresistance shade 4501 make it cover memory array (as shown in figure 45) then, and 98.2,98.1,124,108 each layers of etching neighboring area 1603 are to expose substrate 905.

Then, remove photoresistance shade 4501, oxidation wafer under 850 ℃ or lower temperature, so can generate the silicon layer 4408 (as shown in figure 46) of thick 24um in active area 4402,4404,4406, simultaneously, above the silicon nitride layer 98.2 of memory array active area 901, then form the silicon layer 98.3 of thick 1nm to 1.5nm.

Deposition and patterning photoresistance shade 4601 make it cover whole memory array and high voltage active area 4402 then, and active area 4404 and 4406 is not covered, and therefore are able to the silicon layer 4408 of etching active area 4404 and 4406.

Remove photoresistance shade 4601 then, generally speaking, remove photoresistance step afterwards and normally clean wafer, the dioxide layer 4408 that cleaning not too can failure area 4402 in this embodiment, this is because dioxide layer 4408 is very thick, and thin oxide layer 4410 (as shown in figure 44) is because of can contacting with photoresistance, so also can be because of removing the cleaning behind the photoresistance and cause damage.

Oxidation wafer then, generate the silicon layer 4410 (as shown in figure 47) of thick 3.5nm in active area 4404 and 4406, but serviceability temperature is lower than 850 ℃ dry type oxidation process here, and this step makes the thickness of dioxide layer 4408 (promptly in the zone 4402) be increased to about 25um.

On wafer, deposit control sluice layer 128 and silicon oxide layer 720 then, form photoresistance shade 1014, and the electric crystal gate that utilizes this photoresistance shade 1014 to define stacked structures 710 and be positioned at high-voltage region 4402 and high-speed region 4404, photoresistance shade 1014 does not cover I/O active area 44406, and in regular turn etching photoresistance shade 1014 with the silicon nitride layer 720 under exposing, control sluice layer 128, and 98.3,98.2,98.1,4408,4410 each layers are as long as wherein run into the polysilicon layer 124 of array active area 901 and the substrate 905 of peripheral active area promptly stops in etching process.

Remove photoresistance shade 1014 then; form another photoresistance shade 4801 (as shown in figure 48) and cover all neighboring areas 1603 (have the zone that forms silicon nitride layer 720 can be) without photoresistance shade 4801; on the etched wafer not by the polysilicon layer 124 and the silicon layer 108 of 720 protection of photoresistance shade 4801 and silicon nitride layer; so form stacked structure 710; remove photoresistance shade 4801 then, the structure that is generated as shown in figure 49.

Then; continue to form silicon layer 1510 and silicon nitride layer 903 (shown in Figure 19 A and Figure 19 B); sidewall with protection stacked structure 710; oxidation wafer then; above the exposed substrate 905 of the exposed substrate regions 150 of memory array active area 901 and I/O active area 4406, form the silicon layer 1810 (as Figure 20 A and shown in Figure 44) of thick 5um; then deposition and patterning polysilicon layer 520 are with as I/O periphery electric crystal gate (shown in Figure 25, Figure 26 A, Figure 26 B, Figure 26 C).

As mentioned above; when carrying out cmp; the silicon nitride layer 2607 (shown in Figure 26 C) of active area 4406 polysilicon layers 520 top can be protected polysilicon layer 520; if if but do not form above-mentioned silicon nitride layer 2607; also can protect polysilicon layer 520 in the mode of Figure 50; its method is: form empty interposed structure at " void is put (dummy) " the regional 4404D near electric crystal active area 4406 earlier; void is put the treatment step and high-speed region 4404 identical (Figure 44) in zone; so can form silicon nitride layer 720 at regional 4404D; the upper surface of silicon nitride layer 720 is than the upper surface height of regional 4406 polysilicon layers 520; when covering brilliant figure and carrying out cmp with silicon (not drawing) after a while; the silicon nitride layer 720 of zone 4404D can not allow the silicon of regional 4406 polysilicon layers 520 top be removed, and so can protect polysilicon layer 520.

In addition, void is put regional treatment step also can be identical with high-voltage region 4402, perhaps, available different void is put the zone and is surrounded each I/O electric crystal active area 4406, some is a mode of utilizing zone 4402, some then utilizes the mode in zone 4404, or is provided in the single disposal structure that arbitrary side surrounds element.Some regional 4404D can not be that void is put the zone, promptly can form electric crystal in these zones.Can utilize isolated groove 910 that regional 4404D is separated with zone 4406, perhaps regional 4404D may be partly overlapping with isolated groove, or be positioned at the top of isolated groove fully.

Below we at mode with empty interposed structure protective circuit element, be described further again.

Figure 51 is the profile of semiconductor structure 110, and this structure comprises that semiconductor substrate 905, polysilicon layer 128 and 520, protective layer 720 its materials can be silicon nitride), dielectric layer 113.Circuit structure 121.1 comprises by polysilicon layer 128 formed circuit element 128.1 and by polysilicon layer 520 formed circuit element 520.1, in one embodiment, said elements 128.1 can be the gate of capacitor board or membrane transistor, and element 520.1 can be source electrode, drain and/or the passage area of capacitor board, electric crystal, both can be different devices, for example, element 128.1 can be the electric crystal gate, and element 520.1 can be resistor, capacitor board, intraconnections etc.

Polysilicon layer 520 provides circuit element 520.2, in the embodiment of Figure 51, element 520.2 is gates of electric crystal 121.2, electric crystal 121.2 has source/drain areas 129 in substrate 905, electric crystal 121.2 has gate insulation layer 1810 at substrate 905 and 520.2 of gates, the present invention does not limit this class electric crystal, and element 520.2 can be capacitor board, resistor, intraconnections or any other element.Similarly, polysilicon layer 128 provides circuit element 128.3, and in Figure 51, element 128.3 is gates of electric crystal 121.3, electric crystal 121.3 comprises the source/drain areas 133 that is formed in the substrate 905, and gate insulation layer 4410 is gate 128.3 and substrate 905 separately.

The protection feature 720.1 and 720.2 be by 720 layers form, can protection component 128.1,520.1,520.2 when cmp dielectric layer 113.

The element 128.3 of at least a portion does not have protected seam 720 to cover.

Form empty interposed structure 141 in place near element 128.3; can when cmp dielectric layer 113, protect this circuit element; each empty interposed structure comprises by polysilicon layer 520 formed part 520.3; can cover other part 520.3 by protective layer 720 formed feature member 720.3; feature 520.3 can be as any circuit element; any electrical functionality is not provided yet, can be connected to a fixed voltage or allows it float.

Field area of isolation 1010 is formed by the shallow trench isolation technology, or can utilize local silicon oxidation (local oxidation of silicon, LOCOS) technology or other technologies formation; Empty interposed structure 141 is positioned at an area of isolation 1010 tops, but this not necessarily.

Because the non-flat forms influencing profiles of each element; make that the upper surface of dielectric layer 113 is also uneven; we carry out cmp to dielectric layer 113; stop when running into protective layer 720; reach the purpose of planarization whereby; the structure that generates is shown in Figure 52; the upper surface of structure may be fully smooth; or also leave some non-flat forms zones; a reason that forms non-flat forms is each feature member 720.1; 720.2; 720.3 it is and uneven; wherein element 720.2 and 720.3 upper surface are lower than the upper surface of element 720.1; also have; dielectric layer 113 upper surfaces of element 128.3 tops also can be lower; this is because the below does not have the structure of protective layer 720; the not good reason of another flatness may be that element is lower in some partial density of integrated circuit; see also in the U.S. Patent number 5 of bulletin on June 1st, 1999; 909; 628 " REDUCING NON-UNIFORMITYIN A REFILL LAYER THICKNESS FOR A SEMICONDUCTOR DEVICE "; but; through after the cmp; the upper surface of structure 110 is more smooth, belongs to substantive smooth.

In certain embodiments; gap is less than 15nm between the low spot of the height point of protective layer 720 and dielectric layer 113; the degree of known non-flat forms is relevant with thickness, milling time, the cmp parameter (as pressure) of dielectric layer 113; the degree of non-flat forms is also relevant with specific cmp technology (as using mud or low mud fixed abrasive), and the present invention does not limit any specific cmp processing procedure or non-flat forms degree.

In certain embodiments, not every protective layer 720 all is subjected to grinding influence, such as has only higher feature member 720.1 can be subjected to grinding influence, and lower feature member 720.2 then can not.

Empty interposed structure 141 meeting protection components 128.3 are unaffected, in certain embodiments, adjacent structure 141 spacings of element 128.3 two opposite sides are about 5mm, and layer 720 be the silicon nitride of thick 160nm, and void is put upper surface about 0.21mm above element 128.3 of feature member 720.3; In other embodiments, empty interposed structure 141 spacings of element 128.3 two opposite sides surpass 10mm, and maximum can allow spacing to follow the quality of the material of use, layer thickness, cmp that relation is all arranged.

Can only provide empty interposed structure on one side of structure 121.3.

If the dielectric layer 113 above element 128.3 is thick inadequately, so that required isolation can't be provided, then can structurally deposit another layer insulating (not drawing), this one deck has the substantive smooth upper surface of comparison, because the dielectric layer of below 113 has more smooth structure through after the cmp.

Gate insulation layer 1810 and gate insulation layer 4410 are not necessarily formed by same insulating barrier, can use different insulating barriers, especially work as us and want to allow electric crystal 121.2 and 121.3 that the gate insulation layer of different-thickness is arranged.

Provide one below with reference to processing procedure: according to each one demand treatment substrate 905 (as forming complementary metal oxide semiconductor (complementary metal oxide semiconductor, CMOS) well, but the present invention is not limited only to complementary metal oxide semiconductor), form then insulating barrier 4410 or 1810 and other the layer, deposition and patterning 128,520,720 each layers, depositing insulating layer 113 then, and, can form other layer or steps of mixing certainly some stage in processing procedure with the chemical mechanical milling method processing.

Deposition polysilicon layer 128 and 520 can utilize the technology of chemical vapour deposition technique, sputtering method or other known the unknowns.Can use single shade patterning 720 and 520 layers simultaneously, also can after forming 128 layers, just form 1810 layers.

In Figure 53, empty interposed structure 141 is to use polysilicon layer 128, the integrated circuit of Figure 53 comprises a fast-flash memory array 901, silicon layer 124 is as the floating gate of memory cell, polysilicon layer 128 is as control sluice, polysilicon layer 520 is gate alternatively, insulating barrier 108 (" tunnel oxide ") is to be formed by silicon, enough thickness is arranged so that suitable data memory to be provided, in certain embodiments, oxide layer 108 thick 9nm select electric crystal gate pole oxidation layer 1810 thick 5nm, the material of mentioning here and thickness only the confession explanation with but not be used for limiting the present invention.

The bit line of memory cell zone 134 is connected with top bit line (not drawing), and it stretches to the direction of bit line " BL ", and the direction of character line is stretched in source electrode line zone 144, and is vertical with the bit line.

Wherein neighboring area 1603 comprises active area 4402,4404,4406 (shown in Figure 53), form electric crystal in it, high voltage active area 4402 is to use for the electric crystal that is arranged in high voltage environment, electric crystal then is used to erase and the memory cell of the array 901 that stylizes, this regional electric crystal gate is formed by 128 on polysilicon layer, and gate insulation layer 4408 is silicon layers of thick about 20nm.

High-speed region 4404 comprises the electric crystal with thin gate pole oxidation layer 4410, under low-voltage, operate, oxide layer 4410 thick 3.5nm, electric crystal gate be by 128 layers form.

I/O active area 4406 is for using as the electric crystal that cuts off the wafer circuit interface, cutting off wafer circuit can operate under higher power supply supply voltage, so electric crystal has thicker gate pole oxidation layer, to bear this voltage, gate insulation layer is with identical as memory array 901 1810 layers of selection electric crystal gate insulation.

Label 133 is electric crystal source electrode and the drain zones in the indication zone 4402,4404,4406, field insulating layer 1010 be formed at electric crystal in the zone 4406 or other electric crystals around.

Relevant manufacturing step is summarized as follows:

On substrate 905, form the tunnel oxide 108 (Figure 54) of thick 9nm with thermal oxidation method, deposit polysilicon layer 124, silicon layer 98.1, silicon nitride layer 98.2 then in regular turn, then above memory array 901, form photoresistance shade 4501,98.2,98.1,124 each layers in the etching area 4402,4404,4406 are to expose substrate 905.

Before deposition silicon layer 98.1, first patterning polysilicon layer 124 and substrate 905 form isolated groove, fill up groove with silicon 1010.

After the etching oxide layer 108, remove photoresistance shade 4501, heating generates the oxide layer 4408 (Figure 55) of thick 19nm on substrate 905, at this moment can form very thin silicon layer 98.3 above silicon nitride layer 98.2.

Generate photoresistance shade 4601, the silicon layer 4408 in the etching area 4404 and 4406 on the substrate at memory array 901 and high-voltage region 4402 little shadows.

Remove photoresistance shade 4601 then, the oxidation wafer, the silicon layer 4410 (the 56th figure) of the thick 3.5nm of generation above the substrate 905 in zone 4404 and 4406, in this step, the thickness of the oxide layer 4408 in the zone 4402 has a little to be increased.

On wafer, deposit polysilicon layer 128 and silicon nitride layer 720 then, form photoresistance shade 1014 with the floating gate of definition (i) memory array and control sluice (ii) the electric crystal gate in the zone 4402 and 4404, the (iii) empty interposed structure 141 in the zone 4406, etching is by 720,128,98.3,98.2,98.1,4408,4410 each layers of shade overlay area, and etching will stop at polysilicon layer 124 in the memory array zone and the substrate 905 (Figure 57) in other zones.

Remove photoresistance 1014 then, when cleanup step, polysilicon layer 128 and silicon nitride layer 720 can be protected the thin gate pole oxidation layer 4410 of high-speed region 4404.

4402,4404,4406 form another photoresistance shade 4801 in the zone; there is the place of silicon nitride layer 720 can; except the zone of photoresistance shade 4801 and 720 protection of silicon nitride layer; the polysilicon layer 1124 of etched wafer and silicon layer 108 remove photoresistance shade 4801 (Figure 58) then.

124 and 128 layers expose sidewall and substrate 905 above oxidation structure generate thin silicon layer 1510 (Figure 59), deposition and anisotropic etching approach silicon nitride layer 903 then, so can form partition at electric crystal gate structure and empty interposed structure, when etching, the silicon layer 1510 that exposes because of etching silicon nitride layer 903 may be removed.

Above the exposed surface of substrate 905, generate the silicon layer 1810 (Figure 60) of thick 5nm with thermal oxidation.

Structurally deposit polysilicon layer 520, form the electric crystal gate of photoresistance shade 2501 then, the partition that anisotropic etching polysilicon layer 520 forms on electric crystal gate structure and the empty interposed structure sidewall with definition I/O zone 4406.

Remove resistance shade 2501 earlier, above the selection gate of the gate of I/O electric crystal and memory array, form photoresist layer 1710 (Figure 61), the polysilicon layer 520 in the remaining zone of etching.

The doping step that the suitable stage in processing procedure suits forms the source electrode of electric crystal and drain zone, bit line and source electrode line are regional and other doped regions.

In certain embodiments, memory cell is multistage cell element (multilevel cells, MLC), be that each memory cell can store the information that surpasses a bit, each floating gate 124 can store three or more charge energy rank, corresponds to three or more different control sluice 128 threshold voltage, sees also the United States Patent (USP) 5 of Lee in bulletin on September 4th, 1999,953,255.

The present invention is not limited to the above embodiments, the present invention not only be defined in specific erase or the mechanism that stylizes (as Fowler-Nordheim, or hot electron injects), non-flash electronic type programmable read-only memory (the electrically eraseableprogrammable read only memory that can erase is contained in the present invention, EEPROM) and other known or not the invention memories, the present invention also is not limited only to above-mentioned material, such as control sluice, selecting the material of lock and other conducting elements can be metal, the metal silicon compounds, polysilicon metal and other electric conducting materials or compound, perhaps also can comprise conductor and conductor part simultaneously, polysilicon layer as the part doping, silicon or silicon nitride also can replace with other insulating material, P type and N type conduction pattern can exchange, the present invention is not subject to any specific program step or sequence of steps, give an example, in certain embodiments, the thermal oxidation of silicon can change into chemical vapour deposition technique or other technologies deposition one deck silicon or other insulating material, in certain embodiments, dark implantation 2110 can be carried out behind etching insulating material 1010, the invention is not restricted to the silicon integrated circuit, the claim scope definition other meet the embodiment and the variation of category of the present invention.

Claims (59)

1, a kind of manufacturing comprises the method for the integrated circuit of non-volatility memorizer, and this method comprises at least:

(a) form a ground floor on semiconductor region S 1, wherein this integrated circuit comprises a plurality of non-volatile memory cell unit, and each those memory cell includes a floating gate by one one-tenth of this ground floor institute shape of part;

(b) sluice gate via this ground floor forms a plurality of grooves in this semiconductor regions S1, and with those grooves of filling insulating material;

(c) form a ground floor on this semiconductor regions S1, wherein each those cell element includes one by the formed conduction lock of this second layer of part, and this floating gate of this conduction lock and those cell elements is isolated;

(d) this second layer of patterning stretches to the rectangular of a predetermined direction with formation, each this rectangular across a plurality of those grooves;

(e) remove not this ground floor of part on this semiconductor regions S1 that is covered by this ground floor, to form a plurality of first structures, it is one formed rectangular by this second layer that each those first structure comprises, and comprising this ground floor of part of this rectangular below, each those first structure has a first side wall;

(f) on this ground floor and this second layer, form one the 3rd layer, and with the processing procedure that comprises anisotropic etching remove the part the 3rd layer, what make in each those first structures forms a partition to this first side wall of small part, the wherein material of this ground floor in corresponding first structure with this of each this partition and this second layer isolation;

(g) remove the 3rd layer of part on part this semiconductor regions S1, but not exclusively remove this partition.Wherein each those cell element includes one by the formed conduction lock of the part partition on this first side wall of this first structure; And

(h) in to this semiconductor regions of small part S1, mixing alloy;

Step (g) and (h) use and to carry out wherein in the preceding single little shadow shade operation of step (g).

2, the method for claim 1, wherein before forming this second layer, this ground floor forms and is the rectangular of an angle with this predetermined direction and those grooves pass a row non-volatile memory cell unit to be same as this rectangular direction.

3, method as claimed in claim 2, the method that wherein forms this ground floor more comprises:

Shade on little this ground floor of shadow patterning, rectangular to define this of this ground floor; And

Utilize above-mentioned this shade to define those grooves.

4, the method for claim 1, wherein:

Each this first structure includes one second sidewall;

This little shadow shade processing procedure comprises deposition and little shadow patterning one shade, with on this first side wall that covers this first structure to this partition of small part, and cover one first semiconductor substrate, the zone of this first side wall lock of adjacent this first structure; And

This step (h) is contained in the second semiconductor substrate zone between this second sidewall of adjacent this first structure and mixes alloy.

5, method as claimed in claim 4, wherein:

Each this second semiconductor substrate zone extends between two adjacent these first structures, and the source/drain areas of all memory cells between two adjacent these first structures of bound fraction is provided, and wherein this source/drain areas is electrically connected to each other.

6, method as claimed in claim 4 more comprises and uses this shade to remove insulating material in the groove that depends on this second semiconductor substrate zone with etching wholly or in part.

7, method as claimed in claim 6 is removed in this groove after the insulating material in etching wholly or in part, more comprises removing this shade, and mix alloy in this first and second semiconductor substrates zone.

8, the method for claim 1, wherein this ground floor comprises a polysilicon layer, this second layer comprises a polysilicon layer and a metal silicon compounds layer.

9, the method for claim 1, wherein:

Before forming this second layer, this ground floor has a plurality of oblong openings, but the zone that will form source electrode line is then by this ground floor covering;

The formation of this groove is to form from this semiconductor regions of the downward etching of this oblong openings S1; And

Step (e) comprises on this source electrode line zone and removes this ground floor.

10, a kind of manufacturing comprises the method for the integrated circuit of non-volatility memorizer, and this method comprises:

(a) above semiconductor region S 1, form an insulating barrier;

(b) form a plurality of rectangularly by the formed conduction of one first material first on this insulating barrier, it will form floating gate, this first rectangular first direction that stretches to;

(c) form a plurality of grooves in this semiconductor regions S1, each those groove extends by formed adjacent this first rectangular lock of this first material, and this groove comprises an insulating material;

(d) form an insulating barrier in this first rectangular going up;

(e) form one second material, it will form conduction memory body gate, and wherein this second material is formed on the insulating barrier of this first material end face;

(f) form a shade on this second material, and use this second material of this mask patternization, rectangular by this second material formed one second to form, this second rectangular second direction of stretching to is with this first rectangular angle that is;

(g) remove not by part first material on the region S 1 of this second material covering, to form a plurality of first structures, each those first structure contains by this second material formed one second rectangular, and comprise by the formed floating gate of first material under this second material, each this first structure has a first side wall;

(h) the exposed sidewall top of the floating gate in this first structure and this second material forms an insulating barrier;

(i) form one the 3rd material in this first and second material top, and remove part the 3rd material with a processing procedure that comprises anisotropic etching, what make in each this first structure forms partition to the small part the first side wall;

(j) use little shadow to form a shade, this shade covers this partition on this first structure the first side wall;

(k) to comprise the selective etched processing procedure of this shade is removed the 3rd material, will not become this partition of this non-volatility memorizer conduction lock but do not remove; And

(l) mix alloy in this region S 1, wherein this alloy is stopped by this shade, can not enter in this region S 1 part.

11, a kind of manufacturing comprises the method for the integrated circuit of non-volatility memorizer, and this method comprises:

(a) on semiconductor region S 1, form a ground floor, this ground floor comprises a plurality of the first rectangular of first direction that stretch to, wherein this memory comprises a plurality of non-volatile memory cell unit, and each this memory cell has by the formed floating gate of this ground floor of part;

(b) form a plurality of grooves in this semiconductor regions S1, each those groove is positioned at the adjacent first rectangular lock and stretches to this first direction, and this groove comprises an insulating material;

(c) form a second layer on this ground floor, wherein each this cell element has by the formed conduction lock of this second layer of part, isolation between the floating of this conduction lock and this cell element, and this second layer comprises with this and first rectangularly is a plurality of second rectangular of an angle;

(d) remove not this ground floor of part on the region S 1 that is covered by this second layer, to form a plurality of first structures, it is one second rectangular that each those first structure comprises, and also comprises this ground floor of part of this second rectangular below, and each this first structure includes a first side wall;

(e) on this ground floor and ground floor, form one the 3rd layer, and with the processing procedure that comprises anisotropic etching remove the part the 3rd layer, make in each this first structure form partition to this first side wall top of small part, each this partition is isolated with the material that forms this corresponding first structure ground floor and the second layer;

(f) remove the 3rd layer, but do not remove this partition, this partition on this first side wall will provide the conduction lock of this non-volatile memory cell unit;

(g) mix alloy in this region S 1 of part, wherein the insulating material of a part of P1 contacts this alloy in this groove, stops this alloy to arrive a flute surfaces;

(h) afterwards, remove part or all of this insulating material part P1 from this groove in this step (g); And

(i) afterwards, in to this region S 1 of small part, mixing alloy, with the part surface at least of this groove that mixes in this step (h).

12, method as claimed in claim 11, wherein this semiconductor regions S1 is one first conduction type zone, regional P1 is electrically insulated with second conduction type of its below; And

Wherein in this step (g), doped region and this region R 1 of this alloy in this step (g) that this insulating material in this groove is avoided mixing in step (g) forms short circuit.

13, a kind of method of making integrated circuit, this method comprises:

Form one first gate insulation layer in the semiconductor substrate top that one first gold medal oxygen half electric crystal is provided, this first gold medal oxygen half electric crystal will be formed at a first area of this integrated circuit;

Form one deck L1 in this first insulating barrier top, so that a conduction lock of this first gold medal oxygen half electric crystal to be provided;

Remove this layer L1 and this first insulating barrier from a second area of this integrated circuit;

Form one second gate insulation layer above this semiconductor substrate in one second gold medal oxygen half electric crystal is provided at this second area; And

Form one deck L2 in this second insulating barrier top, so that a conduction lock of this second gold medal oxygen half electric crystal to be provided.

14, method as claimed in claim 13 is wherein different with the thickness to this second insulating barrier of small part to this first insulating barrier of small part.

15, method as claimed in claim 13, wherein:

This integrated circuit comprises and will form one the 3rd zone of one the 3rd gold medal oxygen half electric crystal;

Form this first insulating barrier and be included in the 3rd this first insulating barrier of zone formation;

Before forming this layer L1, remove this first gate insulation layer from this second and third zone, and form one the 3rd gate insulation layer in this second and third zone; And

When this second area removes this layer L1, patterning is positioned at this layer L1 in this first and the 3rd zone simultaneously, so that the conduction lock as this first and the 3rd gold medal oxygen half electric crystal to be provided.

16, method as claimed in claim 15, wherein after forming this layer L2, this first insulating barrier, this second insulating barrier, and the thickness of the 3rd insulating barrier all inequality.

17, method as claimed in claim 15, wherein when forming the 3rd insulating barrier, the thickness that is positioned at this first insulating barrier of this first area can increase.

18, method as claimed in claim 13, wherein this integrated circuit comprises a non-volatile memory cell unit, and this cell element comprises (a) by the formed conduction lock of this layer of part L1 and (b) by the formed conduction lock of this layer of part L2.

19, method as claimed in claim 18 more comprises:

Before forming this first gate insulation layer, on this semiconductor substrate that a non-volatile memory cell unit is provided, form a gate insulation layer I1, this memory cell will be formed in the regional A1 of this integrated circuit;

Before forming this first gate insulation layer, on this insulating barrier I1, form one deck L3, so that a floating gate of this memory cell to be provided; And

Before forming this first gate insulation layer, this first and second zone removes this layer L3 and this insulating barrier I1 certainly.

20, method as claimed in claim 19 more is included in this layer L3 top and forms an insulating barrier, to isolate this layer L3 and this layer L1.

21, a kind of manufacturing comprises the method for the integrated circuit of non-volatility memorizer, and this method comprises:

Form an insulating barrier 11, with gate insulation layer as non-volatile memory cell unit;

Form a ground floor, with floating gate as this cell element;

Remove this ground floor and this insulating barrier L1 in regular turn from first, second, third zone of this integrated circuit, wherein respectively this first, second, third zone in order to form the golden oxygen half electric crystal of at least one periphery;

Form one first gate insulation layer in this first, second, third zone; Remove this first gate insulation layer from this second and third zone;

Form one second gate insulation layer in this second and third zone;

Form a second layer on this ground floor, this first gate insulation layer, this second gate insulation layer, this memory cell and this gold oxygen half electric crystal that wherein are positioned at this first and the 3rd zone respectively have by the formed conduction lock of this second layer of part;

Remove this second layer from this second area;

In a zone of this second area and this memory cell, form one the 3rd gate insulation layer; And

Form one the 3rd layer, this memory cell and this gold oxygen half electric crystal that wherein are positioned at this second area respectively have by the 3rd layer of formed conduction lock of part,

This first gate insulation layer that wherein is positioned at this first area is thicker than this second gate insulation layer, and is also thick than the 3rd gate insulation layer, and the 3rd gate insulation layer is then thick than this second gate insulation layer.

22, a kind of integrated circuit comprises:

At least one non-volatile memory cell unit, it has the floating gate with the semiconductor substrate isolates, and a control sluice that is positioned at this floating gate top is arranged, and has another conduction lock; And

One first peripheral electric crystal, one second peripheral electric crystal, and one the 3rd peripheral electric crystal;

Wherein the gate insulation layer of this first peripheral electric crystal is thicker than the gate insulation layer of this second peripheral electric crystal, and the gate insulation layer of this second peripheral electric crystal is thicker than the gate insulation layer of the 3rd peripheral electric crystal.

23, a kind of manufacturing comprises the method for the non-volatility memorizer integrated circuit of a plurality of peripheral electric crystals, and this method comprises:

On one first, second, third zone of this integrated circuit, form a ground floor, wherein this memory comprises at least one memory cell, at least one the peripheral electric crystal that is positioned at this second area that is positioned at this first area, at least one the peripheral electric crystal that is positioned at the 3rd zone, and wherein this memory cell comprises a floating gate of being made up of this ground floor of part;

Remove this ground floor from this second and third zone;

Form a second layer in this first, second, third zone, wherein this memory cell comprises by the formed conduction lock of this second layer of part, and this periphery electric crystal that is positioned at this second area comprises by the formed conduction lock of this second layer of part;

Remove this second layer from the 3rd zone; And

Form one the 3rd layer in this first and the 3rd zone, wherein this memory cell comprises by to the 3rd layer of formed conduction lock of small part, and this periphery electric crystal that is positioned at the 3rd zone comprises by to the 3rd layer of formed conduction lock of small part.

24, an integrated circuit comprises:

At least one non-volatile memory cell unit, the floating gate that it has with the semiconductor substrate isolates is positioned at a control sluice of this floating gate top in addition, and a conduction lock G1 is arranged; And

One first peripheral electric crystal;

Wherein this control sluice is formed by one deck L1, and wherein a gate of this lock G1 and this first peripheral electric crystal is formed by different layers L2.

25, integrated circuit as claimed in claim 24 more comprises one second peripheral electric crystal, and it has the formed gate by this layer L1.

26, a kind of manufacturing method of integrated circuit of comprising non-volatile memory array and operating the peripheral electric crystal of this memory array, this method comprises:

On the semiconductor substrate, form a ground floor, with floating gate as this memory array;

Form a second layer on this semiconductor substrate, other but are isolated with this ground floor on this ground floor, with the conduction memory gate as this memory array;

This first and second layer meeting comes across on the region S 1 of this semiconductor substrate, this region S 1 is the place that this memory array will form, and this first and second layer can not come across on the region S 2 of this semiconductor substrate, and this region S 2 is places that a peripheral electric crystal of a peripheral circuit will form; And

Form this first and second the layer after, on this semiconductor substrate, form one the 3rd layer, with the conduction lock as this memory array, wherein each non-volatile memory cell unit of this memory array has by the formed conduction lock of this second layer with by the 3rd a layer of formed conduction lock

Wherein part comes across on this region S 2 for the 3rd layer, with the conduction lock to small part as this periphery electric crystal.

27, a kind of manufacturing comprises the method for the integrated circuit of non-volatility memorizer, and this method comprises:

On the semiconductor substrate, form a ground floor, with floating gate as this memory array;

Form a second layer on this semiconductor substrate, other but are isolated with this ground floor on this ground floor, and wherein this memory has the plural conductive lock, and each those conduction lock comprises this second layer of part;

This second layer of patterning, to form at least one structure, it comprises a second layer, an and floating gate that is positioned at this second layer below, this floating gate is formed by this ground floor, wherein this memory has a plurality of cell elements, and each those cell element comprises the conduction lock of being made up of this second layer of part, and wherein this structure includes a sidewall;

On this structure the deposition one the 3rd layer, wherein each this cell element by one by the part the 3rd layer of conduction lock of being formed, it is formed on this structure side wall;

On the 3rd layer, form a shade, and the 3rd layer of etching, with the partition on this structure side wall of formation in a zone that is not covered by this shade;

Wherein each this cell element includes one by the formed conduction lock of this partition of part;

Wherein the 3rd layer segment of this shade covering comprises a protruding extension to this partition; And

On this first, second, third layer, form an insulating barrier, and form a conductive layer, contact with this extension via the opening in this insulating barrier.

28, a kind of integrated circuit that comprises non-volatility memorizer comprises:

One structure, it comprises the lead L1 as a plurality of memory cells first conduction locks, and this structure also comprises a plurality of floating gates, and other are in nuclear lead L1 below, and insulate with this lead L1;

One lead L2, it becomes the partition on this structure side wall, and as the second conduction lock of this memory cell, each this memory cell has this first conduction lock and this second conduction lock; And

Wherein this structure, this floating gate, this lead L1 and L2 are formed on the semiconductor substrate,

Wherein this substrate comprises:

Be positioned at a plurality of grooves of its inside, and be an angle with this structure; And

One conductive region, it crosses the source/drain areas that a plurality of these conductive regions of this groove provide this memory cell along this structure.

29, a kind of manufacturing comprises the method for the integrated circuit of non-volatility memorizer, and this method comprises:

(a) formation is rectangular by first material formed a plurality of first on semiconductor region S 1, and it will form floating gate, this first rectangular first direction that stretches to;

(b) on this semiconductor regions S1, form rectangular by second material formed a plurality of second, this second rectangular second direction of stretching to, with an angle in this first direction, make this first and second rectangularly cross a plurality of zones;

(c) region S in this first and first rectangular institute region 1 forms groove, and with this groove of filling insulating material;

(d) form a material L1, it will form conduction memory gate, and wherein this material L1 is formed on this first material, and isolates with this first material;

(e) on this material L1, form a shade, and use this material of this mask patternization L1, to remove this material L1 from respectively this first rectangular end face to small part;

(f) remove this first material that is not covered by this material L1 on this region S 1, to form a plurality of first structures, each this first structure comprises first material and is positioned at the material L1 of this first material top;

(g) isolate at least one sidewall of each this first structure;

(h) on this first material and this material L1, form one the 3rd material;

(i), make and form a partition at least one sidewall of this first structure in each to comprise a processing procedure etching the 3rd material of anisotropic etching; And

(j) this region S 1 of part and top second rectangular established these region S 1 that first material has been removed above the doping,

Wherein this non-volatility memorizer comprises by the formed floating gate of this first material zone, by this material, the formed conduction lock of matter L1 zone, by the formed conduction lock of the 3rd material zone.

30, method as claimed in claim 29, wherein:

This step (b) comprises this second material of deposition, exposes this second material under this shade open bottom in formation one shade, etching on this second material; And

This step (c) comprising:

This shade being had optionally etch process etching this semiconductor regions S1 and this first material, but keep this shade, with formation groove in this first and second rectangular zone that is surrounded; And

In this groove, form insulating barrier.

31, a kind of manufacturing comprises the method for the integrated circuit of non-volatility memorizer, and this method comprises:

(a) form a ground floor on semiconductor region S 1, wherein this integrated circuit comprises a plurality of non-volatile memory cell unit, and each those cell element has by the formed floating gate of this ground floor of part;

(b) form groove from being opened in this region S 1 of this ground floor, and with this groove of filling insulating material;

(c) form a ground floor on this region S 1, wherein each this cell element has by the formed conduction lock of this second layer of part, and the floating gate of this conduction lock and this cell element is isolated;

(d) this second layer of patterning stretches to the rectangular of a predetermined direction with formation, each this rectangular across a plurality of grooves;

(e) remove not by this ground floor of part on the S1 of this second layer overlay area, to form a plurality of first structures, each this first structure comprises by this second layer formed rectangular, and this ground floor of the part of this rectangular below, and each this first structure includes a first side wall;

(f) on these first and second layers, form one the 3rd layer, and with a processing procedure that comprises anisotropic etching remove the part the 3rd layer, what make in each this first structure forms partition to the small part the first side wall, first and second layers material in corresponding first structure with this of each this partition is isolated;

(g) remove the 3rd layer of part on this region S 1 of part, but not exclusively remove this partition, wherein each this cell element comprises by the formed conduction lock of the partial sidewall on this first structure the first side wall; And

(h) in to this region S 1 of small part, mixing alloy.

32, a kind of erase the semiconductor intra-zone and above the method for fast-flash memory array memory cell, this memory array comprises plurality of sections, each this section can be erased individually, each this section has a plurality of memory cells, this method comprises:

This memory receives an instruction, indicates whether the whole memory array of will erasing, or will adopt to remove is less than whole memory array;

The whole memory array if erase, this whole memory array of then erasing; And

Be less than whole memory array if erase, this memory array of the part of then erasing, and this whole memory array of not erasing.

33, method as claimed in claim 32, this whole memory array of wherein erasing comprise provides this semiconductor regions one first voltage, and all control sluice one second voltages of this memory array are provided.

34, method as claimed in claim 32, this memory array of the part of wherein erasing comprises:

Offer control sluice one first voltage of memory cell in this part; And

Offer control sluice one second voltage of this part External Memory cell element in this memory array.

35, method as claimed in claim 32, this whole memory array of wherein erasing comprise that the Fowler-Nordheim of utilization from this cell element floating gate to the passage area that is positioned at this this cell element of semiconductor regions wears tunnel with the memory cell of erasing.

36, method as claimed in claim 32, this part memory array of wherein erasing comprise that the Fowler-Nofdheim of utilization from this cell element floating gate to the passage area that is positioned at this this cell element of semiconductor regions wears tunnel with the memory cell of erasing.

37, method as claimed in claim 32, this part memory array of wherein erasing comprise that utilization wears tunnel with the memory cell of erasing to the Fowler-Nordheim of the source/drain areas that is positioned at this this cell element of semiconductor regions between floating from this cell element.

38, a kind of manufacturing comprises the method for the integrated circuit of non-volatility memorizer, and this method comprises:

Form a ground floor on the semiconductor region S 1 of semiconductor substrate, wherein this integrated circuit comprises a plurality of memory cells, and each those memory cell comprises by the formed floating gate of this ground floor of part;

Form a second layer on this ground floor and this semiconductor regions S1, and form one deck C1 in this second layer end face, wherein each this memory cell comprises by the formed conduction lock of this second layer of part, isolation between the floating of its and this cell element;

Form one the 3rd layer, wherein each this memory cell comprises by the 3rd layer of formed conduction lock of part, and wherein a peripheral electric crystal comprises by the 3rd layer of formed conduction lock of part,

Wherein this second layer comprises near a void of this periphery electric crystal conduction lock and puts part, and the top that the 3rd layer of void is put part comprises this layer C1 of part; And this method further comprises in regular turn to form an insulating barrier on this layer C1, this ground floor, this second layer, and grinds this insulating barrier, and wherein this layer C1 is used as etching stopping layer.The part layer C1 that this second layer void is put on the part can be when this grinds processing procedure, and protection is positioned at the 3rd layer of the part of this periphery electric crystal conduction lock.

39, a kind of method of making integrated circuit, this method comprises:

Form a ground floor on the semiconductor substrate, this ground floor will can be used as to first circuit element of small part and to the void of small part and put element;

Form a second layer on this semiconductor substrate, this second layer will can be used as the second circuit element to small part;

Put on the element in this first circuit element and this void but not form on this second circuit element by one the 3rd layer of formed protection feature member;

On this first, second, third layer, form an insulating barrier in regular turn; And

Grind this insulating barrier, wherein the 3rd layer is as etching stopping layer, and so this void this protection feature member of putting element top will be ground in this and be protected this second element in processing procedure.

40, method as claimed in claim 39, wherein this void is put this protection feature member of element top in order to protect this second element not by this grinding processing procedure influence.

41, method as claimed in claim 39, wherein this void this protection feature member of putting element top is in order to protect this insulating barrier above this second element not by worn.

42, method as claimed in claim 39, wherein this ground floor is formed at before this second layer.

43, method as claimed in claim 39, wherein this second layer is formed at before this ground floor.

44, method as claimed in claim 39, wherein this second circuit element is formed at before this first circuit element.

45, method as claimed in claim 39, wherein each this first and second circuit element comprises an electric crystal gate.

46, method as claimed in claim 45, wherein this first circuit element is positioned at one first electric crystal gate insulation layer top, and this second circuit element is positioned at one second electric crystal gate insulation layer top, and this second electric crystal gate insulation layer has different thickness with this first electric crystal gate insulation layer.

47, method as claimed in claim 39, wherein the 3rd layer comprises the silicon nitride layer, and this insulating barrier comprises the silicon layer, and this grinding processing procedure comprises cmp.

48, method as claimed in claim 39, wherein this first circuit element comprises first capacitor board of an electric capacity, and this electric capacity also comprises by formed one second capacitor board of this second layer, makes to this second capacitor board of small part to be positioned at above or below this first capacitor board of small part.

49, method as claimed in claim 39, wherein this second circuit element is not overlapping with any part of this ground floor.

50, method as claimed in claim 39, wherein each this first and second circuit element is a conductive layer.

51, a kind of integrated circuit comprises:

The semiconductor substrate;

One first circuit element, it is formed on this semiconductor substrate;

One second circuit element, it is formed on this semiconductor substrate;

One void is put element, and it is near this second circuit element;

One first feature member, it is formed on this first circuit element;

One second feature member, it is formed at this void and puts on the element, and wherein this first and second feature member is formed by one first material; And

One insulating barrier, it has the upper surface of substantial planar, the material of this insulating barrier is different with this first material, this insulating barrier is positioned on this second circuit element, and fill up the zone that this second circuit element and this void are put the element lock, wherein this insulating barrier upper surface and this first and second feature member upper surface essence copline

Wherein this first material does not appear between this second circuit element upper surface and this insulating barrier upper surface.

52, integrated circuit as claimed in claim 51, wherein this first and second circuit element is formed by different materials.

53, integrated circuit as claimed in claim 51, wherein this first and second circuit element is formed by the doping polysilicon.

54, integrated circuit as claimed in claim 53, wherein the polysilicon of this first circuit element gets via different doping steps with the polysilicon of this second circuit element.

55, integrated circuit as claimed in claim 51, wherein this first and second protection feature member is formed by silicon nitride, and this insulating barrier is a silicon layer.

56, integrated circuit as claimed in claim 51; more comprise a tertiary circuit element; its be positioned at this first circuit element above or below, and be positioned at this first the protection feature member the below, this tertiary circuit element and this tertiary circuit element are formed with identical materials.

57, integrated circuit as claimed in claim 51, wherein each this first and second circuit element comprises an electric crystal gate.

58, integrated circuit as claimed in claim 57, wherein this first circuit element is positioned at one first electric crystal gate insulation layer top, and this second circuit element is positioned at one second electric crystal gate insulation layer top, and this second electric crystal gate insulation layer has different thickness with this first electric crystal gate insulation layer.

59, integrated circuit as claimed in claim 51, wherein each this first and second circuit element is a conductive layer.

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