CN103021855B - Separate gate flash memory active region manufacturing method - Google Patents
Separate gate flash memory active region manufacturing method Download PDFInfo
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- CN103021855B CN103021855B CN201110297802.XA CN201110297802A CN103021855B CN 103021855 B CN103021855 B CN 103021855B CN 201110297802 A CN201110297802 A CN 201110297802A CN 103021855 B CN103021855 B CN 103021855B
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Abstract
The invention discloses a separate gate flash memory active region manufacturing method. The manufacturing method is characterized in that a mask layer is adopted to shield an SL (sea level) region in a process of manufacturing a floating gate in a separate gate flash memory active region, so that a floating gate layer in the middle part of the SL region is not etched off, in the manner, an etching manner is adopted in the subsequent SL region to remove an oxygen-nitrogen-oxygen layer and a control grid polycrystalline silicon layer above the floating gate layer; when the floating gate layer is removed, planar etching is adopted; and the floating gate layer, the oxygen-nitrogen-oxygen layer and the control grid polycrystalline silicon layer on a silicon substrate of the SL region are all etched under the condition that the silicon substrate of the SL region is not damaged. Therefore, the method provided by the invention prevents the silicon substrate of the SL region in the separate gate flash memory active region from being damaged, the Rs resistivity of a storage unit of the active region is reduced, and finally, the manufactured separate gate flash memory device property is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly the active area manufacture method of a kind of separate gate flash memory (Split-GateFlash).
Background technology
Along with the development of semiconductor technology, there is various memory device, wherein have a kind of memory device to be separate gate flash memory.Separate gate flash memory is made up of peripheral control region and memory cell region, and wherein, memory cell region is for storing information; Peripheral control region, reads for the information stored memory cell region.
Multiple memory cell is comprised in the memory cell region of separate gate flash memory, each memory cell is made up of floating boom and control gate, source electrode line (SL is passed through in x-axis direction between memory cell, Source Line isolates, in y-axis direction by wordline (Bit-line) isolation, Fig. 1 a to Fig. 1 e shows in prior art the y-axis cross-sectional view in SL region when making memory cell, comprising:
First, as shown in Figure 1a, deposit floating gate layer 101 on a semiconductor substrate 100, photoetching and etching technics are adopted to floating gate layer 101, form floating boom on a semiconductor substrate 100, in SL region, obtain in floating boom process in etching, SL region does not adopt mask layer to block, so the floating gate layer 101 of mid portion is etched away in SL region;
In this step, floating gate layer is made up of floating gate oxide layers and floating gate polysilicon layer, and floating gate oxide layers is that 100 Izods are right, and floating gate polysilicon layer is that 1.2 thousand Izods are right;
Adopt photoetching and etching technics, the process forming floating boom is on a semiconductor substrate 100: on floating boom, apply photoresist layer, then be mask with floating gate patterns, on photoresist layer, floating gate patterns is formed after exposure and development, then there is the photoresist layer of floating gate patterns for mask, etching floating gate layer 101, forms floating boom;
Then, as shown in Figure 1 b, on exposed Semiconductor substrate 100 and floating gate layer 101 surface, after deposition oxygen nitrogen oxygen layer 102 structure, then depositional control gate polysilicon layer 103, last depositional control gate oxide 104, then deposition mask layer 105;
In this step, the thickness of oxygen nitrogen oxygen layer 102 is 170 dusts, and the thickness of control gate polysilicon layer 103 is that 2,000 Izods are right, and control gate oxide layer 104 is that 200 Izods are right;
Again, as illustrated in figure 1 c, adopt photoetching and etching technics formation control grid on floating boom, isolated between floating boom and control gate by oxygen nitrogen oxygen layer 102, at this moment, in SL region, the part of control gate polysilicon layer 103 is also by eating away in the same time;
In this step, the process of formation control grid is: lithographic mask layer 105, formation control gate pattern in mask layer 105, this control gate pattern is positioned at above formed floating boom, then there is the mask layer 105 of control gate pattern for blocking, control gate polysilicon layer 103 is etched, obtains control gate.
Again, as shown in Figure 1 d, adopt the second mask layer to block the memory cell made, then etching is continued to SL region, adopt the mode of etching to remove control gate polysilicon layer 103 and oxygen nitrogen oxygen layer 102 successively;
Finally, as shown in fig. le, the mode of etching is adopted to remove the floating gate layer 101 in SL region, in the process removed, because in SL region in fig 1 a, the floating gate layer 101 of mid portion is etched away, so the silicon substrate of mid portion can etch away in SL region, until the floating gate layer 101 in SL region is all etched, at this moment, silicon substrate damage will be caused, the degree of depth of damage is greater than the 1000 Izods right sides, is such as 170 dusts.
Vertical view when Fig. 2 is prior art making memory cell, this figure is the vertical view of Fig. 1 a, as can be seen from the figure, make in the memory unit in floating boom process, SL does not block in region, and SL region does not adopt mask layer to block, so the floating gate layer 101 of mid portion is etched away in SL region.
Silicon substrate damage is caused in SL region between memory cell, can improve the Rs resistivity of memory cell, reduces final made separate gate flash memory device performance.
Summary of the invention
In view of this, the invention provides a kind of active area manufacture method of separate gate flash memory, the method can prevent the SL region silicon substrate damage in the active area of separate gate flash memory, reduces the Rs resistivity of the memory cell of active area.
Technical scheme of the present invention is achieved in that
An active area manufacture method for separate gate flash memory, the method comprises:
The Semiconductor substrate provided deposits floating gate layer, and adopt photoetching and etching technics to form floating boom to floating gate layer, in source electrode line SL region, obtain in floating boom process in etching, SL region adopts the first mask layer to block, and the floating gate layer in SL region is not etched away;
On exposed Semiconductor substrate and floating gate layer surface, after depositing oxygen nitrogen oxygen layer, control gate polysilicon layer, control gate oxide layer and the second mask layer successively, adopt photoetching and etching technics formation control grid on floating boom, by the isolation of oxygen nitrogen oxygen layer between floating boom and control gate, form memory cell, in SL region, control gate polysilicon layer also by while partial etching fall;
Adopt the second mask layer to block the memory cell made, then etching is continued to SL region, adopt the mode of etching to remove remaining control gate polysilicon layer, oxygen nitrogen oxygen layer and floating gate layer successively.
Described floating gate layer is made up of floating gate oxide layers and floating gate polysilicon layer, and floating gate oxide layers is that 100 Izods are right, and floating gate polysilicon layer is that 1.2 thousand Izods are right.
The process of described formation floating boom is: on floating boom, apply photoresist layer, is then mask with floating gate patterns, forms floating gate patterns after exposure and development on photoresist layer, and then to have the photoresist layer of floating gate patterns for mask, etching floating gate layer, forms floating boom.
Described first mask layer is photoresist layer, is formed during coating photoresist layer in described formation floating boom process.
The thickness of described oxygen nitrogen oxygen layer is 170 dusts, and the thickness of control gate polysilicon layer is 2,000 dusts, and control gate oxide layer is that 200 Izods are right.
The described process at formation control grid is: photoetching second mask layer, formation control gate pattern in mask layer, this control gate pattern is positioned at above formed floating boom, then to have the second mask layer of control gate pattern for blocking, control gate polysilicon layer is etched, obtains control gate.
As can be seen from such scheme, method provided by the invention makes in floating boom process in the active area of separate gate flash memory, mask layer is adopted to block to SL region, the floating gate layer of mid portion in SL region is not etched away, like this, the oxygen nitrogen oxygen layer above etching mode removal floating gate layer and control gate polysilicon layer is adopted in follow-up SL region, and when removing floating gate layer, it is all planar etch, in the silicon substrate situation not damaging SL region, the floating gate layer on the silicon substrate of SL region, oxygen nitrogen oxygen layer and control gate polysilicon layer are all etched.Therefore, method provided by the invention prevents the SL region silicon substrate damage in the active area of separate gate flash memory, reduces the Rs resistivity of the memory cell of active area, the separate gate flash memory device performance made by final raising.
Accompanying drawing explanation
Fig. 1 a to Fig. 1 e is the y-axis cross-sectional view in SL region when making memory cell in prior art;
Vertical view when Fig. 2 is prior art making memory cell;
Fig. 3 is the active area manufacture method flow chart of separate gate flash memory provided by the invention;
The y-axis cross-sectional view in SL region when Fig. 4 a to Fig. 4 e is the memory cell made in the present invention in the active area of separate gate flash memory;
Vertical view when Fig. 5 is making memory cell provided by the invention.
Embodiment
For making object of the present invention, technical scheme and advantage clearly understand, to develop simultaneously embodiment referring to accompanying drawing, the present invention is described in further detail.
Cause the Rs resistivity of the memory cell of separate gate flash memory too high, the reason of the separate gate flash memory device performance made by reducing finally is exactly the silicon substrate damage in the SL region of the isolated storage unit in the active area of separate gate flash memory, in order to address this problem, the present invention have modified the processing procedure of the memory cell in the active area making separate gate flash memory, namely make in floating boom process in the active area of separate gate flash memory, mask layer is adopted to block to SL region, the floating gate layer 101 of mid portion in SL region is not etched away, like this, the oxygen nitrogen oxygen layer above etching mode removal floating gate layer and control gate polysilicon layer is adopted in follow-up SL region, and when removing floating gate layer, it is all planar etch, in the silicon substrate situation not damaging SL region, by the floating gate layer on the silicon substrate of SL region, oxygen nitrogen oxygen layer and control gate polysilicon layer have all etched.
Fig. 3 is the active area manufacture method flow chart of separate gate flash memory provided by the invention, and the y-axis cross-sectional view in SL region when composition graphs 4a to Fig. 4 e shows in the present invention the memory cell made in the active area of separate gate flash memory, is described in detail:
Step 301, as shown in fig. 4 a, deposit floating gate layer 101 on a semiconductor substrate 100, photoetching and etching technics are adopted to floating gate layer 101, form floating boom on a semiconductor substrate 100, in SL region, obtain in floating boom process in etching, SL region adopts the first mask layer to block, and in SL region, the floating gate layer 101 of mid portion is not etched away;
In this step, floating gate layer is made up of floating gate oxide layers and floating gate polysilicon layer, and floating gate oxide layers is that 100 Izods are right, and floating gate polysilicon layer is that 1.2 thousand Izods are right;
Adopt photoetching and etching technics, the process forming floating boom is on a semiconductor substrate 100: on floating boom, apply photoresist layer, then be mask with floating gate patterns, on photoresist layer, floating gate patterns is formed after exposure and development, then there is the photoresist layer of floating gate patterns for mask, etching floating gate layer 101, forms floating boom;
In this step, floating gate patterns does not cover SL region, and namely SL region is in etching floating boom process, and photoresist layer shelters from SL region as the first mask layer, and the floating gate layer 101 in SL region is not etched away, and is still a plane;
Step 302, as shown in Figure 4 b, on exposed Semiconductor substrate 100 and floating gate layer 101 surface, after deposition oxygen nitrogen oxygen layer 102 structure, then depositional control gate polysilicon layer 103, last depositional control gate oxide 104, then deposits the second mask layer 105;
In this step, the thickness of oxygen nitrogen oxygen layer 102 is 170 dusts, and the thickness of control gate polysilicon layer 103 is that 2,000 Izods are right, and control gate oxide layer 104 is that 200 Izods are right;
Step 303, as illustrated in fig. 4 c, is adopted photoetching and etching technics formation control grid on floating boom, is isolated between floating boom and control gate by oxygen nitrogen oxygen layer 102, and at this moment, in SL region, the part of control gate polysilicon layer 103 is also by eating away in the same time;
In this step, the process of formation control grid is: photoetching second mask layer 105, formation control gate pattern in mask layer 105, this control gate pattern is positioned at above formed floating boom, then there is the second mask layer 105 of control gate pattern for blocking, control gate polysilicon layer 103 is etched, obtains control gate;
In this step, in SL region, the part control gate polysilicon layer 103 that silicon substrate deposited successively floating gate layer 101, oxygen nitrogen oxygen layer 102 and be not etched completely away;
Step 304, as shown in figure 4d, adopts the second mask layer to block the memory cell made, and then continues etching to SL region, adopts the mode of etching to remove control gate polysilicon layer 103 and oxygen nitrogen oxygen layer 102 successively;
Step 305, as shown in fig 4e, adopts the mode of etching to remove the floating gate layer 101 in SL region, obtains the SL region not having silicon substrate damage.
Vertical view when Fig. 5 is making memory cell provided by the invention, this figure is the vertical view of Fig. 4 a, as can be seen from the figure, make in floating boom process in the memory unit, SL region is blocked, SL region adopts mask layer to block, so the floating gate layer 101 of mid portion is not etched away in SL region, be still a plane, so in follow-up employing etching technics removal process, also each local etching of SL region surface can not be caused uneven, SL region can not be caused to damage.
The foregoing is only preferred embodiment of the present invention, not in order to limit the present invention, within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (6)
1. an active area manufacture method for separate gate flash memory, it is characterized in that, the method comprises:
The Semiconductor substrate provided deposits floating gate layer, and adopt photoetching and etching technics to form floating boom to floating gate layer, in source electrode line SL region, obtain in floating boom process in etching, SL region adopts the first mask layer to block, and the floating gate layer in SL region is not etched away;
On exposed Semiconductor substrate and floating gate layer surface, after depositing oxygen nitrogen oxygen layer, control gate polysilicon layer, control gate oxide layer and the second mask layer successively, adopt photoetching and etching technics formation control grid on floating boom, by the isolation of oxygen nitrogen oxygen layer between floating boom and control gate, form memory cell, in SL region, control gate polysilicon layer also by while partial etching fall;
Adopt the second mask layer to block the memory cell made, then etching is continued to SL region, adopt the mode of etching to remove remaining control gate polysilicon layer, oxygen nitrogen oxygen layer and floating gate layer successively.
2. the method for claim 1, is characterized in that, described floating gate layer is made up of floating gate oxide layers and floating gate polysilicon layer, and floating gate oxide layers is 100 dusts, and floating gate polysilicon layer is 1.2 thousand dusts.
3. the method for claim 1, it is characterized in that, the process of described formation floating boom is: on floating boom, apply photoresist layer, then be mask with floating gate patterns, on photoresist layer, floating gate patterns is formed after exposure and development, then to have the photoresist layer of floating gate patterns for mask, etching floating gate layer, forms floating boom.
4. method as claimed in claim 3, it is characterized in that, described first mask layer is photoresist layer, is formed during coating photoresist layer in described formation floating boom process.
5. the method for claim 1, is characterized in that, the thickness of described oxygen nitrogen oxygen layer is 170 dusts, and the thickness of control gate polysilicon layer is 2,000 dusts, and control gate oxide layer is 200 dusts.
6. the method for claim 1, it is characterized in that, the process of described formation control grid is: photoetching second mask layer, formation control gate pattern in mask layer, this control gate pattern is positioned at above formed floating boom, then there is the second mask layer of control gate pattern for blocking, control gate polysilicon layer being etched, obtains control gate.
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| CN105826178B (en) * | 2015-01-07 | 2018-11-16 | 中芯国际集成电路制造(上海)有限公司 | The manufacturing method of semiconductor devices |
| CN114784009B (en) * | 2022-06-20 | 2022-09-09 | 广州粤芯半导体技术有限公司 | Method for preparing embedded flash memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6060356A (en) * | 1998-10-19 | 2000-05-09 | Lee; William W. Y. | Method of fabricating virtual ground SSI flash EPROM cell and array |
| CN1632952A (en) * | 2001-12-31 | 2005-06-29 | 台湾茂矽电子股份有限公司 | Non-volatile memory structure and method for manufacturing same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060356A (en) * | 1998-10-19 | 2000-05-09 | Lee; William W. Y. | Method of fabricating virtual ground SSI flash EPROM cell and array |
| CN1632952A (en) * | 2001-12-31 | 2005-06-29 | 台湾茂矽电子股份有限公司 | Non-volatile memory structure and method for manufacturing same |
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