CN114784009B - Method for preparing embedded flash memory - Google Patents
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- CN114784009B CN114784009B CN202210695044.5A CN202210695044A CN114784009B CN 114784009 B CN114784009 B CN 114784009B CN 202210695044 A CN202210695044 A CN 202210695044A CN 114784009 B CN114784009 B CN 114784009B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/3115—Doping the insulating layers
- H01L21/31155—Doping the insulating layers by ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
Abstract
The invention provides a preparation method of an embedded flash memory, which is characterized in that arsenic is injected into an oxidation isolation unit uniformly distributed in an active region and an oxidation isolation region outside the active region by optimizing a layout of the embedded flash memory, so that the oxidation isolation unit in the oxidation isolation region and the oxidation isolation unit in the active region have the same etching rate in a subsequent wet process/dry process, and the oxidation isolation unit in the oxidation isolation region and the oxidation isolation unit in the active region have the same height. The invention can obviously improve the uniformity of each storage unit of the embedded flash memory, reduce the performance difference among the storage units, reduce the dispersion of the distribution of the programming or erasing of each storage unit of the embedded flash memory, effectively improve the durability of the storage units and prolong the service life of the embedded flash memory.
Description
Technical Field
The invention belongs to the field of semiconductor memory design and manufacture, and particularly relates to a preparation method of an embedded flash memory.
Background
The Flash Memory (Flash Memory) is a non-volatile Memory integrated circuit, and has the main characteristics of high working speed, small unit area, high integration level, good reliability, repeated erasing and writing for more than 10 ten thousand times, and reliable data retention for more than 10 years. FLASH basic cells are classified into N-channel FLASH memory (nFLASH) and P-channel FLASH memory (pFLASH) according to the type of carriers generating current.
In the existing preparation process of the embedded flash memory, the thickness of floating gate polysilicon is not uniform easily due to the low surface flatness of a trench isolation Structure (STI), so that the final performance of the embedded flash memory is influenced.
It should be noted that the above background description is only for the convenience of clear and complete description of the technical solutions of the present application and for the understanding of those skilled in the art. Such solutions are not considered to be known to the person skilled in the art merely because they have been set forth in the background section of the present application.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a method for manufacturing an embedded flash memory, which is used to solve the problem in the prior art that the uneven surface of the trench isolation structure results in poor thickness uniformity of the floating gate polysilicon.
In order to achieve the above objects and other related objects, the present invention provides a method for manufacturing an embedded flash memory, the method comprising: 1) providing a semiconductor structure, wherein the semiconductor structure comprises a high-voltage region, an active region and an oxidation isolation region arranged outside the active region, the active region comprises a plurality of oxidation isolation units arranged on a substrate at intervals and active units positioned between adjacent oxidation isolation units, and the oxidation isolation units comprise first isolation parts embedded in the substrate and second isolation parts connected with the first isolation parts and protruding out of the substrate; 2) forming a high-voltage gate oxide layer on the surfaces of the high-voltage region and the active region; 3) forming a photoetching pattern, wherein the photoetching pattern is provided with an injection window, and the active region and the oxidation isolation region are exposed out of the whole injection window; 4) performing arsenic implantation based on the implantation window to adjust the arsenic concentration in the active region, thereby adjusting the turn-on voltage of the embedded flash memory, wherein the oxidation isolation region and the oxidation isolation unit have the same arsenic implantation amount; 5) removing the high-voltage gate oxide layer on the surface of the active region through a wet etching process, and removing the photoetching pattern, wherein the oxidation isolation region and the second isolation part of the oxidation isolation unit have basically the same height after the wet etching process; 6) forming a tunneling gate oxide layer on the surface of the active unit, and depositing a polycrystalline silicon layer on the substrate; 7) and removing the polysilicon layer above the oxidation isolation units through a chemical mechanical polishing process to obtain polysilicon floating gate layers arranged between adjacent oxidation isolation units at intervals, wherein the polysilicon floating gate layers have basically the same thickness.
Optionally, in the polysilicon floating gate layer prepared in step 7), the difference between the thicknesses of any two polysilicon floating gate layers is less than or equal to 50 angstrom.
Optionally, the etching solution of the wet etching process in step 5) is a diluted hydrofluoric acid solution DHF.
Optionally, in the process of removing the high voltage gate oxide layer by the wet etching process in step 5), the oxide isolation region and the second isolation portion of the oxide isolation unit are removed by the same height, where the height is between 200 to 300 angstroms.
Optionally, the heights of the oxidation isolation region and the second isolation portion of the oxidation isolation unit after the wet etching process in step 5) are between 700 and 800 angstroms.
Optionally, the step 5) removing the lithography pattern includes: a) removing part of the photoetching pattern through a process of reacting oxygen with the photoresist; b) and removing the residual photoetching pattern by adopting a sulfuric acid solution.
Optionally, the thickness of the tunneling gate oxide layer is smaller than that of the high-voltage gate oxide layer.
Optionally, the first isolation portion of the oxidation isolation unit is embedded in the substrate in an inverted trapezoid shape, the second isolation portion protrudes from the substrate in a regular trapezoid shape, and the polysilicon floating gate layer is arranged between two adjacent second isolation portions in an inverted trapezoid shape.
Optionally, the method further includes a step of performing N-type ion implantation on the polysilicon floating gate layer to form an N-type doped polysilicon floating gate layer.
Optionally, a substrate contact region is further formed in the substrate under the oxide isolation region, and the substrate contact region has a distance from the active region.
As described above, the method for manufacturing an embedded flash memory of the present invention has the following beneficial effects:
the invention provides a preparation method of an embedded flash memory, which is characterized in that arsenic is injected into an oxidation isolation unit uniformly distributed in an active region and an oxidation isolation region outside the active region by optimizing an embedded flash memory layout, so that the oxidation isolation unit in the oxidation isolation region and the oxidation isolation unit in the active region have the same etching rate in a subsequent wet process/dry process, and the oxidation isolation unit in the oxidation isolation region and the oxidation isolation unit in the active region have the same height. The invention can obviously improve the uniformity of each storage unit of the embedded flash memory, reduce the performance difference among the storage units, reduce the dispersion of each storage unit of the embedded flash memory in programming or erasing (pgm/erase) distribution (distribution), effectively improve the durability of the storage unit and prolong the service life of the embedded flash memory.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is to be understood that the drawings in the following description are of some embodiments of the application only.
Fig. 1 to 4 are schematic structural diagrams showing steps of a method for manufacturing an embedded flash memory according to an embodiment of the invention, wherein fig. 2 to 4 are schematic sectional structural diagrams at a-a' position in fig. 1.
Fig. 5 to 8 are schematic structural diagrams showing steps of a method for manufacturing an embedded flash memory according to another embodiment of the present invention, wherein fig. 6 to 8 are schematic sectional structural diagrams at a-a' position in fig. 5.
Element number description: 10 active regions, 101 active cells, 102 oxidation isolation cells, 103 tunneling gate oxide layers, 104 polysilicon floating gate layers, 20 oxidation isolation regions, 201 steps, 202 and 203 substrate contact regions, 30 photoetching patterns and 40 high-voltage gate oxide layers.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be emphasized that the term "comprises/comprising" when used herein, is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.
Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments, in combination with or instead of the features of the other embodiments.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. Further, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of this application, a structure described as having a first feature "on" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
As shown in fig. 1 to 4, wherein fig. 2 to 4 are schematic cross-sectional structural diagrams at a-a' in fig. 1, the present embodiment provides a method for manufacturing an embedded flash memory, the method including the following steps:
step 1), providing a semiconductor structure, wherein the semiconductor structure comprises a high-voltage region, an active region 10 and an oxide isolation region 20 arranged outside the active region 10, the active region 10 comprises a plurality of oxide isolation units 102 arranged on a substrate at intervals and active units 101 located between adjacent oxide isolation units 102, and each oxide isolation unit 102 comprises a first isolation part embedded in the substrate and a second isolation part connected with the first isolation part and protruding out of the substrate;
and 2) forming a high-voltage gate oxide layer 40 on the high-voltage region and the surface of the active region 10.
And step 3), forming a photoetching pattern 30, wherein the photoetching pattern 30 is provided with an injection window, and the injection window exposes the active region 10.
And 4) performing arsenic implantation based on the implantation window to adjust the arsenic concentration in the active region 10, so as to adjust the turn-on voltage of the embedded flash memory, wherein the oxidation isolation region 20 and the oxidation isolation unit 102 have the same arsenic implantation amount.
And 5), removing the high-voltage gate oxide layer 40 on the surface of the active region 10 by a wet etching process, and removing the photoetching pattern 30.
Step 6), forming a tunneling gate oxide layer 103 on the surface of the active unit 101, and depositing a polysilicon layer on the substrate; 7) the polysilicon layer above the oxide isolation cells 102 is removed by a chemical mechanical polishing process to obtain polysilicon floating gate layers 104 arranged between adjacent oxide isolation cells 102 at intervals.
As shown in fig. 3, since the etching rate of the hydrofluoric acid diluted solution (DHF) to the oxidation isolation unit 102 with arsenic implantation is significantly increased when the high voltage gate oxide layer 40 is removed by the wet method after arsenic is implanted into the oxidation isolation unit 102 of the active region 10, the height of the oxidation isolation unit 102 with arsenic implantation is significantly reduced after the high voltage gate oxide layer 40 and the photolithography pattern are removed, which is about 200 angstroms lower than the peripheral oxidation isolation region 20, and a step 201 is formed between the oxidation isolation region 20 and the active region 10, as shown in fig. 3. In the subsequent chemical mechanical polishing process for forming the polysilicon floating gate layer 104, because there is a difference in height at the step 201, in order to remove the polysilicon floating gate layer 104 on the isolation layer, there is inevitably a difference in height of the polysilicon floating gate layer 104, and there is a section of the polysilicon floating gate layer 104 with a decreasing height at the boundary of the memory cell, as shown in fig. 4.
The decreasing height of the polysilicon floating gate layer 104 at the boundary of the memory cell may cause the uniformity of the memory cell to be poor, and the uniformity of the memory cell to be poor, so that the dispersion of the distribution (distribution) of the memory cells in programming or erasing (pgm/erase) of the embedded flash memory becomes large, which may adversely affect the lifetime of the memory cell.
Based on the above embodiments, as shown in fig. 5 to 8, where fig. 6 to 8 are schematic cross-sectional structures at a-a' in fig. 5, the present embodiment further provides a method for manufacturing an embedded flash memory, the method including the steps of:
as shown in fig. 5 and 6, step 1) is performed first, providing a semiconductor structure, where the semiconductor structure includes a high-voltage region, an active region 10, and an oxide isolation region 20 disposed outside the active region 10, where the active region 10 includes a plurality of oxide isolation units 102 arranged at intervals on a substrate and an active cell 101 located between adjacent oxide isolation units 102, and the oxide isolation unit 102 includes a first isolation portion embedded in the substrate and a second isolation portion connected to the first isolation portion and protruding from the substrate.
The semiconductor structure may be formed on a semiconductor substrate, which may be, for example, a silicon substrate, a germanium-silicon substrate, a silicon carbide substrate, an SOI substrate, or the like, and is not limited to the above-listed examples.
The high voltage region (not shown) may be disposed in the middle or other region of the device for performing the functions of driving the device, and therefore, it is usually necessary to prepare a high voltage gate oxide layer 40 with a larger thickness.
The upper surface of the oxide isolation region 20 is flush with the upper surface of the oxide isolation unit 102 of the active region 10, and both can be simultaneously prepared by the same process. The material of the oxide isolation regions 20 and the oxide isolation units 102 may be silicon dioxide, which may be prepared by trench etching and thermal oxygen or/and high density plasma deposition, etc.
The active region 10 may include a P-well region and the like, and a corresponding memory device, such as a floating gate flash memory device, may be formed based on the P-well region in a subsequent process. The floating gate flash memory device may include a floating gate polysilicon layer, an isolation layer on the floating gate polysilicon layer, a polysilicon gate on the isolation layer, and the like, wherein the isolation layer may include, for example, a silicon oxide layer-silicon nitride layer-silicon oxide layer stack structure.
In one embodiment, substrate contact regions 202, 203 are also formed in the substrate under the oxide isolation regions 20, the substrate contact regions 202, 203 having a spacing from the active region 10.
As shown in fig. 6, step 2) is then performed to form a high voltage gate oxide layer 40 on the surface of the high voltage region and the active region 10.
In one embodiment, the high voltage gate oxide layer 40 may be formed by, for example, a thermal oxidation process (in an oxygen or ozone environment), or the high voltage gate oxide layer 40 may be formed by a chemical vapor deposition process, and is not limited to the examples listed herein.
As shown in fig. 6, step 3) is then performed to form a lithographic pattern having an implantation window that entirely exposes the active region 10 and the oxide isolation region 20 (not shown here since the lithographic pattern exposes all of the regions shown in fig. 5 and 6); and step 4) performing arsenic (As) implantation based on the implantation window to adjust the arsenic concentration in the active region 10, thereby adjusting the turn-on voltage of the embedded flash memory, wherein the oxide isolation region 20 and the oxide isolation unit 102 have the same arsenic implantation amount. The implantation dose of the arsenic ions and the like may be adjusted according to the desired turn-on voltage Vt of the device, which is not limited herein.
As shown in fig. 5 and fig. 6, the oxide isolation regions 20 and the oxide isolation units 102 are both exposed to the ion implantation region at the same time, and are not shielded by the photolithography pattern, so that they finally contain the same concentration of arsenic ions, thereby having the same etching rate in the subsequent wet etching process.
As shown in fig. 7, step 5) is then performed, the high voltage gate oxide layer 40 on the surface of the active region 10 is removed by a wet etching process, and the photolithographic pattern is removed, wherein the height of the oxide isolation region 20 and the second isolation portion of the oxide isolation unit 102 after the wet etching process is substantially the same. The substantially same height means that the heights of the oxide isolation region 20 and the second isolation portion of the oxide isolation unit 102 are consistent, but a certain height difference may exist within a process tolerance range, and such a height difference due to the process tolerance should also be included in the scope of the present invention.
In one embodiment, the etching solution of the wet etching process is a diluted hydrofluoric acid solution DHF.
In one embodiment, since the concentration of the arsenic ions contained in the isolation region 20 and the isolation unit 102 is the same, and the arsenic ions have the same etching rate in the subsequent wet etching process, the second isolation portions of the isolation region 20 and the isolation unit 102 are removed by the same height, which is between 200 to 300 angstroms, during the wet etching process for removing the high voltage gate oxide layer 40.
In one embodiment, the height of the oxide isolation region 20 and the second isolation portion of the oxide isolation unit 102 after the wet etch process is between 700-800 angstroms.
In one embodiment, removing the lithographic pattern comprises: a) removing part of the photoetching pattern through a process of reacting oxygen with the photoresist; b) and removing the residual photoetching pattern by adopting a sulfuric acid solution.
As shown in fig. 8, step 6) is finally performed to form a tunneling gate oxide layer 103 on the surface of the active unit 101, and a polysilicon layer is deposited on the substrate; and step 7) removing the polysilicon layer above the oxidation isolation unit 102 by a chemical mechanical polishing process to obtain a polysilicon floating gate layer 104 arranged between adjacent oxidation isolation units 102 at intervals, wherein the polysilicon layer above the oxidation isolation unit 102 is removed at substantially the same time due to the absence of the step 201 between the oxidation isolation area 20 and the oxidation isolation unit 102 of the embodiment, so that the polysilicon floating gate layer 104 has substantially the same thickness. The substantially same thickness means that the thickness of the polysilicon floating gate layer 104 is uniform, but there may be a certain thickness difference within a process tolerance, and such a thickness difference due to the process tolerance should also be included in the scope of the present invention.
In one embodiment, the thickness of the tunnel gate oxide layer 103 is less than the thickness of the high voltage gate oxide layer 40, so that charges in the underlying semiconductor substrate can pass through the tunnel gate oxide layer 103 to the polysilicon floating gate layer 104 at a specific voltage.
In one embodiment, polysilicon floating gate layers 104 are fabricated in which the difference in the thickness of any two of the polysilicon floating gate layers 104 is less than or equal to 50 angstroms.
In one embodiment, the first isolation portions of the oxidation isolation unit 102 are embedded in the substrate in an inverted trapezoid shape, the second isolation portions protrude from the substrate in a regular trapezoid shape, and the polysilicon floating gate layer 104 is arranged between two adjacent second isolation portions in an inverted trapezoid shape.
In one embodiment, the method further comprises the step of performing N-type ion implantation on the polysilicon floating gate layer 104 to form an N-type doped polysilicon floating gate layer 104.
According to the invention, by optimizing the embedded flash memory layout, arsenic is injected and uniformly distributed in the active region 10 and the oxidation isolation region 20 outside the active region 10, so that the oxidation isolation region 20 and the oxidation isolation unit 102 in the active region 10 have the same etching rate in the subsequent wet process/dry process, and the oxidation isolation region 20 and the oxidation isolation unit 102 in the active region 10 have the same height, therefore, the subsequent polysilicon floating gate layer 104 is not uneven in thickness due to the existence of the step 201 and the like in the chemical mechanical polishing process, and the polysilicon floating gate layer 104 with higher height consistency is obtained. The invention can obviously improve the uniformity of each storage unit of the embedded flash memory, reduce the performance difference among the storage units, reduce the dispersion of each storage unit of the embedded flash memory in programming or erasing (pgm/erase) distribution (distribution), effectively improve the durability of the storage unit and prolong the service life of the embedded flash memory.
As described above, the method for manufacturing an embedded flash memory of the present invention has the following beneficial effects:
the invention provides a preparation method of an embedded flash memory, which is characterized in that arsenic is injected into an active region 10 and an oxidation isolation region 20 outside the active region 10 by optimizing an embedded flash memory layout, so that the oxidation isolation region 20 and an oxidation isolation unit 102 in the active region 10 have the same etching rate in a subsequent wet process/dry process, and the oxidation isolation region 20 and the oxidation isolation unit 102 in the active region 10 have the same height, therefore, the thickness of a subsequent polysilicon floating gate layer 104 is not uneven due to the existence of a step 201 and the like in the chemical mechanical polishing process, and the polysilicon floating gate layer 104 with higher height consistency is obtained. The invention can obviously improve the uniformity of each storage unit of the embedded flash memory, reduce the performance difference among the storage units, reduce the dispersion of each storage unit of the embedded flash memory in programming or erasing (pgm/erase) distribution (distribution), effectively improve the durability of the storage unit and prolong the service life of the embedded flash memory.
Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A preparation method of an embedded flash memory is characterized by comprising the following steps:
1) providing a semiconductor structure, wherein the semiconductor structure comprises a high-voltage region, an active region and an oxidation isolation region arranged outside the active region, the active region comprises a plurality of oxidation isolation units arranged on a substrate at intervals and active units positioned between adjacent oxidation isolation units, and the oxidation isolation units comprise first isolation parts embedded in the substrate and second isolation parts connected with the first isolation parts and protruding out of the substrate;
2) forming a high-voltage gate oxide layer on the surfaces of the high-voltage region and the active region;
3) forming a photoetching pattern, wherein the photoetching pattern is provided with an injection window, and the active region and the oxidation isolation region are exposed out of the whole injection window;
4) performing arsenic implantation based on the implantation window to adjust the arsenic concentration in the active region, thereby adjusting the turn-on voltage of the embedded flash memory, wherein the oxide isolation region and the oxide isolation unit have the same arsenic implantation amount;
5) removing the high-voltage gate oxide layer on the surface of the active region through a wet etching process, and removing the photoetching pattern, wherein the oxidation isolation region and the second isolation part of the oxidation isolation unit have basically the same height after the wet etching process;
6) forming a tunneling gate oxide layer on the surface of the active unit, and depositing a polycrystalline silicon layer on the substrate;
7) and removing the polycrystalline silicon layer above the oxidation isolation units through a chemical mechanical polishing process to obtain polycrystalline silicon floating gate layers arranged between the adjacent oxidation isolation units at intervals, wherein the polycrystalline silicon floating gate layers have basically the same thickness, and the difference of the thicknesses of any two polycrystalline silicon floating gate layers is smaller than or equal to 50 angstrom meters.
2. The method for manufacturing an embedded flash memory according to claim 1, wherein: and 5) etching solution of the wet etching process in the step 5) is hydrofluoric acid (DHF) diluted solution.
3. The method of claim 2, wherein the flash memory further comprises: in the process of removing the high-voltage gate oxide layer by the wet etching process in the step 5), the oxidation isolation region and the second isolation part of the oxidation isolation unit are removed to the same height, and the height is between 200 and 300 angstroms.
4. The method for manufacturing an embedded flash memory according to claim 1, wherein: and 5) after the wet etching process, the heights of the oxidation isolation region and the second isolation part of the oxidation isolation unit are between 700 and 800 angstroms.
5. The method for manufacturing an embedded flash memory according to claim 1, wherein: step 5) removing the lithography pattern comprises:
a) removing part of the photoetching pattern through a process of reacting oxygen with the photoresist;
b) and removing the residual photoetching pattern by adopting a sulfuric acid solution.
6. The method for manufacturing an embedded flash memory according to claim 1, wherein: the thickness of the tunneling gate oxide layer is smaller than that of the high-voltage gate oxide layer.
7. The method for manufacturing an embedded flash memory according to claim 1, wherein: the first isolation part of the oxidation isolation unit is embedded into the substrate in an inverted trapezoid shape, the second isolation part protrudes out of the substrate in a regular trapezoid shape, and the polysilicon floating gate layer is arranged between two adjacent second isolation parts in an inverted trapezoid shape.
8. The method for manufacturing an embedded flash memory according to claim 1, wherein: and the method also comprises the step of carrying out N-type ion implantation on the polysilicon floating gate layer to form an N-type doped polysilicon floating gate layer.
9. The method for manufacturing an embedded flash memory according to claim 1, wherein: a substrate contact region is also formed in the substrate below the oxide isolation region, and the substrate contact region has a distance from the active region.
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| CN105789212A (en) * | 2014-12-24 | 2016-07-20 | 上海格易电子有限公司 | Flash memory unit and fabrication method |
| CN104900652B (en) * | 2015-04-10 | 2017-09-26 | 京东方科技集团股份有限公司 | A kind of low-temperature polycrystalline silicon transistor array base palte and preparation method thereof, display device |
| CN106206446B (en) * | 2015-05-05 | 2019-03-29 | 中芯国际集成电路制造(上海)有限公司 | The production method for being embedded in the flash memory of logic circuit |
| CN105826273B (en) * | 2016-05-11 | 2019-03-08 | 上海华虹宏力半导体制造有限公司 | Flush memory device and its manufacturing method |
| CN107479341A (en) * | 2017-09-13 | 2017-12-15 | 武汉新芯集成电路制造有限公司 | A kind of developing method for reducing etching barrier layer residual |
| CN111128700A (en) * | 2019-12-18 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Preparation method of semiconductor device and semiconductor device |
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Address after: 510700 No. 28, Fenghuang fifth road, Huangpu District, Guangzhou, Guangdong Patentee after: Yuexin Semiconductor Technology Co.,Ltd. Address before: 510700 No. 28, Fenghuang fifth road, Huangpu District, Guangzhou, Guangdong Patentee before: Guangzhou Yuexin Semiconductor Technology Co.,Ltd. |