CN110289260B - Flash memory manufacturing method, flash memory and photomask mask - Google Patents
Flash memory manufacturing method, flash memory and photomask mask Download PDFInfo
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
The invention relates to a method for manufacturing a flash memory, in the manufacturing process of the flash memory, when a CRS process is carried out, a photomask mask is used to form a groove in a first part region of each field oxide layer on a semiconductor substrate after the CRS process is carried out, and a control grid electrode of the flash memory is formed above the groove in a subsequent process, so that no groove is formed in a second part region of each field oxide layer on the semiconductor substrate except the first part region, a field oxide layer between the control grid electrodes is not etched, a dielectric layer between the subsequent grid electrodes grows flatly, DEP of the control grid electrode is also flatly, etching of the control grid electrode is easier, uniformity between the control grid electrodes is better, and performance of the flash memory is greatly improved.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a flash memory, and a photomask.
Background
In semiconductor integrated circuits, flash memories are widely used in consumer electronics products such as mobile phones and digital cameras and portable systems due to their Non-Volatile (Non-Volatile) characteristics. The non-volatile memory technology mainly includes floating gate (floating gate) technology, voltage dividing gate (split gate) technology, Silicon-Oxide-Nitride-Oxide-Silicon Oxide (SONOS) technology, and SONOS (Silicon-Oxide-Nitride-Oxide-Silicon Oxide, Silicon/Silicon Oxide/Silicon Nitride/Silicon Oxide/Silicon) type flash memory, which are widely used due to the advantages of simple process, low operating voltage, high data reliability, and easy integration into standard CMOS process.
Common flash memory structures include a gate structure consisting of both select gates and control gates. The selection grid mainly plays a role in selecting the flash memory unit, and the control grid mainly plays a role in controlling data storage. The floating gate mainly plays a role in storing charges, and the floating gate and the control gate form a stacked gate structure, wherein the stacked gate structure generally comprises a tunneling dielectric layer, the floating gate, an inter-gate dielectric layer and the control gate from bottom to top.
Typically, in a flash memory including multiple control gates, the uniformity between the control gates affects the performance of the flash memory.
The working principle of the flash memory is as follows: when the flash memory is programmed, a first voltage is applied to the drain electrode, a voltage which is larger than the first voltage is applied to the control grid electrode, the voltage on the control grid electrode is coupled to the floating grid electrode, and electrons in the drain electrode pass through the tunneling dielectric layer and enter the floating grid electrode under the driving of the voltage on the control grid electrode; and during the erasing operation, a second voltage is applied to the source electrode, the second voltage is larger than the voltage on the control grid electrode, and electrons in the floating grid electrode penetrate through the tunneling dielectric layer to enter the source electrode under the driving of the second voltage. As described above, the voltage on the floating gate is coupled to the voltage on the control gate through the intergate dielectric layer. The parameter of the voltage on the control gate coupled to the floating gate is referred to as the coupling ratio or capacitive coupling ratio Cp of the flash memory,
with the development of semiconductor device technology, the performance requirements of flash memory devices are higher and higher. However, as the integration level of the integrated circuit is continuously increased and the device size is continuously reduced, the size of the floating gate is reduced to be less than sub-micron, so that the facing area between the control gate and the floating gate is reduced, and further, the capacitive coupling ratio is too small, which seriously affects the performance of the flash memory.
To improve the device coupling ratio, the industry has been to increase the capacitance of the ONO layer by introducing a trench Oxide Etch (CRS-Cell Process Oxide Etch). Through a CRS process, the side wall of the floating gate is exposed and then covered with the ONO layer, so that the surface area of the floating gate is constant, and the ONO capacitance is increased through increasing the contact area between the ONO layer and the side wall of the floating gate. Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a flash memory formed in the prior art, and fig. 2 is a schematic layout of a photomask used in the CRS process in fig. 1, as shown in fig. 1 and fig. 2, the basic manufacturing processes of the flash memory include active region etching, shallow trench isolation filling and planarization, followed by floating gate growth and chemical mechanical planarization. The floating gate is formed and then the coupling capacitor forming process (i.e., the formation of the ONO layer) of the flash memory is performed. As shown in fig. 2, the conventional photomask layout is generally implemented by opening all flash memory regions, then etching the STI with shallow trench isolation by using an etching process to form a groove with a height H in fig. 1, and then performing a growth process of an inter-gate dielectric (generally, ONO) and a growth process of a control gate. By the method, the contact area between the ONO and the side wall of the floating gate is increased, and the capacitive coupling rate is further improved. However, referring to fig. 3 and 4, fig. 3 is a schematic diagram of a mask layout for adding control gates on the basis of fig. 2 in the prior art, and fig. 4 is a cross-sectional view along the line S3 parallel to the control gates between the control gates in the flash memory manufacturing process using the layout shown in fig. 3. Because shallow trench isolation between control gates is etched through the existing photomask layout, there is a height difference before the growth of the control gates, so that after the growth of the control gates, as shown in fig. 4, the surface may also be fluctuated, which causes difficulty in subsequent etching of the control gates, so that uniformity between the control gates is poor, that is, the uniformity between the control gates is seriously affected.
On the basis of ensuring the coupling ratio of the device, how to improve the uniformity between the control gates becomes a significant problem in the industry.
Disclosure of Invention
The invention aims to provide a manufacturing method of a flash memory, which enables the uniformity between control grid electrodes to be better and greatly improves the performance of the flash memory.
The invention provides a method for manufacturing a flash memory, which comprises the following steps: s1: providing a semiconductor substrate, forming field oxide layers on the semiconductor substrate, and isolating a plurality of active regions by the field oxide layers, wherein the upper surface of part of each field oxide layer is higher than the upper surface of the semiconductor substrate to form a field oxide boss; s2: forming a tunneling oxide layer, wherein the tunneling oxide layer covers the part between the field oxide bosses; s3: forming a first polysilicon gate layer on the tunneling oxide layer; s4: carrying out a planarization process and stopping on the first polysilicon gate layer; s5: carrying out photoetching process by using a photomask as a mask, forming a groove in the first partial area of each field oxide layer boss, and forming a control grid of the flash memory above the groove in the subsequent process; s6: forming an inter-gate dielectric layer which covers the exposed first polysilicon gate layer, the exposed field oxide layer and the bottom and the side wall of the groove; and S7: and forming a second polysilicon gate layer which covers the inter-gate dielectric layer so that the first polysilicon gate layer forms a floating gate and the second polysilicon gate layer forms a control gate.
Further, step S1 further includes the steps of: performing shallow trench etching on the oxide layer and the silicon nitride layer on the semiconductor substrate and the semiconductor substrate by using an active region photomask to form shallow trench isolation; oxidizing the bottom and the side wall of the shallow trench to form a shallow trench oxide layer; filling a field oxide layer medium in the shallow trench and carrying out planarization treatment; and removing the oxide layer and the silicon nitride layer on the semiconductor substrate.
Further, in step S2, the tunnel oxide layer covers the exposed semiconductor substrate and the portion of the field oxide layer whose surface is flush with the surface of the semiconductor substrate.
Further, in step S2, the tunnel oxide layer is formed by using a chemical vapor deposition method or a physical vapor deposition method.
Furthermore, the tunneling oxide layer is made of a low-k material.
Further, in step S3, a chemical vapor deposition method or a physical vapor deposition method is used to form the first polysilicon gate layer.
Further, in step S4, a chemical mechanical polishing process is performed to perform the planarization process.
Further, in step S5, a photolithography process is performed using the mask as a mask, and no recess is formed in a second partial region of each field oxide mesa except the first partial region.
Furthermore, the region corresponding to each field oxide boss in the photomask layout comprises a pattern region and a non-pattern region except the pattern region.
Furthermore, in the photoetching process, the photoresist on the field oxide layer boss corresponding to the pattern region is opened, and the first partial region of the field oxide layer boss corresponding to the pattern region is etched to form a groove, while the photoresist on the field oxide layer boss corresponding to the non-pattern region is not opened, and the second partial region of the field oxide layer boss corresponding to the non-pattern region is not etched.
Furthermore, in the photoetching process, the photoresist on the field oxide layer boss corresponding to the pattern area is not opened, the first partial area of the field oxide layer boss corresponding to the pattern area is etched to form a groove, the photoresist on the field oxide layer boss corresponding to the non-pattern area is opened, and the second partial area of the field oxide layer boss corresponding to the non-pattern area is not etched.
Furthermore, the pattern area is a cross pattern area, a rectangular pattern area or a square pattern area.
Further, in step S6, the intergate dielectric layer is an ONO layer.
The present invention also provides a flash memory including: the semiconductor substrate, form the field oxide on the semiconductor substrate, isolate multiple active areas by the field oxide, wherein the partial upper surface of the field oxide is higher than the upper surface of the semiconductor substrate, in order to form the boss of field oxide; the field oxide layer boss comprises a groove in a first partial area, the inter-grid dielectric layer covers the side wall and the bottom of the groove, and the inter-grid dielectric layer covers the field oxide layer boss in a second partial area except the first partial area on the field oxide layer boss.
Furthermore, the groove on the field oxide boss is a cross-shaped pattern groove, a rectangular pattern groove or a square pattern groove.
Furthermore, the flash memory is manufactured by adopting the manufacturing method of the flash memory.
The invention also provides a photomask mask applied to the CRS process in the flash memory manufacturing process, which is characterized in that the region of the photomask mask corresponding to the field oxide boss on the semiconductor substrate comprises a graphic region and a non-graphic region except the graphic region, so that after the CRS process, a groove is formed in a first partial region corresponding to the graphic region on the field oxide boss, and the field oxide boss in a second partial region corresponding to the non-graphic region on the field oxide boss is a flat surface.
Furthermore, the pattern area is a cross pattern area, a rectangular pattern area or a square pattern area.
Furthermore, in the photoetching process, the photoresist on the field oxide layer boss corresponding to the pattern area is opened, the first partial area of the field oxide layer boss corresponding to the pattern area is etched to form a groove, the photoresist on the field oxide layer boss corresponding to the non-pattern area is not opened, and the second partial area of the field oxide layer boss corresponding to the non-pattern area is not etched.
Furthermore, in the photoetching process, the photoresist on the field oxide layer boss corresponding to the graphic region is not opened, the first partial region of the field oxide layer boss corresponding to the graphic region is etched to form a groove, the photoresist on the field oxide layer boss corresponding to the non-graphic region is opened, and the second partial region of the field oxide layer boss corresponding to the non-graphic region is not etched
In the manufacturing method of the flash memory, when a CRS process is carried out in the manufacturing process of the flash memory, a photomask mask is used, so that a groove is formed in a first part region of each field oxide layer on a semiconductor substrate after the CRS process is carried out, a control grid of the flash memory is formed in a subsequent process above the groove, and no groove is formed in a second part region of each field oxide layer on the semiconductor substrate except the first part region, so that a field oxide layer between the control grids is not etched, a dielectric layer between the subsequent grids is flat in growth, DEP of the control grid is flat, etching of the control grid is easier, uniformity between the control grids is better, and performance of the flash memory is greatly improved.
Drawings
Fig. 1 is a cross-sectional view of a flash memory formed in the prior art.
Fig. 2 is a schematic diagram of a photomask layout used in the CRS process in fig. 1.
FIG. 3 is a schematic diagram of a prior art reticle layout with a control gate added to the control gate shown in FIG. 2.
Fig. 4 is a cross-sectional view along the line S3 between the control gates parallel to the control gates during the fabrication of a flash memory with the layout shown in fig. 3.
FIG. 5 is a flowchart illustrating a method for manufacturing a flash memory according to an embodiment of the present invention.
Fig. 6a-6h are schematic diagrams illustrating a manufacturing process of a flash memory according to an embodiment of the invention.
Fig. 7 is a schematic cross-sectional view of a semiconductor device formed during the CRS process using the photomask layout shown in fig. 6d, taken along dashed line S1'.
Fig. 8 is a schematic diagram of a layout of a mask used in a CRS process according to an embodiment of the present invention.
Fig. 9 is a schematic cross-sectional view of a semiconductor device formed during the CRS process using the photomask layout shown in fig. 6d, taken along dashed line S2'.
Fig. 10 is a schematic diagram of the inter-gate dielectric layer and the second polysilicon layer formed on the basis of fig. 9.
Detailed Description
The technical solutions in the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be obtained by a person skilled in the art without any inventive step based on the embodiments of the present invention, are within the scope of the present invention.
In an embodiment of the present invention, a method for manufacturing a flash memory is provided, and the method for manufacturing a flash memory includes S1: providing a semiconductor substrate, forming field oxide layers on the semiconductor substrate, and isolating a plurality of active regions by the field oxide layers, wherein the upper surface of part of each field oxide layer is higher than the upper surface of the semiconductor substrate to form a field oxide boss; s2: forming a tunneling oxide layer, wherein the tunneling oxide layer covers the part between the field oxide bosses; s3: forming a first polysilicon gate layer on the tunneling oxide layer; s4: carrying out a planarization process and stopping on the first polysilicon gate layer; s5: carrying out photoetching process by using a photomask as a mask, forming a groove in the first partial area of each field oxide layer boss, and forming a control grid of the flash memory above the groove in the subsequent process; s6: forming an inter-gate dielectric layer which covers the exposed first polysilicon gate layer, the exposed field oxide layer and the bottom and the side wall of the groove; and S7: and forming a second polysilicon gate layer which covers the inter-gate dielectric layer so that the first polysilicon gate layer forms a floating gate and the second polysilicon gate layer forms a control gate.
Referring to fig. 5, fig. 5 is a flowchart illustrating a method for manufacturing a flash memory according to an embodiment of the invention. Referring to fig. 6a to 6h, fig. 6a to 6h are schematic diagrams illustrating a manufacturing process of a flash memory according to an embodiment of the invention. As shown in fig. 5 and fig. 6a to 6h, in particular, the method for manufacturing a flash memory according to the present invention includes:
s1: providing a semiconductor substrate, forming field oxide layers on the semiconductor substrate, and isolating a plurality of active regions by the field oxide layers, wherein partial upper surfaces of the field oxide layers are higher than the upper surface of the semiconductor substrate to form field oxide bosses.
As shown in fig. 6a, a field oxide layer 110 is formed on a semiconductor substrate 100 such as a silicon substrate, and the field oxide layer 110 is typically formed using a Shallow Trench Isolation (STI) process. The field oxide layer 110 isolates a plurality of active regions 120, and a portion of the upper surface 111 of the field oxide layer 110 is higher than the upper surface 121 of the semiconductor substrate to form a field oxide mesa.
The specific step S1 further includes the following steps: performing shallow trench etching on the oxide layer and the silicon nitride layer on the semiconductor substrate 100 and the semiconductor substrate 100 by using an active region photomask to form shallow trench isolation; oxidizing the bottom and the side wall of the shallow trench to form a shallow trench oxide layer; filling a field oxide layer medium in the shallow trench and carrying out planarization treatment; and removing the oxide layer and the silicon nitride layer on the semiconductor substrate 100. So that a portion of the upper surface 111 of the field oxide layer is formed higher than the upper surface 121 of the semiconductor substrate.
S2: and forming a tunneling oxide layer which covers the part between the field oxide bosses.
A tunnel oxide layer 210 is formed on the portion of the field oxide layer above the upper surface 121 of the semiconductor substrate, as shown in fig. 6b, the tunnel oxide layer 210 covers the exposed semiconductor substrate and the portion of the field oxide layer whose surface is flush with the surface of the semiconductor substrate.
In an embodiment of the present invention, the tunnel oxide layer 210 is preferably formed by a chemical vapor deposition method or a physical vapor deposition method. Other methods known in the art may be used, and the present invention is not limited thereto.
In an embodiment of the present invention, the material of the tunnel oxide layer 210 is preferably a low-k material, such as one or more of amorphous carbon nitride, poly boron nitride, fluorosilicone glass, porous SiOCH, and porous diamond. Since the capacitance is in direct proportion to the dielectric constant of the dielectric layer, the tunneling oxide layer 210 made of a low-k material can reduce the capacitance between the floating gate formed in the subsequent process and the semiconductor substrate 100, which is beneficial to improving the capacitive coupling ratio of the flash memory.
S3: and forming a first polysilicon gate layer on the tunneling oxide layer.
As shown in fig. 6c, a first polysilicon gate layer 310 is formed on the tunnel oxide layer 210.
In an embodiment of the present invention, the first polysilicon gate layer 310 is preferably formed by chemical vapor deposition or physical vapor deposition. Other methods known in the art may be used, and the present invention is not limited thereto.
In an embodiment of the present invention, preferably, the material of the first polysilicon gate layer 310 is polysilicon. Other materials known in the art may of course be used, and the invention is not limited thereto.
S4: and carrying out a planarization process and stopping on the first polysilicon gate layer.
In an embodiment of the invention, the planarization process is performed by chemical mechanical polishing.
S5: and carrying out photoetching process by using a photomask as a mask, forming a groove in the first partial region of each field oxide boss, and forming a control grid of the flash memory above the groove in the subsequent process.
Further, in step S5, a photolithography process is performed using a mask as a mask, and no recess is formed in the second partial region of each field oxide mesa except the first partial region. More specifically, the second partial region is a region between the control gates on the field oxide boss. Specifically, please refer to fig. 6d, where fig. 6d is a layout diagram of a mask used in a CRS process according to an embodiment of the present invention. As shown in fig. 6d, the region corresponding to each field oxide mesa in the reticle layout includes a pattern region 411 and a non-pattern region 412 excluding the pattern region 411. In an embodiment of the present invention, in the photolithography and etching process, the photoresist on the field oxide layer mesa corresponding to the pattern region 411 is opened, and the first partial region of the field oxide layer mesa corresponding to the pattern region 411 is etched to form a groove, while the photoresist on the field oxide layer mesa corresponding to the non-pattern region 412 is not opened, and the second partial region of the field oxide layer mesa corresponding to the non-pattern region 412 is not etched. Alternatively, in the photolithography and etching process, the photoresist on the field oxide layer mesa corresponding to the pattern region 411 is not opened, and a first partial region of the field oxide layer mesa corresponding to the pattern region 411 is etched to form a groove, while the photoresist on the field oxide layer mesa corresponding to the non-pattern region 412 is opened, and a second partial region of the field oxide layer mesa corresponding to the non-pattern region 412 is not etched.
Referring to fig. 6c and 7, a cross-sectional view of the semiconductor device formed in the CRS process performed by the mask layout shown in fig. 6d along the dashed line S3' is shown in fig. 6c, and the field oxide layer of the semiconductor device corresponding to the non-pattern region 412 is not etched. Fig. 7 shows a schematic cross-sectional view of a semiconductor device formed in the CRS process using the mask layout shown in fig. 6d, along the dotted line S1', wherein a recess 410 is etched in the field oxide layer of the semiconductor device corresponding to the pattern region 411. A schematic cross-sectional view of the semiconductor device formed by the CRS process using the photomask layout shown in fig. 3 along the dashed line S3 is shown in fig. 7, and a schematic cross-sectional view of the semiconductor device formed by the CRS process using the photomask layout shown in fig. 3 along the dashed line S1 is also shown in fig. 7, that is, the CRS process using the photomask layout shown in fig. 3 is performed to open all flash memory regions, that is, all field oxide layers are etched to form the recess 410. That is, the photomask layout provided by the invention only forms the groove in the partial region of each field oxide layer, and the photomask layout in the prior art completely opens each field oxide layer.
In an embodiment of the present invention, the area above the recess 410 formed in each field oxide layer is used for forming a control gate in a subsequent process.
In one embodiment of the present invention, the pattern area 411 is a cross pattern area as shown in FIG. 6 d. In one embodiment of the present invention, the graphic area 411 is a rectangular graphic area as shown in FIG. 8. In an embodiment of the present invention, the pattern area 411 is a square pattern area. The recess of the field oxide layer boss corresponding to the pattern region 411 is also a cross pattern recess, a rectangular pattern recess or a square pattern recess.
S6: and forming an inter-gate dielectric layer which covers the first polysilicon gate layer, the field oxide layer and the bottom and the side wall of the groove.
Referring to fig. 6e, fig. 6e is a schematic cross-sectional view along a dashed line S1' after forming an inter-gate dielectric layer on the semiconductor device formed in the manufacturing process of the flash memory formed by the CRS process using the photomask layout shown in fig. 6d, that is, the inter-gate dielectric layer is formed on the basis of fig. 7, and as shown in fig. 6e, the inter-gate dielectric layer 510 covers the first polysilicon gate layer 310 and the bottom and the sidewall of the recess 410. Referring to fig. 6f, fig. 6f is a schematic cross-sectional view along a dashed line S3' after forming an inter-gate dielectric layer on the semiconductor device formed in the process of manufacturing the flash memory by using the mask layout shown in fig. 6d to perform the CRS process, that is, the inter-gate dielectric layer is formed on the basis of fig. 6c, and as shown in fig. 6f, the inter-gate dielectric layer 510 covers the first polysilicon gate layer 310 and the bump of the field oxide layer 110.
In an embodiment of the present invention, the inter-gate dielectric layer is an Oxide-Nitride-Oxide (ONO) layer. The ONO layer sequentially comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer from bottom to top, wherein the first silicon oxide layer is a tunneling oxide layer of the device, the silicon nitride layer is a data storage medium layer, and the second silicon oxide layer is a blocking oxide layer.
In one embodiment of the present invention, the ONO layer is deposited by a Low Pressure Chemical Vapor Deposition (LPCVD) process or Atomic Layer Deposition (ALD) process.
S7: and forming a second polysilicon gate layer which covers the inter-gate dielectric layer so that the first polysilicon gate layer forms a floating gate and the second polysilicon gate layer forms a control gate.
Referring to fig. 6g, fig. 6g is a schematic cross-sectional view along a dashed line S1' after a second polysilicon gate layer is formed on a semiconductor device formed in a CRS flash memory manufacturing process using the photomask layout shown in fig. 6d, that is, a second polysilicon gate layer 610 is formed on the basis of fig. 6 e. Referring to fig. 6h, fig. 6h is a schematic cross-sectional view of a second polysilicon gate 610 formed along the dashed line S3' after forming a second polysilicon gate 610 on the semiconductor device formed in the CRS process performed on the photomask layout shown in fig. 6 d. As shown in fig. 6h, the surface of the formed second polysilicon gate layer is flat, and the height difference between the second polysilicon gate layer is caused only after the inter-gate dielectric layer and the second polysilicon gate layer are formed on the field oxide layer as shown in fig. 6g and above the groove formed by the CRS process performed with the photomask layout as shown in fig. 6 d. In the prior art, as shown in fig. 7, the mask layout shown in fig. 6d is used to perform CRS process to open all the field oxide layers, that is, the field oxide layers between the control gates are etched away, so that there is a height difference before the growth of the control gates, as shown in fig. 6e, after the growth of the control gates, the surface is also fluctuated, as shown in fig. 6g (see also fig. 4), and the subsequent etching of the control gates is difficult, so that the uniformity of the control gates is poor. In the invention, because the field oxide layer medium between the control gates is not etched, the subsequent inter-gate medium layer growth is flat, the DEP of the control gates is also flat, and the etching of the control gates is easier, so the uniformity of the control gates is better, and the performance of the flash memory is greatly improved.
In one embodiment of the present invention, the second polysilicon gate layer 610 is formed by a Low Pressure Chemical Vapor Deposition (LPCVD) process. Or other methods known in the art, and are not limited herein.
As described in the background, the larger Cono (capacitance of inter-gate dielectric) the larger the capacitive coupling ratio α cg (control gate) when C (tunnel oxide capacitance) is constant. Here, Cono (capacitance of inter-gate dielectric) ═ 2H × L (∈/tonio) + W × L (∈/tonio) ═ L × (∈/tonio) {2H + W }. Wherein W is a width of a facing portion between the control gate and the floating gate, H is a height of a recess formed by recess oxide etching (CRS), tono is a thickness of the ONO layer, and e is a dielectric constant of the ONO layer, as shown in fig. 1; l is the width of the control gate, as shown in FIG. 6 d.
Wherein the capacitance coupling ratio α cg (control gate) Cono (capacitance of inter-gate dielectric)/Ctotal (total capacitance)
Approximately equal to Cono (capacitance of inter-gate dielectric)/C (capacitance of inter-gate dielectric + tunneling oxide layer capacitance)
That is, Cono (capacitance of inter-gate dielectric) is the capacitance between the control gate and the floating gate, and C (capacitance of tunnel oxide) is the capacitance between the floating gate and the substrate. When C (tunnel oxide capacitance) is constant, the larger Cono (capacitance of inter-gate dielectric) is, the larger the capacitive coupling ratio α cg (control gate) is. The larger the capacitive coupling ratio α cg (control gate), the stronger the ability of the voltage on the control gate to couple to the flash memory manufacturing method, and the lower the voltage to be applied to the control gate during the programming operation, thereby greatly improving the programming operation speed and efficiency of the flash memory. Similarly, during the erasing operation, the second voltage applied to the source electrode is also reduced, so that the over-erasing problem can be avoided, and the speed and efficiency of the erasing operation can be improved. As shown in the above formula, to increase Cono (capacitance of inter-gate dielectric), it is necessary to increase W, H and/or L, or decrease the distance D between the ONO layers on the sidewall of the trench, because the smaller the distance D between the ONO layers on the sidewall of the trench, i.e., the larger W, the higher the coupling ratio between the ONO layers, and the larger the capacitive coupling ratio α cg (control gate). Referring to fig. 9, fig. 9 is a schematic cross-sectional view of a semiconductor device formed in a CRS process performed by using the mask layout shown in fig. 6d, taken along a dashed line S2 ', wherein as shown in fig. 9, a width of a groove along a cross-section of a dashed line S2 ' is d1, and as shown in fig. 7, a width of a groove along a cross-section of a dashed line S1 ' is d2, wherein d2> d1, that is, for a cross-shaped pattern region shown in fig. 6d, a groove formed in a region other than the intersection region of the cross-shaped pattern region is narrower. Fig. 10 shows a schematic diagram after forming an inter-gate dielectric layer and a second polysilicon layer on the basis of fig. 9, so that the distance D between the ONO layers in the groove becomes smaller, thereby further improving Cono (capacitance of the inter-gate dielectric) on the basis of improving the uniformity of the control gate, and further increasing the flash memory coupling ratio.
In an embodiment of the present invention, there is also provided a flash memory including: the semiconductor substrate, form the field oxide on the semiconductor substrate, isolate multiple active areas by the field oxide, wherein the partial upper surface of the field oxide is higher than the upper surface of the semiconductor substrate, in order to form the boss of field oxide; the field oxide layer boss comprises a groove in a first partial area, the inter-grid dielectric layer covers the side wall and the bottom of the groove, and the inter-grid dielectric layer covers the field oxide layer boss in a second partial area except the first partial area on the field oxide layer boss.
Referring to fig. 6g, a first partial region on the field oxide mesa includes a recess 410, and an inter-gate dielectric layer 510 covers the sidewall and the bottom of the recess 410, and referring to fig. 6h, a second partial region on the field oxide mesa is flat and does not include a recess, and the inter-gate dielectric layer 510 covers the field oxide mesa.
In an embodiment of the present invention, the recess on the field oxide layer boss is a cross-shaped pattern recess, a rectangular pattern recess or a square pattern recess.
In an embodiment of the present invention, the flash memory is manufactured by the method for manufacturing a flash memory according to any one of the above embodiments.
In an embodiment of the present invention, a photomask used in a CRS process in a flash memory manufacturing process is further provided, as shown in fig. 6d and 8, a region of the photomask corresponding to a field oxide layer mesa on a semiconductor substrate includes a pattern region and a non-pattern region except the pattern region, so that after the CRS process, a groove is formed in a first partial region of the field oxide layer mesa corresponding to the pattern region, and a field oxide layer mesa in a second partial region of the field oxide layer mesa corresponding to the non-pattern region is a flat surface.
In an embodiment of the present invention, the graphic area is a cross graphic area, a rectangular graphic area, or a square graphic area.
In an embodiment of the present invention, in the photolithography and etching process, the photoresist on the field oxide layer mesa corresponding to the pattern region 411 is opened, and the first partial region of the field oxide layer mesa corresponding to the pattern region 411 is etched to form a groove, while the photoresist on the field oxide layer mesa corresponding to the non-pattern region 412 is not opened, and the second partial region of the field oxide layer mesa corresponding to the non-pattern region 412 is not etched. Alternatively, in the photolithography and etching process, the photoresist on the field oxide layer mesa corresponding to the pattern region 411 is not opened, and a first partial region of the field oxide layer mesa corresponding to the pattern region 411 is etched to form a groove, while the photoresist on the field oxide layer mesa corresponding to the non-pattern region 412 is opened, and a second partial region of the field oxide layer mesa corresponding to the non-pattern region 412 is not etched.
In summary, in the manufacturing process of the flash memory, when the CRS process is performed, the photomask mask is used to form a groove in a first partial region of each field oxide layer on the semiconductor substrate after the CRS process is performed, and the control gate of the flash memory is formed above the groove in the subsequent process, so that no groove is formed in a second partial region of each field oxide layer on the semiconductor substrate except the first partial region, so that the field oxide layer between the control gates is not etched, the subsequent inter-gate dielectric layer grows flat, the DEP of the control gate is also flat, the etching of the control gate is easier, the uniformity between the control gates is better, and the performance of the flash memory is greatly improved.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (19)
1. A method of manufacturing a flash memory, comprising:
s1: providing a semiconductor substrate, forming field oxide layers on the semiconductor substrate, and isolating a plurality of active regions by the field oxide layers, wherein the upper surface of part of each field oxide layer is higher than the upper surface of the semiconductor substrate to form a field oxide boss;
s2: forming a tunneling oxide layer, wherein the tunneling oxide layer covers the part between the field oxide bosses;
s3: forming a first polysilicon gate layer on the tunneling oxide layer;
s4: carrying out a planarization process and stopping on the first polysilicon gate layer;
s5: carrying out photoetching process by using a photomask as a mask, forming a groove in a first partial region of each field oxide layer boss, not forming a groove in a second partial region of each field oxide layer boss except the first partial region, and forming a control grid of the flash memory above the groove in the subsequent process;
s6: forming an inter-gate dielectric layer which covers the exposed first polysilicon gate layer, the exposed field oxide layer and the bottom and the side wall of the groove; and
s7: and forming a second polysilicon gate layer which covers the inter-gate dielectric layer so that the first polysilicon gate layer forms a floating gate and the second polysilicon gate layer forms a control gate.
2. The method of claim 1, wherein the step S1 further comprises the steps of: performing shallow trench etching on the oxide layer and the silicon nitride layer on the semiconductor substrate and the semiconductor substrate by using an active region photomask to form shallow trench isolation; oxidizing the bottom and the side wall of the shallow trench to form a shallow trench oxide layer; filling a field oxide layer medium in the shallow trench and carrying out planarization treatment; and removing the oxide layer and the silicon nitride layer on the semiconductor substrate.
3. The method of claim 1, wherein the tunneling oxide layer covers the exposed semiconductor substrate and the portion of the field oxide layer whose surface is flush with the surface of the semiconductor substrate in step S2.
4. The method of claim 3, wherein the tunneling oxide layer is formed in step S2 by chemical vapor deposition or physical vapor deposition.
5. The method of claim 1, wherein the tunneling oxide layer is made of a low-k material.
6. The method of claim 1, wherein the first polysilicon gate layer is formed by chemical vapor deposition or physical vapor deposition in step S3.
7. The method of claim 1, wherein the planarization process is performed by using a chemical mechanical polishing process in step S4.
8. The method of claim 1, wherein the region of the mask corresponding to each field oxide mesa comprises a pattern region and a non-pattern region except the pattern region.
9. The method of claim 8, wherein in the photolithography and etching process, the photoresist on the field oxide layer mesa corresponding to the pattern region is opened, and a first partial region of the field oxide layer mesa corresponding to the pattern region is etched to form a groove, while the photoresist on the field oxide layer mesa corresponding to the non-pattern region is not opened, and a second partial region of the field oxide layer mesa corresponding to the non-pattern region is not etched.
10. The method of claim 8, wherein in the photolithography etching process, the photoresist on the field oxide layer mesa corresponding to the pattern region is not opened, and a first partial region of the field oxide layer mesa corresponding to the pattern region is etched to form a groove, while the photoresist on the field oxide layer mesa corresponding to the non-pattern region is opened, and a second partial region of the field oxide layer mesa corresponding to the non-pattern region is not etched.
11. The method of claim 8, wherein the pattern area is a cross pattern area, a rectangular pattern area, or a square pattern area.
12. The method of claim 1, wherein the intergate dielectric layer is an ONO layer in step S6.
13. A flash memory, comprising: the semiconductor substrate, form the field oxide on the semiconductor substrate, isolate multiple active areas by the field oxide, wherein the partial upper surface of the field oxide is higher than the upper surface of the semiconductor substrate, in order to form the boss of field oxide; the field oxide layer boss comprises a groove in a first partial region, the field oxide layer boss does not comprise a groove in a second partial region except the first partial region, the inter-grid dielectric layer covers the side wall and the bottom of the groove, and the inter-grid dielectric layer covers the field oxide layer boss in the second partial region except the first partial region.
14. The flash memory of claim 13 wherein the recesses on the field oxide mesas are cross pattern recesses, rectangular pattern recesses or square pattern recesses.
15. The flash memory according to claim 13, wherein the flash memory is manufactured by the method of manufacturing a flash memory according to any one of claims 1 to 13.
16. A photomask mask applied to a CRS process in a flash memory manufacturing process is characterized in that a region of the photomask mask, which corresponds to a field oxide boss on a semiconductor substrate, comprises a graphic region and a non-graphic region except the graphic region, so that after the CRS process is carried out, a groove is formed in a first partial region, corresponding to the graphic region, of the field oxide boss, and the field oxide boss in a second partial region, corresponding to the non-graphic region, of the field oxide boss is a flat surface.
17. The reticle mask for use in a CRS process in a flash memory manufacturing process of claim 16, wherein the pattern area is a cross pattern area, a rectangular pattern area or a square pattern area.
18. The mask blank of claim 16, wherein in the photolithography etching process, the photoresist on the field oxide mesas corresponding to the pattern region is opened and etched to form a groove in a first partial region of the field oxide mesas corresponding to the pattern region, while the photoresist on the field oxide mesas corresponding to the non-pattern region is not opened and a second partial region of the field oxide mesas corresponding to the non-pattern region is not etched.
19. The mask blank of claim 16, wherein in the photolithography etching process, the photoresist on the field oxide mesas corresponding to the pattern region is not opened, and is etched to form a groove in a first partial region of the field oxide mesas corresponding to the pattern region, and the photoresist on the field oxide mesas corresponding to the non-pattern region is opened, and the second partial region of the field oxide mesas corresponding to the non-pattern region is not etched.
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| CN105845685A (en) * | 2015-01-30 | 2016-08-10 | 台湾积体电路制造股份有限公司 | Method to improve floating gate uniformity for non-volatile memory devices |
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| CN105845685A (en) * | 2015-01-30 | 2016-08-10 | 台湾积体电路制造股份有限公司 | Method to improve floating gate uniformity for non-volatile memory devices |
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