CN110289260A - Manufacturing method, flash memory and the light shield mask plate of flash memory - Google Patents
Manufacturing method, flash memory and the light shield mask plate of flash memory Download PDFInfo
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Abstract
The present invention relates to the manufacturing methods of flash memory, it is related to semiconductor integrated circuit manufacture method, in the manufacturing process of flash memory, when carrying out CRS technique, the light shield mask plate used, make to carry out one groove of formation in the first part region of each field oxide after CRS technique in semiconductor substrate, and for forming the control grid of flash memory in the subsequent process above groove, make not form groove in the second part region in addition to first part region of each field oxide in semiconductor substrate, so that the field oxygen layer between control grid is not etched, dielectric layer growth is just flat between subsequent gate, the DEP of control grid is also flat, etching for controlling grid is more easier, so the uniformity of control gate interpolar also can be more preferable, substantially increase the performance of flash memory.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacture method more particularly to a kind of manufacturing methods of flash memory, flash memory
And light shield mask plate.
Background technique
In semiconductor integrated circuit, flash memory is with electric in movement the characteristics of its non-volatile (Non-Volatile)
It is used widely in the consumer electronics products such as words, digital camera and portable system.Non-volatile holographic storage technology mainly has
Floating gate (floating gate)) technology, partial pressure grid (split gate) technology and SONOS (Silicon-Oxide-
Nitride-Oxide-Silicon, silicon-silicon oxide-silicon nitride-silica-silicon) technology, SONOS (Silicon-
Oxide-Nitride-Oxide-Silicon, silicon/silicon dioxide/silicon nitride/silicon dioxide/silicon) type flash memory is due to technique
Simply, it operates the advantages that voltage is low, data reliability is high and is readily integrated into standard CMOS process and is used widely.
Common flash memory structure includes the gate structure being made of selection gate and control two kinds of grids of grid.Wherein select
Grid primarily serves the effect of selection flash cell, and control grid primarily serves the effect of control data storage.Wherein controlling
Suspended grid is also formed between grid and substrate, suspended grid primarily serves the effect of storage charge, suspended grid and control
Grid forms stacked gate structure, and general stacked gate structure includes between tunneling medium layer, suspended grid, grid from bottom to up
Dielectric layer and control grid.
In general, including multiple control grids in a flash memory, the uniformity of control gate interpolar influences the property of flash memory
Energy.
The working principle of flash memory are as follows: in flash memory programming operation, a first voltage is added in drain electrode, and controlling
The voltage of the first voltage is applied more than on grid processed, the voltage controlled on grid is coupled to suspended grid, makes the electricity in drain electrode
Under the driving of the voltage of son on the control gate, enter suspended grid across tunneling medium layer；When erasing operation, applied on source electrode
Add a second voltage, second voltage is greater than the voltage on control grid, the electronics in suspended grid under the driving of second voltage,
Enter in source electrode across tunneling medium layer.As described above, the voltage on suspended grid is to couple control gate by dielectric layer between grid
Voltage on extremely.And it controls the voltage on grid and is coupled to the parameter of suspended grid and be known as the coupling efficiency or capacitive coupling rate of flash memory
Cp,
It is higher and higher to the performance requirement of flush memory device with the development of semiconductor device technology.However as integrated electricity
Integrated level continuous improvement, the continuous diminution of device size on road, the size of suspended grid have fallen to time micron hereinafter, making to control
Positive area between grid and suspended grid reduces, and then causes capacitive coupling rate too small, has seriously affected flash memory
Performance.
In order to improve device coupling efficiency, industry is by introducing groove oxide etching (CRS-Cell Recess Oxide
Etch increase ONO layer capacitor) to realize.By CRS technique, the side wall of suspended grid is exposed, is then covered with ONO layer, just
Can be certain in suspended grid surface area, by the contact area of increased ONO and suspended grid side wall, increase ONO capacitor.Please
Refering to fig. 1, Fig. 1 is a diagrammatic cross-section of the flash memory formed in the prior art, and Fig. 2 is the light shield version that CRS technique uses in Fig. 1
Diagram is intended to, and as depicted in figs. 1 and 2, the basic manufacture craft of flash memory is active area etching, shallow-trench isolation filling and planarization
Technique, subsequent is exactly the growth of suspended grid and chemical-mechanical planarization.Suspended grid formed after be exactly flash memory coupled capacitor
Formation process (i.e. the formation of ONO layer).Existing light shield domain as shown in Figure 2 is generally by fully open by flash memory area, so
The STI etching of shallow-trench isolation is gone down using etching technics afterwards, the groove that a height in Fig. 1 is H is formed, then again by between grid
The growth of medium (typically ONO) and the growth technique for controlling grid.ONO and suspended grid side are increased by such method
The contact area of wall, and then improve capacitive coupling rate.However, please referring to Fig. 3 and Fig. 4, Fig. 3 is in the prior art Fig. 2's
On the basis of increase control grid light shield domain schematic diagram, Fig. 4 be with domain shown in Fig. 3 make Flash-process in along control gate
The sectional drawing of the S3 line parallel with control grid between pole.Due to controlling the shallow slot between grid by existing mask domain
Isolation is etched away, so being to have difference in height before control grid growth, is caused as shown in Figure 4 after control grid growth,
Surface also can be that height rises and falls, and difficulty be caused to the subsequent etching to control grid, so the uniformity between control grid
It is poor, namely seriously affected the uniformity between control grid.
On the basis of guaranteeing device coupling efficiency, how to improve the uniformity between control grid becomes the weight that industry encounters
Big problem.
Summary of the invention
The purpose of the present invention is to provide a kind of manufacturing methods of flash memory, keep the uniformity of control gate interpolar more preferable, significantly
Improve the performance of flash memory.
The manufacturing method of flash memory provided by the invention, comprising: S1: semi-conductive substrate is provided, on a semiconductor substrate shape
At field oxide, multiple active areas are isolated by field oxide, wherein the portion of upper surface of each field oxide is served as a contrast higher than semiconductor
The upper surface at bottom, to form field oxide boss；S2: formed tunnel oxide, tunnel oxide cover field oxide boss it
Between part；S3: first layer polycrystalline silicon gate layer is formed on tunnel oxide；S4: carrying out flatening process, and stops at the
On one layer of polycrystalline silicon gate layer；S5: lithographic etch process is carried out by mask plate of a light shield, the first of each field oxide boss
A groove is formed in partial region, and for forming the control grid of flash memory in the subsequent process above groove；S6: it is formed between grid
Dielectric layer, the bottom and side wall of dielectric layer covering is exposed between grid first layer polycrystalline silicon gate layer, field oxide and groove；With
And S7: second layer polycrystalline silicon gate layer, dielectric layer between second layer polycrystalline silicon gate layer cover grid, so that first layer polysilicon are formed
Grid layer forms suspended grid, and second layer polycrystalline silicon gate layer forms control grid.
Further, step is further included in step S1: using active area light shield in the semiconductor substrate
Oxide layer and silicon nitride layer and the semiconductor substrate carry out shallow channel etching to form shallow trench isolation；To shallow channel bottom
It is aoxidized with side wall to form shallow channel oxide layer；Field oxide medium is filled in shallow channel and carries out planarization process；With
And removal is located at oxide layer and silicon nitride layer in the semiconductor substrate.
Further, the semiconductor substrate and field oxide surface that the tunnel oxide covering is exposed in step s 2
The field oxide part concordant with semiconductor substrate surface.
Further, the tunnelling is formed using the method for chemical vapor deposition or physical vapour deposition (PVD) in step s 2
Oxide layer.
Further, the material of the tunnel oxide is low-k materials.
Further, described first is formed using the method for chemical vapor deposition or physical vapour deposition (PVD) in step s3
Layer polycrystalline silicon gate layer.
Further, the flatening process is carried out using chemical mechanical grinding in step s 4.
Further, lithographic etch process is carried out by mask plate of the light shield in step s 5, in each field oxide
Groove is not formed in the second part region in addition to first part region of boss.
Further, the region that each field oxide boss is corresponded in the light shield domain includes graphics field and except institute
State the non-graphic region except graphics field.
Further, the photoetching in lithographic etch process, on the corresponding field oxygen layer boss in the graphics field
Glue is opened, and is etched in the first part region of field oxide boss corresponding with the graphics field and to form one recessed
Slot, and the photoresist on the corresponding field oxygen layer boss in the non-graphic region is not opened, it is corresponding with the non-graphic region
The second part region of field oxide boss is not etched.
Further, in lithographic etch process, the photoresist on the corresponding field oxygen layer boss in the graphics field is not
It is opened, and is etched in the first part region of field oxide boss corresponding with the graphics field and forms a groove,
And the photoresist on the corresponding field oxygen layer boss in the non-graphic region is opened, field oxidation corresponding with the non-graphic region
The second part region of layer boss is not etched.
Further, the graphics field is cruciform pattern region, rectangular pattern region or square-shaped patterns area
Domain.
Further, dielectric layer is ONO layer between the grid in step s 6.
The present invention also provides a kind of flash memories, comprising: and semiconductor substrate forms field oxide on a semiconductor substrate,
Multiple active areas are isolated by field oxide, wherein the portion of upper surface of field oxide is higher than the upper surface of semiconductor substrate, with
Form field oxide boss；It and on a semiconductor substrate from the bottom to top further include between tunnel oxide, first layer polysilicon layer, grid
Dielectric layer and second layer polysilicon layer wherein include a groove, medium between grid in the first part region on field oxide boss
The side wall of layer covering groove and bottom, and the second part region in addition to first part region on field oxide boss
Interior, dielectric layer covers field oxide boss between grid.
Further, the groove on the field oxide boss be cruciform pattern groove, rectangle diagram connected in star or
Square-shaped patterns groove.
Further, it is made the flash memory using the manufacturing method of any of the above-described flash memory.
The present invention also provides a kind of light shield mask plates applied to CRS technique during flash memory fabrication, which is characterized in that light
It includes graphics field and non-in addition to graphics field that cover mask plate, which corresponds to the region of the field oxide boss in semiconductor substrate,
Graphics field, so that after CRS technique, shape in first part corresponding with the graphics field region on field oxide boss
Field oxide boss in second part region corresponding with the non-graphic region at a groove, and on field oxide boss
For flat surfaces.
Further, the graphics field is cruciform pattern region, rectangular pattern region or square-shaped patterns area
Domain.
Further, the photoresist quilt in lithographic etch process, on the corresponding field oxygen layer boss in the graphics field
It opens, and is etched in the first part region of field oxide boss corresponding with the graphics field and forms a groove, and
Photoresist on the corresponding field oxygen layer boss in the non-graphic region is not opened, field oxidation corresponding with the non-graphic region
The second part region of layer boss is not etched.
Further, in lithographic etch process, the photoresist on the corresponding field oxygen layer boss in the graphics field is not
It is opened, and is etched in the first part region of field oxide boss corresponding with the graphics field and forms a groove,
And the photoresist on the corresponding field oxygen layer boss in the non-graphic region is opened, field oxidation corresponding with the non-graphic region
The second part region of layer boss is not etched
The manufacturing method of flash memory provided by the invention, in the manufacturing process of flash memory, when carrying out CRS technique, the light that uses
Cover mask plate makes to carry out one groove of formation in the first part region of each field oxide after CRS technique in semiconductor substrate, and
For forming the control grid of flash memory in the subsequent process above groove, make each field oxide in semiconductor substrate removes first
Groove is not formed in second part region except partial region, so that the field oxygen layer between control grid is not etched, after
Dielectric layer growth is just flat between continuous grid, and the DEP for controlling grid is also flat, and the etching for controlling grid is more held
Easily, so the uniformity of control gate interpolar also can be more preferable, the performance of flash memory is substantially increased.
Detailed description of the invention
Fig. 1 is a diagrammatic cross-section of the flash memory formed in the prior art.
Fig. 2 is the light shield domain schematic diagram that CRS technique uses in Fig. 1.
Fig. 3 is the light shield domain schematic diagram for increasing control grid on the basis of Fig. 2 in the prior art.
Fig. 4 is the S3 parallel with control grid made in Flash-process between control grid with domain shown in Fig. 3
The sectional drawing of line.
Fig. 5 is the manufacturing method flow chart of the flash memory of one embodiment of the invention.
Fig. 6 a-6h is the manufacturing process schematic diagram of the flash memory of one embodiment of the invention.
Fig. 7 is the semiconductor of formation during the flash memory fabrication for carrying out the formation of CRS technique with light shield domain shown in Fig. 6 d
Diagrammatic cross-section of the device along dotted line S1 '.
Fig. 8 is the light shield domain schematic diagram that the CRS technique of one embodiment of the invention uses.
Fig. 9 is the semiconductor of formation during the flash memory fabrication for carrying out the formation of CRS technique with light shield domain shown in Fig. 6 d
Diagrammatic cross-section of the device along dotted line S2 '.
Figure 10 is the schematic diagram between forming grid on the basis of Fig. 9 after dielectric layer and second layer polysilicon layer.
Specific embodiment
Below in conjunction with attached drawing, clear, complete description is carried out to the technical solution in the present invention, it is clear that described
Embodiment is a part of the embodiments of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, this field is general
Logical technical staff's all other embodiment obtained under the premise of not making creative work belongs to what the present invention protected
Range.
In an embodiment of the present invention, a kind of manufacturing method of flash memory, the manufacturing method of flash memory provided by the invention are provided
Include: S1: semi-conductive substrate being provided, field oxide is formed on a semiconductor substrate, is isolated by field oxide multiple active
Area, wherein the portion of upper surface of each field oxide is higher than the upper surface of semiconductor substrate, to form field oxide boss；S2: shape
At tunnel oxide, tunnel oxide covers the part between field oxide boss；S3: first layer is formed on tunnel oxide
Polycrystalline silicon gate layer；S4: flatening process is carried out, and is stopped on first layer polycrystalline silicon gate layer；S5: using a light shield as exposure mask
Version carries out lithographic etch process, a groove is formed in the first part region of each field oxide boss, and be used for above groove
The control grid of flash memory is formed in the subsequent process；S6: forming dielectric layer between grid, and the first layer that dielectric layer covering is exposed between grid is more
The bottom and side wall of polysilicon gate layer, field oxide and groove；And S7: second layer polycrystalline silicon gate layer, the second layer are formed
Dielectric layer between polycrystalline silicon gate layer cover grid, so that first layer polycrystalline silicon gate layer forms suspended grid, second layer polysilicon gate
Pole layer forms control grid.
Fig. 5 is seen, Fig. 5 is the manufacturing method flow chart of the flash memory of one embodiment of the invention.And Fig. 6 a-6h is please referred to,
Fig. 6 a-6h is the manufacturing process schematic diagram of the flash memory of one embodiment of the invention.As shown in Fig. 5 and Fig. 6 a-6h, specifically, this hair
The manufacturing method of the flash memory of bright offer includes:
S1: providing semi-conductive substrate, form field oxide on a semiconductor substrate, and being isolated by field oxide multiple has
Source region, wherein the portion of upper surface of each field oxide is higher than the upper surface of semiconductor substrate, to form field oxide boss.
As shown in Figure 6 a, field oxide 110 is formed in semiconductor substrate 100 such as silicon substrate, field oxide 110 is usually adopted
It is formed with shallow trench isolation (STI) technique.Field oxide 110 is isolated multiple active areas 120, on the part of another field oxide 110
Surface 111 is higher than the upper surface 121 of semiconductor substrate, forms field oxide boss.
Specific step S1 further includes following steps: the oxidation using active area light shield to being located in semiconductor substrate 100
Layer and silicon nitride layer and semiconductor substrate 100 carry out shallow channel etching to form shallow trench isolation；To shallow channel bottom and side
Wall is aoxidized to form shallow channel oxide layer；Field oxide medium is filled in shallow channel and carries out planarization process；And it goes
Except the oxide layer and silicon nitride layer being located in semiconductor substrate 100.So that the portion of upper surface 111 of the field oxide formed is higher than
The upper surface 121 of semiconductor substrate.
S2: forming tunnel oxide, and tunnel oxide covers the part between field oxide boss.
The upper surface 111 of field oxide, which is higher than on the part except the upper surface 121 of semiconductor substrate, forms tunnel oxide
Layer 210, as shown in Figure 6 b, the semiconductor substrate and field oxide surface and semiconductor substrate that the covering of tunnel oxide 210 is exposed
The field oxide part of flush.
In an embodiment of the present invention, it is preferred that tunnel is formed using chemical vapor deposition or the method for physical vapour deposition (PVD)
Wear oxide layer 210.Can certainly be using other methods known to industry, the present invention is to this and without limitation.
In an embodiment of the present invention, it is preferred that the material of tunnel oxide 210 be low-k materials, as amorphous carbon nitrogen,
One or more of polycrystalline boron nitrogen, fluorine silica glass, porous SiOCH and porous diamond.Due to the dielectric of capacitor and dielectric layer
Constant is directly proportional, and tunnel oxide 210 can reduce the suspended grid formed in subsequent technique and semiconductor substrate using low-k materials
Capacitor between 100, conducive to the capacitive coupling rate for improving flash memory.
S3: first layer polycrystalline silicon gate layer is formed on tunnel oxide.
As fig. 6 c, first layer polycrystalline silicon gate layer 310 is formed on tunnel oxide 210.
In an embodiment of the present invention, it is preferred that form the using chemical vapor deposition or the method for physical vapour deposition (PVD)
One layer of polycrystalline silicon gate layer 310.Can certainly be using other methods known to industry, the present invention is to this and without limitation.
In an embodiment of the present invention, it is preferred that the material of first layer polycrystalline silicon gate layer 310 is polysilicon.Certainly
Can be using other materials known to industry, the present invention is to this and without limitation.
S4: flatening process is carried out, and is stopped on first layer polycrystalline silicon gate layer.
In an embodiment of the present invention, the flatening process is carried out using chemical mechanical grinding.
S5: lithographic etch process is carried out by mask plate of a light shield, in the first part region of each field oxide boss
A groove is formed, and for forming the control grid of flash memory in the subsequent process above groove.
Further, in step s 5, lithographic etch process is carried out by mask plate of a light shield, it is convex in each field oxide
Groove is not formed in the second part region in addition to first part region of platform.More specifically, the second part region is
Region on field oxide boss between control gate pole.Specifically, please referring to Fig. 6 d, Fig. 6 d is one embodiment of the invention
The light shield domain schematic diagram that CRS technique uses.As shown in fig 6d, the region of each field oxide boss is corresponded in the light shield domain
Non-graphic region 412 including graphics field 411 and in addition to graphics field 411.In an embodiment of the present invention, it is carved in photoetching
In etching technique, the photoresist on the oxygen layer boss of graphics field 411 corresponding is opened, and corresponding with graphics field 411
The first part region of field oxide boss is etched and forms a groove, rather than the oxygen layer boss of graphics field 412 corresponding
On photoresist be not opened, the second part region of field oxide boss corresponding with non-graphic region 412 is not etched.It allows
So, it can also be that in lithographic etch process, the photoresist on the oxygen layer boss of graphics field 411 corresponding is not opened, and
The first part region of field oxide boss corresponding with graphics field 411 is etched and forms a groove, rather than graphics field
Photoresist on 412 corresponding oxygen layer boss is opened, and second of field oxide boss corresponding with non-graphic region 412
Subregion is not etched.
Fig. 6 c and Fig. 7 are please referred to, shape during the flash memory fabrication of CRS technique formation is carried out with light shield domain shown in Fig. 6 d
At semiconductor devices along dotted line S3 ' diagrammatic cross-section as shown in 6c, the field of the corresponding semiconductor devices in non-graphic region 412
Oxygen layer will not be etched.It is partly led with what the flash memory fabrication that light shield domain shown in Fig. 6 d carries out the formation of CRS technique was formed in the process
Body device along dotted line S1 ' diagrammatic cross-section as shown in fig. 7, the field oxygen layer of the corresponding semiconductor devices in graphics field 411 is carved
Lose groove 410 out.And the semiconductor formed during the flash memory fabrication of CRS technique formation is carried out with light shield domain shown in Fig. 3
Device along dotted line S3 line diagrammatic cross-section as shown in fig. 7, with light shield domain shown in Fig. 3 carry out the formation of CRS technique flash memory
The semiconductor devices formed in manufacturing process along dotted line S1 diagrammatic cross-section also as shown in fig. 7, i.e. with light shield version shown in Fig. 3
Figure progress CRS technique is fully open by flash memory area, i.e., each field oxide is carried out whole etchings and form groove 410.Namely
Light shield domain provided by the invention only forms groove, and light shield domain in the prior art in the partial region of each field oxide
Each field oxide is fully open.
In an embodiment of the present invention, the overlying regions of the groove 410 formed in each field oxide are in the subsequent process
It is used to form control grid.
In an embodiment of the present invention, graphics field 411 is cruciform pattern region as shown in fig 6d.In the present invention one
In embodiment, graphics field 411 is rectangular pattern region as shown in Figure 8.In an embodiment of the present invention, graphics field
411 are square graphics field.The groove of field oxide boss corresponding with graphics field 411 be also cruciform pattern groove,
Rectangle diagram connected in star or square-shaped patterns groove.
S6: dielectric layer between grid is formed, dielectric layer covers first layer polycrystalline silicon gate layer, field oxide and groove between grid
Bottom and side wall.
Fig. 6 e is please referred to, Fig. 6 e is in the flash memory fabrication process for carrying out the formation of CRS technique with light shield domain shown in Fig. 6 d
It is formed on the semiconductor devices of middle formation between grid after dielectric layer along the diagrammatic cross-section along dotted line S1 ', namely on the basis of Fig. 7
Dielectric layer between grid is formed, as shown in fig 6e, dielectric layer 510 covers first layer polycrystalline silicon gate layer 310 and groove 410 between grid
Bottom and side wall.And Fig. 6 f is please referred to, Fig. 6 f is in the flash memory fabrication for carrying out the formation of CRS technique with light shield domain shown in Fig. 6 d
It is formed on the semiconductor devices formed in the process between grid after dielectric layer along the diagrammatic cross-section along dotted line S3 ', namely Fig. 6 c's
On the basis of form dielectric layer between grid, as shown in Figure 6 f, dielectric layer 510 covers first layer polycrystalline silicon gate layer 310 and field between grid
The boss of oxide layer 110.
In an embodiment of the present invention, dielectric layer is ONO (Oxide-Nitride-Oxide, silica-between the grid
Silicon nitride-silicon dioxide) layer.ONO layer from bottom to up successively include the first silicon oxide layer, silicon nitride layer and the second silicon oxide layer,
First silicon oxide layer is the tunnel oxide of device, and silicon nitride layer is data storage medium layer, and the second silica is barrier oxidation
Layer.
In an embodiment of the present invention, using low-pressure chemical vapor deposition process (LPCVD) or atomic layer deposition (ALD) side
Formula deposits to form ONO layer.
S7: second layer polycrystalline silicon gate layer, dielectric layer between second layer polycrystalline silicon gate layer cover grid, so that first layer are formed
Polycrystalline silicon gate layer forms suspended grid, and second layer polycrystalline silicon gate layer forms control grid.
Fig. 6 g is please referred to, Fig. 6 g is in the flash memory fabrication process for carrying out the formation of CRS technique with light shield domain shown in Fig. 6 d
It is formed after second layer polycrystalline silicon gate layer along the diagrammatic cross-section along dotted line S1 ', namely schemed on the semiconductor devices of middle formation
Second layer polycrystalline silicon gate layer 610 is formed on the basis of 6e.And Fig. 6 h is please referred to, Fig. 6 h is with light shield domain shown in Fig. 6 d
It carries out after forming 610 layers of second layer polysilicon gate on the semiconductor devices formed during the flash memory fabrication of CRS technique formation
Along the diagrammatic cross-section along dotted line S3 '.As shown in figure 6h, the surface of the second layer polycrystalline silicon gate layer of formation makes flat, only
It include as with the top of the groove of the progress CRS technique formation of light shield domain shown in Fig. 6 d on field oxide as shown in figure 6g
It is formed between grid after dielectric layer and second layer polycrystalline silicon gate layer, leads to the difference in height between second layer polycrystalline silicon gate layer.And show
Have in technology, as shown in fig. 7, it is fully open to carry out CRS process field oxygen layer with light shield domain shown in Fig. 6 d, namely controls grid
Between field oxygen layer be etched away, so having difference in height before control grid growth, as shown in fig 6e, control grid is raw
After length, surface also can be that height rises and falls, and (also see Fig. 4) as shown in figure 6g, and the subsequent etching for controlling grid is that have
Difficulty, so the uniformity of control grid is poor.And in the present invention due to control grid between field oxide medium not by
It etches away, dielectric layer growth is just flat between subsequent gate, and the DEP for controlling grid is also flat, for controlling the quarter of grid
Erosion is more easier, so the uniformity of control gate also can be more preferable, substantially increases the performance of flash memory.
In an embodiment of the present invention, second layer polysilicon gate is formed using low-pressure chemical vapor deposition process (LPCVD)
Pole layer 610.Or method known to other industries, it is not limited here.
If background technique describes, when C (tunnel oxide layer capacitance) is constant, Cono (capacitor of medium between grid) is bigger, electricity
It is bigger to hold coupling efficiency α cg (control grid).Wherein, Cono (capacitor of medium between grid)=2H*L* (ε/tono)+W*L* (ε/
Tono)=L* (ε/tono) { 2H+W }.Wherein W is the width for controlling the face part between grid and suspended grid, and H is groove
The height for the groove that oxide etching (CRS) is formed, tono are the thickness of ONO layer, and ε is the dielectric constant of ONO layer, such as Fig. 1 institute
Show；L is the width for controlling grid, as shown in fig 6d.
Wherein capacitive coupling rate α cg (control grid)=Cono (capacitor of medium between grid)/Ctotal (total capacitance)
≒ Cono (capacitor of medium between grid)/C (capacitor of medium+tunnel oxide layer capacitance between grid)
That is, Cono (capacitor of medium between grid) is the capacitor controlled between grid and suspended grid, C (tunnel oxide
Capacitor) capacitor between suspended grid and substrate.When C (tunnel oxide layer capacitance) is constant, Cono (capacitor of medium between grid)
Bigger, capacitive coupling rate α cg (control grid) is bigger.Capacitive coupling rate α cg (control grid) is bigger, controls the electricity on grid
Press the ability for the manufacturing method for being coupled to flash memory stronger, when programming operation, the voltage that need to apply on the control gate will be reduced,
And then greatly promote the programming operation speed of flash memory and efficiency.Similarly, it in erasing operation, need to be applied on source electrode
The problem of second voltage will also decrease, can be to avoid over-erasure, can also improve the speed and efficiency of erasing operation.It is such as above-mentioned
Shown in formula, to increase Cono (capacitor of medium between grid), the value of W, H and/or L need to be increased, or reduce in recess sidewall
Space D between ONO layer, because the space D between the ONO layer in recess sidewall is smaller, that is, W bigger, the coupling between ONO layer
Rate is higher, and capacitive coupling rate α cg (control grid) is bigger.Referring to Fig. 9, Fig. 9 is to be carried out with light shield domain shown in Fig. 6 d
CRS technique formed flash memory fabrication during formed semiconductor devices along dotted line S2 ' diagrammatic cross-section, as shown in figure 9, edge
The width of the groove of the section of dotted line S2 ' is d1, and referring again to shown in Fig. 7, the width along the groove of the section of dotted line S1 ' is
D2, wherein d2 > d1, are for cruciform pattern region as shown in fig 6d, except the intersection region of cruciform pattern region
The groove that region is formed is relatively narrow.The schematic diagram formed between grid after dielectric layer and the second layer polysilicon layer on the basis of Fig. 9 is such as
Shown in Figure 10, so that the space D in groove between ONO layer becomes smaller, therefore on the basis of improving control grid uniformity, into one
Step improves Cono (capacitor of medium between grid), and then increases flash memory coupling efficiency.
In an embodiment of the present invention, a kind of flash memory is also provided, comprising: semiconductor substrate, on a semiconductor substrate
Field oxide is formed, multiple active areas are isolated by field oxide, wherein the portion of upper surface of field oxide is served as a contrast higher than semiconductor
The upper surface at bottom, to form field oxide boss；It and on a semiconductor substrate from the bottom to top further include tunnel oxide, first layer
Dielectric layer and second layer polysilicon layer between polysilicon layer, grid wherein include one in the first part region on field oxide boss
Groove, the side wall of dielectric layer covering groove and bottom between grid, and on field oxide boss in addition to first part region
In second part region, dielectric layer covers field oxide boss between grid.
Please referring to includes groove 410 in the first part region shown in Fig. 6 g, on field oxide boss, dielectric layer between grid
The side wall of 510 covering grooves 410 and bottom, separately please refer to shown in Fig. 6 h, and the second part region on field oxide boss is
Flat, it does not include groove, dielectric layer 510 covers field oxide boss between grid.
In an embodiment of the present invention, the groove on field oxide boss is that cruciform pattern groove, rectangular pattern are recessed
Slot or square-shaped patterns groove.
In an embodiment of the present invention, the flash memory by any of the above-described embodiment flash memory manufacturing method production and
At.
In an embodiment of the present invention, a kind of light shield mask plate applied to CRS technique during flash memory fabrication is also provided,
It sees shown in Fig. 6 d and Fig. 8, the region that light shield mask plate corresponds to the field oxide boss in semiconductor substrate includes graph area
Domain and the non-graphic region in addition to graphics field, so that after CRS technique, it is corresponding with graphics field on field oxide boss
First part region in form a groove, and second part corresponding with the non-graphic region region on field oxide boss
Interior field oxide boss is flat surfaces.
In an embodiment of the present invention, the graphics field is cruciform pattern region, rectangular pattern region or pros
Shape graphics field.
In an embodiment of the present invention, the light in lithographic etch process, on the oxygen layer boss of graphics field 411 corresponding
Photoresist is opened, and is etched in the first part region of field oxide boss corresponding with graphics field 411 and to form one recessed
Slot, rather than the photoresist on the oxygen layer boss of graphics field 412 corresponding is not opened, field corresponding with non-graphic region 412
The second part region of oxide layer boss is not etched.It allows so, can also be, in lithographic etch process, graphics field 411 is corresponding
Field oxygen layer boss on photoresist be not opened, and in the first part of field oxide boss corresponding with graphics field 411
Region is etched and forms a groove, rather than the photoresist on the oxygen layer boss of graphics field 412 corresponding is opened, with non-figure
The second part region of the corresponding field oxide boss in shape region 412 is not etched.
In conclusion when carrying out CRS technique, the light shield mask plate used makes to carry out CRS in the manufacturing process of flash memory
A groove is formed in the first part region of each field oxide after technique in semiconductor substrate, and for subsequent above groove
The control grid that flash memory is formed in technique, makes second in addition to first part region of each field oxide in semiconductor substrate
Groove is not formed in partial region, so that the field oxygen layer between control grid is not etched, dielectric layer is grown just between subsequent gate
It being flat, the DEP for controlling grid is also flat, and the etching for controlling grid is more easier, so control gate interpolar
Uniformity also can be more preferable, substantially increases the performance of flash memory.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (20)
1. a kind of manufacturing method of flash memory characterized by comprising
S1: semi-conductive substrate is provided, field oxide is formed on a semiconductor substrate, is isolated by field oxide multiple active
Area, wherein the portion of upper surface of each field oxide is higher than the upper surface of semiconductor substrate, to form field oxide boss；
S2: forming tunnel oxide, and tunnel oxide covers the part between field oxide boss；
S3: first layer polycrystalline silicon gate layer is formed on tunnel oxide；
S4: flatening process is carried out, and is stopped on first layer polycrystalline silicon gate layer；
S5: lithographic etch process is carried out by mask plate of a light shield, is formed in the first part region of each field oxide boss
One groove, and for forming the control grid of flash memory in the subsequent process above groove；
S6: forming dielectric layer between grid, first layer polycrystalline silicon gate layer, field oxide and the groove that dielectric layer covering is exposed between grid
Bottom and side wall；And
S7: second layer polycrystalline silicon gate layer, dielectric layer between second layer polycrystalline silicon gate layer cover grid, so that first layer polycrystalline are formed
Polysilicon gate layer forms suspended grid, and second layer polycrystalline silicon gate layer forms control grid.
2. the manufacturing method of flash memory according to claim 1, which is characterized in that further include step in step S1: using having
Source region light shield carries out shallow channel to the oxide layer and silicon nitride layer that are located in the semiconductor substrate and the semiconductor substrate
Etching is to form shallow trench isolation；Shallow channel bottom and side wall is aoxidized to form shallow channel oxide layer；It is filled out in shallow channel
It fills field oxide medium and carries out planarization process；And removal is located at oxide layer and silicon nitride in the semiconductor substrate
Layer.
3. the manufacturing method of flash memory according to claim 1, which is characterized in that the tunnel oxide covers in step s 2
Cover the semiconductor substrate of exposing and the field oxide part that field oxide surface is concordant with semiconductor substrate surface.
4. the manufacturing method of flash memory according to claim 3, which is characterized in that use chemical vapor deposition in step s 2
Or the method for physical vapour deposition (PVD) forms the tunnel oxide.
5. the manufacturing method of flash memory according to claim 1, which is characterized in that the material of the tunnel oxide is low k
Material.
6. the manufacturing method of flash memory according to claim 1, which is characterized in that use chemical vapor deposition in step s3
Or the method for physical vapour deposition (PVD) forms the first layer polycrystalline silicon gate layer.
7. the manufacturing method of flash memory according to claim 1, which is characterized in that use chemical mechanical grinding in step s 4
Carry out the flatening process.
8. the manufacturing method of flash memory according to claim 1, which is characterized in that in step s 5 using the light shield as exposure mask
Version carries out lithographic etch process, is not formed in the second part region in addition to first part region of each field oxide boss
Groove.
9. the manufacturing method of flash memory according to claim 8, which is characterized in that correspond to each field oxygen in the light shield domain
The region for changing layer boss includes graphics field and the non-graphic region in addition to the graphics field.
10. the manufacturing method of flash memory according to claim 9, which is characterized in that in lithographic etch process, the figure
Photoresist on the corresponding field oxygen layer boss in region is opened, and in field oxide boss corresponding with the graphics field
First part region be etched and form a groove, and the photoresist on the corresponding field oxygen layer boss in the non-graphic region is not
It is opened, the second part region of field oxide boss corresponding with the non-graphic region is not etched.
11. the manufacturing method of flash memory according to claim 9, which is characterized in that in lithographic etch process, the figure
Photoresist on the corresponding field oxygen layer boss in region is not opened, and in field oxide boss corresponding with the graphics field
First part region is etched and forms a groove, and the photoresist on the corresponding field oxygen layer boss in the non-graphic region is beaten
It opens, the second part region of field oxide boss corresponding with the non-graphic region is not etched.
12. the manufacturing method of flash memory according to claim 9, which is characterized in that the graphics field is cruciform pattern
Region, rectangular pattern region or square-shaped patterns region.
13. the manufacturing method of flash memory according to claim 1, which is characterized in that dielectric layer between the grid in step s 6
For ONO layer.
14. a kind of flash memory characterized by comprising semiconductor substrate forms field oxide on a semiconductor substrate, by
Field oxide isolates multiple active areas, and wherein the portion of upper surface of field oxide is higher than the upper surface of semiconductor substrate, with shape
At field oxide boss；It and on a semiconductor substrate from the bottom to top further include being situated between tunnel oxide, first layer polysilicon layer, grid
Matter layer and second layer polysilicon layer wherein include a groove, dielectric layer between grid in the first part region on field oxide boss
Side wall and the bottom of groove are covered, and in the second part region in addition to first part region on field oxide boss,
Dielectric layer covers field oxide boss between grid.
15. flash memory according to claim 14, which is characterized in that the groove on the field oxide boss is cross
Shape figure groove, rectangle diagram connected in star or square-shaped patterns groove.
16. flash memory according to claim 14, which is characterized in that use the described in any item sudden strains of a muscle of claim 1-13
The manufacturing method deposited is made.
17. a kind of light shield mask plate applied to CRS technique during flash memory fabrication, which is characterized in that light shield mask plate is corresponding
The region of field oxide boss in semiconductor substrate includes graphics field and the non-graphic region in addition to graphics field, so that
After CRS technique, a groove is formed in first part corresponding with the graphics field region on field oxide boss, and
Field oxide boss is flat surfaces in second part region corresponding with the non-graphic region on field oxide boss.
18. the light shield mask plate according to claim 17 applied to CRS technique during flash memory fabrication, feature exist
In the graphics field is cruciform pattern region, rectangular pattern region or square-shaped patterns region.
19. the light shield mask plate according to claim 17 applied to CRS technique during flash memory fabrication, feature exist
In, in lithographic etch process, the photoresist on the corresponding field oxygen layer boss in the graphics field is opened, and with the figure
The first part region of the corresponding field oxide boss in shape region is etched and forms a groove, and the non-graphic region is corresponding
Field oxygen layer boss on photoresist be not opened, the second part area of field oxide boss corresponding with the non-graphic region
Domain is not etched.
20. the light shield mask plate according to claim 17 applied to CRS technique during flash memory fabrication, feature exist
In, in lithographic etch process, the photoresist on the corresponding field oxygen layer boss in the graphics field is not opened, and with it is described
The first part region of the corresponding field oxide boss in graphics field is etched and forms a groove, and the non-graphic region pair
The photoresist on the oxygen layer boss of field answered is opened, the second part area of field oxide boss corresponding with the non-graphic region
Domain is not etched.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113224066A (en) * | 2021-04-28 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Flash memory device structure and manufacturing method thereof |
| CN113224064A (en) * | 2021-04-21 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Method for manufacturing flash memory device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101908509A (en) * | 2009-06-08 | 2010-12-08 | 海力士半导体有限公司 | Make the method for nonvolatile semiconductor memory member |
| CN104112654A (en) * | 2013-04-18 | 2014-10-22 | 中芯国际集成电路制造(上海)有限公司 | Process method for reducing floating gate holes |
| CN104779209A (en) * | 2014-01-13 | 2015-07-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing flash memory |
| CN105845685A (en) * | 2015-01-30 | 2016-08-10 | 台湾积体电路制造股份有限公司 | Method to improve floating gate uniformity for non-volatile memory devices |
| US20160284718A1 (en) * | 2015-03-24 | 2016-09-29 | SanDisk Technologies, Inc. | Common Source Line with Discrete Contact Plugs |
| CN108109656A (en) * | 2017-12-28 | 2018-06-01 | 上海华力微电子有限公司 | The production method and flash array of flash array |
| CN109494224A (en) * | 2017-09-08 | 2019-03-19 | 华邦电子股份有限公司 | Nonvolatile memory device and its manufacturing method |
-
2019
- 2019-06-21 CN CN201910541255.1A patent/CN110289260B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101908509A (en) * | 2009-06-08 | 2010-12-08 | 海力士半导体有限公司 | Make the method for nonvolatile semiconductor memory member |
| CN104112654A (en) * | 2013-04-18 | 2014-10-22 | 中芯国际集成电路制造(上海)有限公司 | Process method for reducing floating gate holes |
| CN104779209A (en) * | 2014-01-13 | 2015-07-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing flash memory |
| CN105845685A (en) * | 2015-01-30 | 2016-08-10 | 台湾积体电路制造股份有限公司 | Method to improve floating gate uniformity for non-volatile memory devices |
| US20160284718A1 (en) * | 2015-03-24 | 2016-09-29 | SanDisk Technologies, Inc. | Common Source Line with Discrete Contact Plugs |
| CN109494224A (en) * | 2017-09-08 | 2019-03-19 | 华邦电子股份有限公司 | Nonvolatile memory device and its manufacturing method |
| CN108109656A (en) * | 2017-12-28 | 2018-06-01 | 上海华力微电子有限公司 | The production method and flash array of flash array |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113224064A (en) * | 2021-04-21 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Method for manufacturing flash memory device |
| CN113224066A (en) * | 2021-04-28 | 2021-08-06 | 华虹半导体(无锡)有限公司 | Flash memory device structure and manufacturing method thereof |
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|---|---|
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