CN113517353A - Manufacturing method of semi-floating gate device - Google Patents
Manufacturing method of semi-floating gate device Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 90
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 80
- 238000000227 grinding Methods 0.000 claims abstract description 63
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 55
- 238000005498 polishing Methods 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 21
- 239000010703 silicon Substances 0.000 claims abstract description 21
- 239000000126 substance Substances 0.000 claims abstract description 13
- 238000007517 polishing process Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 24
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000000059 patterning Methods 0.000 claims description 19
- 239000000463 material Substances 0.000 claims description 9
- 238000005137 deposition process Methods 0.000 claims description 6
- 150000004767 nitrides Chemical group 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims 2
- 230000000694 effects Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 238000001459 lithography Methods 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
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- 239000002210 silicon-based material Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000007599 discharging Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
Abstract
The invention discloses a manufacturing method of a semi-floating gate device, wherein a gate structure of the semi-floating gate device comprises a floating gate structure, a first control gate superposed on the top of the floating gate structure and a second control gate spanning steps of the floating gate structure and the first control gate, a second metal gate of the second control gate is formed by adopting a back gate process, a floating gate polycrystalline silicon layer of the floating gate structure can fill a gate groove and a dielectric layer window, and the floating gate polycrystalline silicon layer and a third amorphous silicon pseudo gate in the back gate process are subjected to the following planarization processes, which comprise: step 1, depositing a grinding stop layer. And 2, forming a grinding layer. And 3, carrying out chemical mechanical polishing process on the polishing layer and stopping polishing on the polishing stopping layer. And 4, etching the grinding layer, the grinding stop layer and the floating gate polycrystalline silicon layer or the third amorphous silicon pseudo gate at the bottom of the silicon uneven surface by adopting an etching process and stopping at a required height. The invention can realize the semi-floating gate device with double control gates, thereby realizing the simultaneous reading and writing of the device and realizing good planarization effect.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a method for manufacturing a Semi-floating gate (Semi-floating gate) device.
Background
The semi-floating gate device has great potential to replace DRAM, it reads and writes fast, and does not need capacitor device. The semi-floating gate device is different from a common floating gate device in that the semi-floating gate device completes charging and discharging by utilizing an embedded tunneling transistor and a PN node. And writing is carried out through a channel of the embedded tunneling transistor, and the PN node carries out erasing operation. FIG. 1 is a schematic structural diagram of a conventional semi-floating gate device; existing semi-floating gate devices include:
a first well region 101 doped with the second conductivity type, a lightly doped source region 1021 made up of a second well region 102 doped with the second conductivity type, and a lightly doped drain region 1022 are formed in the semiconductor substrate.
The floating gate structure includes a gate trench, a floating gate dielectric layer 103, a dielectric layer window, and a floating gate polysilicon layer 104.
The gate trench passes through the second well region 102 and the bottom surface of the gate trench enters into the first well region 101. The floating gate dielectric layer 103 covers the bottom surface and the side surface of the gate trench and extends to the surface of the lightly doped drain region 1022 outside the gate trench.
The floating gate polysilicon layer 104 completely fills the gate trench formed with the floating gate dielectric layer 103 and extends to the floating gate dielectric layer 103 and the dielectric layer window outside the gate trench. The dielectric layer window is located on the surface of the lightly doped drain region 1022 in the region of the dashed line frame 111, and a PN structure is formed by contacting the floating gate polysilicon layer 104 and the lightly doped drain region 1022 at the dielectric layer window.
The material of the floating gate dielectric layer 103 comprises an oxide layer.
The floating gate polysilicon layer 104 is a polysilicon layer doped with a second conductivity type.
The bottom of the floating gate structure covers the first well region 101, and the surface of the first well region 101 covered by the floating gate structure is used for forming a conductive channel for electrically connecting the lightly doped source region 1021 and the lightly doped drain region 1022.
A heavily doped source region 109 of the first conductivity type is formed in a selected region of the surface of the lightly doped source region 1021.
A drain region 110 heavily doped with the first conductivity type is formed in a selected region of the surface of the lightly doped drain region 1022.
The floating gate structure has a first side and a second side over the semiconductor substrate surface.
The source region 109 is self-aligned to the first side of the floating gate structure.
A control gate, which includes a layer of gate conductive material 107, a layer of gate dielectric 105, and an intergate dielectric 106, overlies the top of the floating gate structure and the surface of the lightly doped drain region 1022 between the drain region 110 and the second side of the floating gate structure. The gate dielectric layer 105 is used for realizing the isolation between the gate conductive material layer 107 and the lightly doped drain region 1022, and the inter-gate dielectric layer 106 is used for realizing the isolation between the gate conductive material layer 107 and the floating gate polysilicon layer 104.
The drain region 110 and a second side of the second control gate 105 are self-aligned.
The prior device shown in fig. 1 has only a single control gate overlying a floating gate and a portion overlying a substrate. In both write and erase operations, tunneling of charge across the PN junction at the location of dashed box 111 is achieved under control of the control gate. The read operation of the device also needs to be performed under the control of the control gate. The structure needs to share the same control gate for reading and writing, and can not read and write at the same time.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a manufacturing method of a semi-floating gate device, which can realize the semi-floating gate device with double control gates, thereby realizing simultaneous reading and writing of the device and realizing good planarization effect.
In order to solve the technical problem, in the manufacturing method of the semi-floating gate device provided by the invention, the gate structure of the semi-floating gate device comprises a floating gate structure formed by overlapping a floating gate dielectric layer and a floating gate polycrystalline silicon layer, a first control gate formed by overlapping a first gate dielectric layer and a first polycrystalline silicon gate, and a second control gate formed by overlapping a second gate dielectric layer and a second metal gate; the second metal gate is formed by adopting a gate-last process, and a third amorphous silicon dummy gate is adopted in the gate-last process to define a forming area of the second metal gate.
A dielectric layer window is formed in the floating gate dielectric layer, a gate groove is formed on the semiconductor substrate, the floating gate polycrystalline silicon layer is filled in the dielectric layer window and the gate groove, and the floating gate polycrystalline silicon layer has a silicon uneven surface after being deposited.
The third amorphous silicon pseudo gate can cross a step formed by superposed layers of the floating gate dielectric layer, the floating gate polycrystalline silicon layer, the first gate dielectric layer and the first polycrystalline silicon gate, and the third amorphous silicon pseudo gate has a silicon uneven surface after being deposited.
And after the deposition process is finished, the floating gate polycrystalline silicon layer and the third amorphous silicon pseudo gate are subjected to the following planarization process, wherein the planarization process comprises the following steps:
and step 1, depositing a grinding stop layer on the uneven surface of the silicon.
And 2, forming a grinding layer on the surface of the grinding stop layer, wherein the lowest position of the top surface of the grinding layer is higher than the highest position of the top surface of the grinding stop layer.
And 3, grinding the grinding layer by adopting a chemical mechanical grinding process, stopping on the grinding stop layer and flattening the top surface of the superposed layer of the grinding layer and the grinding stop layer.
And 4, etching the grinding layer, the grinding stop layer and the floating gate polycrystalline silicon layer or the third amorphous silicon pseudo gate at the bottom of the silicon uneven surface by adopting an etching process and stopping at the height required by the floating gate polycrystalline silicon layer or the third amorphous silicon pseudo gate.
In a further improvement, the floating gate polysilicon layer deposition comprises the following steps:
the method comprises the steps of firstly, providing the semiconductor substrate, and forming a first conductive type doped light doping source region, a first conductive type doped light doping drain region and a second conductive type doped first well region on the semiconductor substrate.
The bottom surface of the grid groove enters the first well region, and the lightly doped source region is positioned above the first well region and is in contact with the first side face of the grid groove; the lightly doped drain region is positioned above the first well region and is contacted with the second side surface of the grid groove.
Step two, forming the floating gate dielectric layer, wherein the floating gate dielectric layer covers the bottom surface and the side surface of the grid groove and extends to the surface of the semiconductor substrate outside the grid groove; and forming a dielectric layer window in the selected region of the floating gate dielectric layer, wherein the dielectric layer window is positioned on the surface of the lightly doped drain region.
And thirdly, performing a step three corresponding to the floating gate polycrystalline silicon layer deposition process, wherein the floating gate polycrystalline silicon layer is deposited, the gate trench formed with the floating gate dielectric layer is completely filled and extends to the floating gate dielectric layer outside the gate trench and the dielectric layer window, and the floating gate polycrystalline silicon layer and the lightly doped drain region are contacted at the dielectric layer window to form a PN structure.
The further improvement is that after the flattening process of the floating gate polysilicon layer is completed, the method also comprises the following steps:
and fourthly, sequentially forming a first gate dielectric layer and a first polysilicon gate on the surface of the floating gate polysilicon layer.
And fifthly, carrying out a first patterning process to form a second side surface of the floating gate structure and a second side surface of the first control gate aligned with the second side surface of the floating gate structure.
A second gate dielectric layer and the third amorphous silicon pseudo gate are sequentially formed, wherein the second gate dielectric layer covers the surface of the semiconductor substrate outside the second side face of the floating gate structure, the second side face of the first control gate and the surface of the first polysilicon gate; the third amorphous silicon dummy gate is formed on the surface of the second gate dielectric layer.
And then carrying out the planarization process on the third amorphous silicon dummy gate.
In a further improvement, in the fifth step, the first patterning process simultaneously forms the first side of the floating gate structure and the first side of the first control gate aligned with the first side of the floating gate structure.
In a further improvement, the first patterning process in the fifth step is formed by a lithography definition plus etching process.
In a further improvement, the third amorphous silicon dummy gate further comprises, after the planarization process is completed:
and seventhly, performing a second patterning process to form a first side surface and a second side surface of the dummy gate structure of the second control gate.
The pseudo grid structure is formed by overlapping the second grid dielectric layer and the third amorphous silicon pseudo grid after the second patterning process is finished, the second side face of the pseudo grid structure is located at the top of the lightly doped drain region, and the first side face of the pseudo grid structure is located at the top of the first control grid.
In a further improvement, the second patterning process in the seventh step is formed by a lithography definition plus etching process.
In a further improvement, after the seventh step, the method further comprises the steps of:
and step eight, forming side walls, wherein the side walls cover the first side surface of the first control gate, the first side surface of the floating gate structure and the second side surface of the second control gate.
The further improvement is that the method also comprises the following steps:
and step nine, performing source-drain injection to form a source region and a drain region, wherein the source region is formed in the lightly doped source region and is self-aligned with the first side surface of the first control gate, and the drain region is formed in the lightly doped drain region and is self-aligned with the second side surface of the dummy gate structure.
The further improvement is that the method also comprises the following steps:
and step ten, removing the third amorphous silicon pseudo gate by a gate replacement process and forming the second metal gate in the third amorphous silicon pseudo gate removal area.
The further improvement is that the method also comprises the following steps:
step eleven, forming a metal interconnection structure to connect the first polysilicon gate to a first control electrode and connect the second metal gate to a second control electrode, wherein the source region is connected to the source electrode, and the drain region is connected to the drain electrode.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In a further improvement, the polishing layer and the polishing stop layer are made of materials selected such that the polishing selection ratio of the chemical mechanical polishing process to the polishing layer and the polishing stop layer in step 3 is greater than 1.
In a further refinement, the combination of materials of the polishing layer and the polish stop layer comprises: the grinding layer is an oxide, and the grinding stop layer is a nitride; or, the polishing layer is nitride, and the polishing stop layer is oxide.
The further improvement is that the thickness of the grinding stop layer is 0.1 nm-100 nm;
the thickness of the grinding layer is 0.1 nm-5100 nm.
In a further improvement, in step 4, the etching process has a selectivity of 1 to the polishing layer, the polishing stop layer and the floating gate polysilicon layer or the third amorphous silicon dummy gate at the bottom of the silicon uneven surface.
In a further improvement, the lightly doped source region and the lightly doped drain region are both formed by a second well region doped with the first conductivity type and formed on the surface of the first well region, and the gate trench penetrates through the second well region to divide the second well region into the lightly doped source region and the lightly doped drain region.
The control grid of the semi-floating grid device is divided into two control grids, so that the device can realize simultaneous reading and writing.
The first control gate is positioned at the top of the floating gate structure and adopts a polysilicon gate structure, so that the device has excellent electric field control capability; the second control grid spans the overlapping structure of the floating grid structure and the first control grid, and the second control grid adopts a metal grid structure to enable the device to have low grid leakage.
The planarization process of the third amorphous silicon pseudo gate in the post-gate process of the floating gate polysilicon and the second control gate of the floating gate structure does not contain a silicon chemical mechanical polishing process, and planarization is carried out through an etching process, so that the planarization of the floating gate polysilicon and the third amorphous silicon pseudo gate can be realized under the condition of lacking a silicon material chemical mechanical polishing process machine table and grinding fluid, and finally, the whole gate structure can have a good planarization effect, so that the performance of a device can be improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a prior art structure of a semi-floating gate device;
FIG. 2 is a flow chart of a planarization process of a floating gate polysilicon layer or a third amorphous silicon dummy gate in the method for manufacturing a semi-floating gate device according to the embodiment of the invention;
FIG. 3 is a schematic structural diagram of a semi-floating gate device in a method for manufacturing the semi-floating gate device according to an embodiment of the invention;
FIG. 4 is a schematic diagram of the structure of the device of FIG. 3 prior to gate replacement;
fig. 5A-5K are schematic views of device structures in steps of a method for manufacturing a semi-floating gate device according to an embodiment of the invention.
Detailed Description
As shown in fig. 2, it is a flow chart of a planarization process of the floating gate polysilicon layer 204 or the third amorphous silicon dummy gate 2053 in the manufacturing method of the semi-floating gate device according to the embodiment of the invention; fig. 3 is a schematic structural diagram of a semi-floating gate device in the manufacturing method of the semi-floating gate device according to the embodiment of the invention; as shown in fig. 4, is a schematic structural diagram of the device of fig. 3 before gate replacement; fig. 5A to 5K are schematic views of device structures in steps of a method for manufacturing a semi-floating gate device according to an embodiment of the present invention; in the manufacturing method of the semi-floating gate device according to the embodiment of the present invention, as shown in fig. 3, the gate structure of the semi-floating gate device includes a floating gate structure formed by overlapping a floating gate dielectric layer 203 and a floating gate polysilicon layer 204, a first control gate 206 formed by overlapping a first gate dielectric layer 2061 and a first polysilicon gate 2062, and a second control gate 205 formed by overlapping a second gate dielectric layer 2051 and a second metal gate 2052. The second metal gate 2052 is formed by using a gate last process, as shown in fig. 5, a third amorphous silicon dummy gate 2053 is used in the gate last process to define a formation region of the second metal gate 2052; the dummy gate structure 205a is formed by overlapping the second gate dielectric layer 2051 and the third amorphous silicon dummy gate 2053.
A dielectric layer window is formed in the floating gate dielectric layer 203, a gate trench is formed on the semiconductor substrate, the floating gate polysilicon layer 204 is filled in the dielectric layer window and the gate trench, and the floating gate polysilicon layer 204 has a silicon uneven surface after deposition.
The third amorphous silicon dummy gate 2053 spans a step formed by stacked layers of the floating gate dielectric layer 203, the floating gate polysilicon layer 204, the first gate dielectric layer 2061 and the first polysilicon gate 2062, and the third amorphous silicon dummy gate 2053 has a silicon uneven surface after being deposited.
After the deposition process is completed, the floating gate polysilicon layer 204 and the third amorphous silicon dummy gate 2053 are both subjected to the following planarization processes, including:
and step 1, depositing a grinding stop layer on the uneven surface of the silicon.
And 2, forming a grinding layer on the surface of the grinding stop layer, wherein the lowest position of the top surface of the grinding layer is higher than the highest position of the top surface of the grinding stop layer.
And 3, grinding the grinding layer by adopting a chemical mechanical grinding process, stopping on the grinding stop layer and flattening the top surface of the superposed layer of the grinding layer and the grinding stop layer.
And 4, etching the grinding layer, the grinding stop layer and the floating gate polycrystalline silicon layer 204 or the third amorphous silicon pseudo gate 2053 at the bottom of the silicon uneven surface by adopting an etching process and stopping at the height required by the floating gate polycrystalline silicon layer 204 or the third amorphous silicon pseudo gate 2053.
The materials of the polishing layer and the polishing stop layer are selected from the materials with the polishing selection ratio of the chemical mechanical polishing process to the polishing layer and the polishing stop layer in step 3 being more than 1.
The combination of materials of the polishing layer and the polishing stop layer comprises: the grinding layer is an oxide, and the grinding stop layer is a nitride; or, the polishing layer is nitride, and the polishing stop layer is oxide.
The thickness of the grinding stop layer is 0.1 nm-100 nm;
the thickness of the grinding layer is 0.1 nm-5100 nm.
In step 4, the etching process has a selectivity of 1 to the polishing layer, the polishing stop layer, and the floating gate polysilicon layer 204 or the third amorphous silicon dummy gate 2053 at the bottom of the uneven silicon surface.
The floating gate polysilicon layer 204 comprises the following steps before deposition:
step one, as shown in fig. 5A, providing the semiconductor substrate, and forming a lightly doped source region 2021 doped with a first conductivity type, a lightly doped drain region 2022 doped with a first conductivity type, and a first well region 201 doped with a second conductivity type on the semiconductor substrate.
The bottom surface of the gate trench enters the first well region 201, and the lightly doped source region 2021 is located above the first well region 201 and contacts the first side of the gate trench; the lightly doped drain region 2022 is located above the first well region 201 and contacts the second side of the gate trench.
In an embodiment of the present invention, the semiconductor substrate includes a silicon substrate.
The lightly doped source region 2021 and the lightly doped drain region 2022 are both composed of a second well region 202 doped with the first conductivity type formed on the surface of the first well region 201, and the gate trench penetrates the second well region 202 to divide the second well region 202 into the lightly doped source region 2021 and the lightly doped drain region 2022.
The second conductive type doping ion implantation dosage of the first well region 201 is 0.25e14cm-2 to 2.50e14cm-2, and the ion implantation energy is 55keV to 220 keV.
From top to bottom, the doping concentration of the first well region 201 decreases in a gradient manner.
The first conductive type doping ion implantation dosage of the second well region 202 is 4.5e12cm-2 to 2.50e13cm-2, and the ion implantation energy is 45keV to 85 keV.
Step two, as shown in fig. 5A, forming the floating gate dielectric layer 203, wherein the floating gate dielectric layer 203 covers the bottom surface and the side surface of the gate trench and extends to the surface of the semiconductor substrate outside the gate trench; and forming a dielectric layer window in the selected region of the floating gate dielectric layer 203, wherein the dielectric layer window is positioned on the surface of the lightly doped drain region 2022.
Step three, as shown in fig. 5A, a deposition process of the floating gate polysilicon layer 204 is performed, after the floating gate polysilicon layer 204 is deposited, the gate trench formed with the floating gate dielectric layer 203 is completely filled and extends to the floating gate dielectric layer 203 outside the gate trench and the dielectric layer window, and a PN structure is formed by contacting the floating gate polysilicon layer 204 and the lightly doped drain region 2022 at the dielectric layer window.
Then, a planarization process, i.e., a first planarization process, is performed on the floating gate polysilicon layer 204, including:
step 1, as shown in fig. 5B, a polish stop layer 301a is deposited on the uneven surface of the floating gate polysilicon layer 204.
Step 2, as shown in fig. 5C, a polishing layer 302a is formed on the surface of the polishing stop layer 301a, and the lowest position of the top surface of the polishing layer 302a is higher than the highest position of the top surface of the polishing stop layer 301 a. The dashed line AA represents the uppermost top surface of the polish stop layer 301 a.
Step 3, as shown in fig. 5D, polishing the polishing layer 302a by using a chemical mechanical polishing process and stopping on the polishing stop layer 301a, that is, stopping at a position corresponding to the dotted line AA, and finally, flattening the top surface of the superimposed layer of the polishing layer 302a and the polishing stop layer 301 a.
And 4, as shown in fig. 5E, etching the grinding layer 302a, the grinding stop layer 301a and the floating gate polysilicon layer 204 by using an etching process and stopping at a height required by the floating gate polysilicon layer 204.
After the planarization process of the floating gate polysilicon layer 204 is completed, the method further includes the following steps:
step four, as shown in fig. 5F, a first gate dielectric layer 2061 and a first polysilicon gate 2062 are sequentially formed on the surface of the floating gate polysilicon layer 204.
And step five, as shown in fig. 5G, performing a first patterning process to form a second side surface of the floating gate structure and a second side surface of the first control gate 206 aligned with the second side surface of the floating gate structure.
In the embodiment of the present invention, the first patterning process forms the first side of the floating gate structure and the first side of the first control gate 206 aligned with the first side of the floating gate structure at the same time. In other embodiments, the first side of the floating gate structure and the first side of the first control gate 206 aligned with the first side of the floating gate structure can also be formed subsequently using a patterning process alone.
The first patterning process is formed by a lithography definition plus etching process.
Step six, as shown in fig. 5H, a second gate dielectric layer 2051 and the third amorphous silicon dummy gate 2053 are sequentially formed, where the second gate dielectric layer 2051 covers the surface of the semiconductor substrate outside the second side surface of the floating gate structure, the second side surface of the first control gate 206, and the surface of the first polysilicon gate 2062; the third amorphous silicon dummy gate 2053 is formed on the surface of the second gate dielectric layer 2051.
Then, the third amorphous silicon dummy gate 2053 is subjected to the planarization process, that is, a second planarization process, which includes:
step 1, as shown in fig. 5I, a polishing stop layer 301b is deposited on the uneven surface of the third amorphous silicon dummy gate 2053.
Step 2, as shown in fig. 5J, a polishing layer 302b is formed on the surface of the polishing stop layer 301b, and the lowest position of the top surface of the polishing layer 302b is higher than the highest position of the top surface of the polishing stop layer 301 b. The dotted line BB indicates the uppermost top surface of the polish stop layer 301 b.
Step 3, as shown in fig. 5K, polishing the polishing layer 302b by using a chemical mechanical polishing process and stopping on the polishing stop layer 301b, that is, stopping at a position corresponding to the dotted line BB, and finally flattening the top surface of the superimposed layer of the polishing layer 302b and the polishing stop layer 301 b.
And step 4, as shown in fig. 4, etching the grinding layer 302b, the grinding stop layer 301b and the third amorphous silicon pseudo gate 2053 by using an etching process and stopping at a height required by the third amorphous silicon pseudo gate 2053.
After the planarization process of the third amorphous silicon dummy gate 2053 is completed, the method further includes:
step seven, as shown in fig. 4, a second patterning process is performed to form a first side and a second side of the dummy gate structure 205a of the second control gate 205.
The dummy gate structure 205a is formed by overlapping the second gate dielectric layer 2051 and the third amorphous silicon dummy gate 2053 after the second patterning process is completed, the second side surface of the dummy gate structure 205a is located at the top of the lightly doped drain region 2022, and the first side surface of the dummy gate structure 205a is located at the top of the first control gate 206.
The second patterning process is formed by a lithography definition plus etch process.
After the seventh step, the method also comprises the following steps:
step eight, as shown in fig. 4, forming a sidewall 208, where the sidewall 208 covers the first side surface of the first control gate 206, the first side surface of the floating gate structure, and the first side surface and the second side surface of the second control gate 205. In fig. 4, the second gate dielectric layer 2051 is also used for the third amorphous silicon dummy gate 2053 and the inter-gate isolation dielectric layer 207 between the floating gate polysilicon layer 204 and the first polysilicon gate 2062.
Step nine, as shown in fig. 4, performing source-drain implantation to form a source region 209 and a drain region 210, where the source region 209 is formed in the lightly doped source region 2021 and is self-aligned with the first side surface of the first control gate 206, and the drain region 210 is formed in the lightly doped drain region 2022 and is self-aligned with the second side surface of the dummy gate structure 205 a.
Step ten, as shown in fig. 3, a gate replacement process is performed to remove the third amorphous silicon dummy gate 2053 and form the second metal gate 2052 in the removed area of the third amorphous silicon dummy gate 2053.
Eleventh, a metal interconnection structure is formed to connect the first polysilicon gate 2062 to a first control electrode and the second metal gate 2052 to a second control electrode, the source region 209 is connected to the source electrode, and the drain region 210 is connected to the drain electrode.
According to the embodiment of the invention, the control gate of the semi-floating gate device is split into two control gates, so that the devices can be read and written simultaneously.
The first control gate 206 is positioned at the top of the floating gate structure and adopts a polysilicon gate structure, so that the device has excellent electric field control capability; the second control gate 205 spans the stack of the floating gate structure and the first control gate 206 and the second control gate 205 adopts a metal gate structure to enable the device to have low gate leakage.
In the embodiment of the invention, the planarization process of the third amorphous silicon dummy gate 2053 in the gate-last process of the floating gate polysilicon and the second control gate 205 of the floating gate structure does not contain a silicon chemical mechanical polishing process, but carries out planarization through an etching process, so that the planarization of the floating gate polysilicon and the third amorphous silicon dummy gate can be realized under the condition of lacking a silicon material chemical mechanical polishing process machine and grinding fluid, and finally, the whole gate structure can have a good planarization effect, thereby improving the performance of a device.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (17)
1. A manufacturing method of a semi-floating gate device is characterized in that a gate structure of the semi-floating gate device comprises a floating gate structure formed by overlapping a floating gate dielectric layer and a floating gate polycrystalline silicon layer, a first control gate formed by overlapping a first gate dielectric layer and a first polycrystalline silicon gate, and a second control gate formed by overlapping a second gate dielectric layer and a second metal gate; the second metal gate is formed by adopting a gate-last process, and a third amorphous silicon pseudo gate is adopted in the gate-last process to define a forming area of the second metal gate;
a dielectric layer window is formed in the floating gate dielectric layer, a gate groove is formed on the semiconductor substrate, the floating gate polycrystalline silicon layer can be filled in the dielectric layer window and the gate groove, and the floating gate polycrystalline silicon layer has a silicon uneven surface after being deposited;
the third amorphous silicon pseudo gate can cross a step formed by superposed layers of the floating gate dielectric layer, the floating gate polycrystalline silicon layer, the first gate dielectric layer and the first polycrystalline silicon gate, and the third amorphous silicon pseudo gate has a silicon uneven surface after being deposited;
and after the deposition process is finished, the floating gate polycrystalline silicon layer and the third amorphous silicon pseudo gate are subjected to the following planarization process, wherein the planarization process comprises the following steps:
step 1, depositing a grinding stop layer on the uneven surface of the silicon;
step 2, forming a grinding layer on the surface of the grinding stop layer, wherein the lowest position of the top surface of the grinding layer is higher than the highest position of the top surface of the grinding stop layer;
step 3, grinding the grinding layer by adopting a chemical mechanical grinding process, stopping on the grinding stop layer and flattening the top surface of the superposed layer of the grinding layer and the grinding stop layer;
and 4, etching the grinding layer, the grinding stop layer and the floating gate polycrystalline silicon layer or the third amorphous silicon pseudo gate at the bottom of the silicon uneven surface by adopting an etching process and stopping at the height required by the floating gate polycrystalline silicon layer or the third amorphous silicon pseudo gate.
2. The method of manufacturing a semi-floating gate device of claim 1, wherein: the floating gate polysilicon layer comprises the following steps before deposition:
providing the semiconductor substrate, and forming a first conductive type doped light doping source region, a first conductive type doped light doping drain region and a second conductive type doped first well region on the semiconductor substrate;
the bottom surface of the grid groove enters the first well region, and the lightly doped source region is positioned above the first well region and is in contact with the first side face of the grid groove; the lightly doped drain region is positioned above the first well region and is contacted with the second side surface of the grid groove;
step two, forming the floating gate dielectric layer, wherein the floating gate dielectric layer covers the bottom surface and the side surface of the grid groove and extends to the surface of the semiconductor substrate outside the grid groove; forming a dielectric layer window in a selected region of the floating gate dielectric layer, wherein the dielectric layer window is positioned on the surface of the lightly doped drain region;
and thirdly, performing a step three corresponding to the floating gate polycrystalline silicon layer deposition process, wherein the floating gate polycrystalline silicon layer is deposited, the gate trench formed with the floating gate dielectric layer is completely filled and extends to the floating gate dielectric layer outside the gate trench and the dielectric layer window, and the floating gate polycrystalline silicon layer and the lightly doped drain region are contacted at the dielectric layer window to form a PN structure.
3. The method of manufacturing a semi-floating gate device of claim 2, wherein: after the floating gate polysilicon layer flattening process is finished, the method further comprises the following steps:
forming a first gate dielectric layer and a first polysilicon gate on the surface of the floating gate polysilicon layer in sequence;
fifthly, carrying out a first patterning process to form a second side surface of the floating gate structure and a second side surface of the first control gate aligned with the second side surface of the floating gate structure;
a second gate dielectric layer and the third amorphous silicon pseudo gate are sequentially formed, wherein the second gate dielectric layer covers the surface of the semiconductor substrate outside the second side face of the floating gate structure, the second side face of the first control gate and the surface of the first polysilicon gate; the third amorphous silicon pseudo gate is formed on the surface of the second gate dielectric layer;
and then carrying out the planarization process on the third amorphous silicon dummy gate.
4. The method of manufacturing a semi-floating gate device of claim 3, wherein: in the fifth step, the first side surface of the floating gate structure and the first side surface of the first control gate aligned with the first side surface of the floating gate structure are simultaneously formed by the first patterning process.
5. The method of manufacturing a semi-floating gate device of claim 4, wherein: and the first patterning process in the fifth step is formed by a photoetching definition and etching process.
6. The method of manufacturing a semi-floating gate device of claim 3, wherein: the third amorphous silicon dummy gate further comprises, after the planarization process is completed:
seventhly, performing a second patterning process to form a first side surface and a second side surface of the pseudo gate structure of the second control gate;
the pseudo grid structure is formed by overlapping the second grid dielectric layer and the third amorphous silicon pseudo grid after the second patterning process is finished, the second side face of the pseudo grid structure is located at the top of the lightly doped drain region, and the first side face of the pseudo grid structure is located at the top of the first control grid.
7. The method of manufacturing a semi-floating gate device of claim 6, wherein: and the second patterning process in the seventh step is formed by a photoetching definition and etching process.
8. The method of manufacturing a semi-floating gate device of claim 7, wherein: after the seventh step, the method also comprises the following steps:
and step eight, forming side walls, wherein the side walls cover the first side face of the first control gate, the first side face of the floating gate structure, and the first side face and the second side face of the second control gate.
9. The method of manufacturing a semi-floating gate device of claim 8, further comprising the steps of:
and step nine, performing source-drain injection to form a source region and a drain region, wherein the source region is formed in the lightly doped source region and is self-aligned with the first side surface of the first control gate, and the drain region is formed in the lightly doped drain region and is self-aligned with the second side surface of the dummy gate structure.
10. The method of manufacturing a semi-floating gate device of claim 9, further comprising the steps of:
and step ten, removing the third amorphous silicon pseudo gate by a gate replacement process and forming the second metal gate in the third amorphous silicon pseudo gate removal area.
11. The method of manufacturing a semi-floating gate device of claim 10, further comprising the steps of:
step eleven, forming a metal interconnection structure to connect the first polysilicon gate to a first control electrode and connect the second metal gate to a second control electrode, wherein the source region is connected to the source electrode, and the drain region is connected to the drain electrode.
12. The method of manufacturing a semi-floating gate device of claim 1, wherein: the semiconductor substrate includes a silicon substrate.
13. The method of manufacturing a semi-floating gate device of claim 12, wherein: the materials of the polishing layer and the polishing stop layer are selected from the materials with the polishing selection ratio of the chemical mechanical polishing process to the polishing layer and the polishing stop layer in step 3 being more than 1.
14. The method of manufacturing a semi-floating gate device of claim 13, wherein: the combination of materials of the polishing layer and the polishing stop layer comprises: the grinding layer is an oxide, and the grinding stop layer is a nitride; or, the polishing layer is nitride, and the polishing stop layer is oxide.
15. A method of manufacturing a semi-floating gate device according to claim 13 or 14, characterized in that: the thickness of the grinding stop layer is 0.1 nm-100 nm;
the thickness of the grinding layer is 0.1 nm-5100 nm.
16. A method of manufacturing a semi-floating gate device according to claim 1, 13 or 14, characterized in that: in step 4, the etching process has a selectivity ratio of 1 to the grinding layer, the grinding stop layer and the floating gate polysilicon layer or the third amorphous silicon dummy gate at the bottom of the silicon uneven surface.
17. The method of manufacturing a semi-floating gate device of claim 2, wherein: the lightly doped source region and the lightly doped drain region are both composed of a second well region doped with the first conductivity type and formed on the surface of the first well region, and the gate trench penetrates through the second well region to divide the second well region into the lightly doped source region and the lightly doped drain region.
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