KR20080040537A - Non-volatile memory device, stacked structure of the same, method of operating the same, method of fabricating the same and system using the same - Google Patents

Abstract

A non-volatile memory device, a stacked structure of the same, a method for operating the same, a method for manufacturing the same, and a system using the same are provided to increase the degree of integration by reducing a volume size of a memory cell. A plurality of control gate electrodes(140) are arranged serially on a semiconductor substrate(105). A charge storage layer(115) is inserted between the control gate electrodes and the semiconductor substrate. A tunneling insulating layer(110) is inserted between the charge storage layer and the semiconductor substrate. A plurality of blocking insulating layers(135a) are inserted between the charge storage layers and the control gate electrodes. The blocking insulating layers are extended to cover both sidewalls of the control gate electrodes.

Description

Non-volatile memory device, stacked structure thereof, method of operation thereof, method of fabrication thereof, and system using nonvolatile memory device {non-volatile memory device, stacked structure of the same, method of operating the same, method of fabricating the same and system using the same}

1 is a diagram showing a nonvolatile memory device according to a first embodiment of the present invention;

2 is a cross-sectional view showing a nonvolatile memory device according to a second embodiment of the present invention;

3 is a cross-sectional view showing a nonvolatile memory device according to a third embodiment of the present invention;

4 is a partial equivalent circuit diagram of the nonvolatile memory device of FIG. 3;

5 to 9 are cross-sectional views showing a method of manufacturing a nonvolatile memory device according to the first embodiment of the present invention;

10 to 12 are cross-sectional views showing a method of manufacturing a nonvolatile memory device according to the second embodiment of the present invention;

13 to 16 are cross-sectional views showing a method of manufacturing a nonvolatile memory device according to the third embodiment of the present invention;

17 is a cross-sectional view showing a stacked structure of a nonvolatile memory device according to the fourth embodiment of the present invention; And

18 is a block diagram illustrating a system using a nonvolatile memory device according to a fifth embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a structure of a nonvolatile memory device, a method of operating the same, a method of manufacturing the same, and a system using the nonvolatile memory device.

Nonvolatile memory devices, such as flash memory devices, include a charge storage layer of floating gate type or charge trap type. Recently, in the manufacture of such flash memory devices, a technique of forming a control gate electrode using a damascene method has been used. For example, Korean Patent Publication No. 2004-0024896 by Kang Sung-taek discloses "SONOS EEPROM with improved program and erase characteristics." Such sony Y pyrom may be included in a flash memory device.

However, in the aforementioned patent, a blocking insulating layer and a charge storage layer are disposed on both sidewalls of the control gate electrode. Therefore, in such a flash memory device, it is difficult to increase the integration degree of the memory cell because of the width of the blocking insulating layer and the charge storage layer as well as the control gate electrode. Further, since the charge is spread to the charge storage layer disposed on the sidewall of the control gate electrode, the retention characteristics of the flash memory device may deteriorate, thereby reducing reliability.

In addition, in the nonvolatile memory device, the area occupied by the source or drain region occupies a large portion in the memory cell. However, despite the reduction in the gate length of the memory transistor, there is a limit to the increase in the density of the memory cell due to the area of the source or drain region. Therefore, it is necessary to reduce the size of the source or drain region in the memory cell.

SUMMARY OF THE INVENTION The first technical problem to be solved by the present invention is to provide a non-volatile memory device capable of high integration and high reliability and a stacked structure thereof.

Another object of the present invention is to provide a method of operating the nonvolatile memory device.

Another object of the present invention is to provide a method of manufacturing the nonvolatile memory device.

A fourth technical object of the present invention is to provide a system using the nonvolatile memory device.

A nonvolatile memory device of one embodiment of the present invention for achieving the first technical problem is provided. The plurality of control gate electrodes are arranged in series on the semiconductor substrate. A charge storage layer is interposed between the semiconductor substrate and the plurality of control gate electrodes. A tunneling insulating layer is interposed between the semiconductor substrate and the plurality of charge storage layers. A plurality of blocking insulating layers is interposed between the charge storage layers and the plurality of control gate electrodes, respectively, and extends to cover both sidewalls of the plurality of control gate electrodes.

The nonvolatile memory device may further include a pair of select gate electrodes on the semiconductor substrate, respectively disposed at both ends of the plurality of control gate electrodes.

The nonvolatile memory device may further include a plurality of dummy mask layers interposed between two adjacent ones of the plurality of blocking insulating layers.

The nonvolatile memory device may further include spacer insulating layers formed on both sidewalls of the pair of select gate electrodes.

A nonvolatile memory device according to another aspect of the present invention for achieving the first technical problem is provided. The plurality of control gate electrodes are arranged in series on the semiconductor substrate. A charge storage layer is interposed between the semiconductor substrate and the plurality of control gate electrodes. A tunneling insulating layer is interposed between the semiconductor substrate and the charge storage layer. A plurality of blocking insulating layers are interposed between the charge storage layer and the plurality of control gate electrodes, respectively. The plurality of auxiliary gate electrodes are interposed between two adjacent two of the plurality of control gate electrodes.

According to another aspect of the present invention for achieving the first technical problem, the nonvolatile memory devices may be provided in a unit layer structure, and a plurality of unit layer structures may be stacked on each other.

An operation method of a nonvolatile memory device of one embodiment of the present invention for achieving the second technical problem includes a program step, a read step, and an erase step. In the programming step, data is stored in a portion of the charge storage layer under the plurality of control gate electrodes. In the reading step, data stored in the charge storage layer is read. In the erasing step, data stored in the charge storage layer is erased. In the programming and reading steps, a first pass voltage is applied to the plurality of control gate electrodes to turn channel regions of the semiconductor substrate under the plurality of control gate electrodes and the plurality of auxiliary gate electrodes. Turn on.

A method for manufacturing a nonvolatile memory device of one embodiment of the present invention for achieving the third another technical problem is provided. A tunneling insulating layer is formed on the semiconductor substrate. A charge storage layer is formed on the tunneling insulating layer. On the charge storage layer, a plurality of blocking insulating layers each having a trench defined opposite to the charge storage layer are formed. A plurality of control gate electrodes filling the trenches of the plurality of blocking insulating layers are formed.

A system of one embodiment of the present invention for achieving the fourth technical problem includes a control unit for performing a command; A memory unit including a nonvolatile memory device for storing the command; And an input / output unit coupled to the memory unit or the control unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. In the accompanying drawings, the thicknesses of the various films and regions are highlighted for clarity.

In embodiments of the present invention, a nonvolatile memory device can program data by storing charge in a charge storage layer. For example, a nonvolatile memory device according to embodiments of the present invention may be referred to as a flash memory, a sonos memory, or an EEPROM. However, the present invention is not limited in scope by these names.

1 is a cross-sectional view illustrating a nonvolatile memory device 100 according to a first embodiment of the present invention. The nonvolatile memory device 100 of FIG. 1 may exemplarily represent a NAND structure.

Referring to FIG. 1, a plurality of control gate electrodes 140 are arranged in series on a semiconductor substrate 105. The charge storage layer 115 may be interposed between the semiconductor substrate 105 and the control gate electrodes 140. A plurality of blocking insulating layers 135a are interposed between the charge storage layer 115 and the control gate electrodes 140, and the tunneling insulating layer 110 is disposed between the charge storage layer 115 and the semiconductor substrate 105. May be interposed.

The stacked structure of the tunneling insulating layer 110 / charge storage layer 115 / blocking insulating layer 135a / control gate electrodes 140 may constitute memory transistors. For example, such memory transistors may be connected in series to form a NAND memory cell. The control gate electrodes 140 may be used as part of a word line of each of the memory transistors. The semiconductor substrate 105 connecting the memory transistors may be used as part of a bit line.

In more detail, the control gate electrodes 140 may include a conductive layer, for example, polysilicon, a metal, a metal silicide, or a metal nitride film. For example, the metal nitride film may include TaN or TiN. The number of control gate electrodes 140 may be appropriately selected depending on the capacity of the memory cell, thus not limiting the scope of the present invention.

The tunneling insulating layer 110 and the charge storage layer 115 may be provided as one layer on the semiconductor substrate 105. In this case, the memory transistors may store data using portions of the charge storage layer 115, respectively. Accordingly, the charge storage layer 115 preferably has a local charge trapping capability so that the charge therein does not move. However, in a modified example of the present invention, the tunneling insulating layer 110 and / or the charge storage layer 115 may be provided in plural numbers so as to be respectively limited under the control gate electrodes 140.

The blocking insulating layers 135a may be bent on the semiconductor substrate 105 at both edge portions to define trenches (not shown) opposite the charge storage layer 115. Control gate electrodes 140 are formed to fill these trenches. For example, the blocking insulating layers 135a may have sidewalls (not shown) respectively extending from between the control gate electrodes 140 and the tunneling insulating layer 110 to both sidewalls of the control gate electrodes 140. It may include. Sidewalls of the blocking insulating layers 135a may be disposed vertically on the semiconductor substrate 105, but the present invention is not limited to this angle.

Since the charge storage layer 115 is not interposed between the control gate electrodes 140, the structure according to this embodiment may contribute to reducing the separation distance between the control gate electrodes 140 as compared with the prior art. Therefore, the size of the memory cell can be reduced, and the degree of integration of the nonvolatile memory device 100 can be increased.

For example, the tunneling insulating layer 110 and the blocking insulating layers 135a may include an oxide film, a nitride film, or a high dielectric constant film. The high dielectric constant film may refer to an insulating layer having a higher dielectric constant than the oxide film and the nitride film, and may include, for example, Al ₂ O ₃ , HfO _2, or Ta ₂ O ₅ . The charge storage layer 115 may include polysilicon, nitride, dot, or nanocrystal. For example, dots or nanocrystals can be composed of particles of metal or polysilicon. Polysilicon may be used as a floating node, and nitride films, dots, or nanocrystals may be used as local charge trap layers.

A plurality of dummy mask layers 130 may be interposed between the blocking insulating layers 135a. For example, the dummy mask layers 130 may include a lower mask layer 120 on the charge storage layer 115 and an upper mask layer 125 on the lower mask layer 120. The lower mask layer 120 has an etch selectivity with respect to the charge storage layer 115, and the upper mask layer 125 has an etch selectivity with respect to the blocking insulating layers 135a and the control gate electrode 140. desirable. For example, the lower mask layer 120 may include an oxide layer and the upper mask layer 125 may include a nitride layer.

The pair of select gate electrodes 145 may be disposed at both ends of the control gate electrodes 140, respectively. The select gate electrodes 145 may configure a string select transistor and a source select transistor, respectively. A gate insulating layer (not shown) may be interposed between the selection gate electrodes 145 and the semiconductor substrate 105. In this embodiment, the select transistors and the memory transistors may have a similar structure, and thus the gate insulating layer may include the tunneling insulating layer 110, the charge storage layer 115, and the blocking insulating layer 135b. . However, the gate insulating layer is not limited to this structure and may be composed of, for example, one insulating layer.

The source or drain regions 150 may be formed near the surfaces of the semiconductor substrates 105 on both sides of the selection gate electrodes 145, respectively. For example, the semiconductor substrate 105 may be doped with impurities of the first conductivity type, and the source or drain region 150 may be doped with impurities of the second conductivity type opposite to the first conductivity type. For example, the first conductivity type and the second conductivity type may be any one selected from n type and p type, respectively.

Spacer insulating layers 160 may be disposed on both sidewalls of the selection gate electrodes 145. In addition, spacer insulating layers 160 may be further formed on outermost sidewalls of the control gate electrodes 140. The spacer insulating layers 160 may meet each other between the selection gate electrodes 145 and the pair of control gate electrodes 140 at both ends, and voids may be defined therebetween.

The channel region 155a may be continuously defined near the surface of the semiconductor substrate 105 under the control gate electrodes 140. That is, the channel region 155a is confined to the semiconductor substrate 105 under the control gate electrodes 140 and the dummy mask layers 130. Thus, memory transistors may be connected to the channel region 155a without a source or drain region. The channel region 155a may be part of the semiconductor substrate 105, but may be a conductive path for charge when the memory transistors are turned on. In addition, another channel region (not shown) may be defined in the semiconductor substrate 105 under the selection gate electrodes 145, but is not continuous with the channel region 155a because of the source or drain region 150.

The turn-on of the channel region 155a under the dummy mask layers 130 may use a lateral electric field of the control gate electrodes 140. This lateral electric field may be called a fringe field. Therefore, in order to continuously turn on the channel region 155a by the fringe field of the control gate electrodes 140, the width of the dummy mask layers 130 may be limited and the dummy mask layers ( 130, the doping concentration may be adjusted to lower the threshold voltage of the channel region 155a below. That is, by varying the doping concentrations of the channel regions 155a under the control gate electrodes 140 and the dummy mask layers 130, the threshold voltages therebetween may be varied.

As such, as the source or drain region is omitted in the memory cell, leakage current due to depletion of the source or drain region can be reduced. For example, the junction leakage current can be reduced and the off-current due to punch-through can be reduced.

2 is a cross-sectional view illustrating a nonvolatile memory device 200 according to a second embodiment of the present invention. The nonvolatile memory device 200 according to the exemplary embodiment of FIG. 2 is modified in part from the nonvolatile memory device 100 of FIG. 1. Thus, duplicate descriptions are omitted in both embodiments.

Referring to FIG. 2, the source or drain region 150 is further defined near the surface of the semiconductor substrate 150 on both sides of the pair of control gate electrodes 140 disposed at both ends of the control gate electrodes 140. . Accordingly, the channel region 155b may be limited to the vicinity of the surface of the semiconductor substrate 150 below except for the pair of control gate electrodes 140 disposed at both ends. Another channel region (not shown) may be defined under the pair of control gate electrodes 140 at both ends, but is not continuous with the channel region 155b.

The spacer insulating layers 160 may be further formed on both sidewalls of the pair of control gate electrodes 140 at both ends. In addition, spacer insulating layers 160 may be further formed on outermost sidewalls of the remaining control gate electrodes 140. In this case, the pair of control gate electrodes 140 at both ends and the spacer insulating layers 160 between the control gate electrodes 140 adjacent to each other may meet each other, and voids may be defined therebetween. .

In this embodiment, the pair of control gate electrodes 140 at both ends are not used as memory transistors for data storage but may be used as dummy transistors. For example, these dummy transistors may not be used as memory cells for data storage by operating simultaneously with the select transistors. This is because the memory transistors at both ends of the NAND memory cell have a problem in program operation depending on the distance from the select transistors. Thus, according to this embodiment, the memory transistors at both ends can be effectively excluded from the operation of the memory cell.

3 is a cross-sectional view illustrating a nonvolatile memory device 300 according to a third embodiment of the present invention. The nonvolatile memory device 300 of FIG. 3 is a modification of the structure and use of the dummy mask layer 130 in the nonvolatile memory device 100 of FIG. 1. Thus, duplicate descriptions are omitted in both embodiments.

Referring to FIG. 3, a plurality of auxiliary gate electrodes 127 may be disposed between the blocking insulating layers 135a. The auxiliary gate electrodes 127 may be provided to more easily control the turn-on of the channel region 155a. For example, the auxiliary gate electrodes 127 may include polysilicon, a metal, a metal silicide, or a metal nitride layer. Optionally, second blocking insulating layers 122 may be interposed between the auxiliary gate electrodes 127 and the charge storage layer 115.

Accordingly, the stacked structure of the tunnel insulating layer 110 / charge storage layer 115 / second blocking insulating layers 122 / auxiliary gate electrodes 127 may constitute other memory transistors. However, in a modified example of this embodiment, the tunnel insulating layer 110, the charge storage layer 115 and the second blocking insulating layers 122 under the auxiliary gate electrodes 127 may be replaced with a suitable insulating layer. have. In this case, the auxiliary gate electrodes 127 may form a MOS transistor.

In a modified example of this embodiment, auxiliary gate electrodes 127 may be further interposed between the select gate electrodes 145 and the control gate electrodes 140 instead of the spacer insulating layers 160. In this case, the source or drain region 150 between the select gate electrodes 145 and both ends of the control gate electrodes 140 may be omitted, and the channel region 155a may be extended.

4 is a partial equivalent circuit diagram of the nonvolatile memory device 300 of FIG. 3.

3 and 4, the control gate electrodes 140 and CG, the auxiliary gate electrodes 127 and SG, and the semiconductor substrates 105, S1, and S2 are capacitively coupled to each other. The control gate electrodes 140 and CG and the semiconductor substrate 105 and S1 form a first capacitor C1, and the auxiliary gate electrodes 127 and SG and the semiconductor substrate 105 and S2 are formed of a second capacitor ( Form C2). The control gate electrodes 140 and CG and the auxiliary gate electrodes 127 and SG form a third capacitor C3.

Therefore, by controlling the control gate electrodes 140 and CG, not only can the semiconductor substrate 105 and S1 be directly controlled thereunder, but also the semiconductor substrate beneath and capacitively coupled to the auxiliary gate electrode 127 and SG. 105 and S2 can be effectively controlled. Accordingly, compared to the embodiment of FIG. 1, it is possible to more easily control the turn-on of the channel region 155a under the auxiliary gate electrode 127 (SG).

Furthermore, by directly controlling the auxiliary gate electrodes 127 and SG, the semiconductor substrates 105 and S2 under the auxiliary gate electrodes 127 and S2 may be controlled more effectively. That is, an electrical signal may be directly applied to the auxiliary gate electrodes 127 and SG without floating the auxiliary gate electrodes 127 and SG.

Hereinafter, a method of operating the nonvolatile memory device 300 according to this embodiment will be described in more detail. In the program operation, data may be stored by storing charge in the charge storage layer 115. In a read operation, data stored in the charge storage layer 115 may be read. In an erase operation, data stored in the charge storage layer 115 may be erased.

According to an operating method according to an example, as described above, while the auxiliary gate electrodes 127 and SG are floated, the control gate electrodes 140 and CG and the semiconductor substrates 105, S1, and S2 are controlled by a program. , Read and erase operations can be performed. For example, the channel region 155a may be turned on by applying a first pass voltage and / or a program voltage to the control gate electrodes 140 and CG in a program and a read operation. For example, when the memory transistors have an n-type channel, the first pass voltage and the program voltage may be positive voltages.

According to an operation method according to another example, an electrical signal may be directly applied to the auxiliary gate electrodes 127 and SG. For example, in the program and read operations, the channel region 155a is applied by applying a first pass voltage to the control gate electrodes 140 and CG and a second pass voltage to the auxiliary gate electrodes 127 and SG. ) Can be turned on. In addition, the voltage applied to the auxiliary gate electrodes 127 and SG may increase channel boosting efficiency for program prevention. For example, the second pass voltage may be similar to the first pass voltage. As another example, the second pass voltage may be higher than the first pass voltage, in which case the channel boosting efficiency may be further improved. In the erase operation, an erase voltage may be applied to the semiconductor substrates 105, S1, and S2, and the control gate electrodes 140 and CG and the auxiliary gate electrodes 127 and SG may be grounded.

According to an operation method according to another example, the auxiliary gate electrodes 127 and SG may be controlled during a program operation to store charges in the charge storage layer 115 under the auxiliary gate electrodes 127 and SG. . In this case, the second blocking insulating layer 122 may increase the storage efficiency of the charge stored in the charge storage layer under the auxiliary gate electrodes 127 and SG.

The charge stored in the charge storage layer 115 under the auxiliary gate electrodes 127 (SG) prevents the charge stored in the charge storage layer 115 under the adjacent control gate electrodes 140 (CG) from moving sideways. Can be. This is because the electrons stored in the charge storage layer 115 under the auxiliary gate electrodes 127 and SG and the control gate electrodes 140 and CG are repulsive. Accordingly, data retention characteristics of the memory cell may be greatly improved.

For example, in a program operation, a first pass voltage and / or a program voltage is applied to the control gate electrodes 140 and CG, and a second pass voltage is applied to one or all of the auxiliary gate electrodes 127 and SG. Is applied. Accordingly, the charge is stored in the charge storage layer 115 under the control gate electrodes 140 and CG to which the program voltage is applied, and at the same time, the charge storage layer under one or all of the auxiliary gate electrodes 127 and SG. Other charges may be stored at 115.

In this case, the amount of charge stored in the charge storage layer 115 under the auxiliary gate electrodes 127 and SG is relative to the amount of charge stored in the charge storage layer 115 under the control gate electrodes 140 and CG. Can be as small as For example, the first pass voltage and the second pass voltage may be the same or similar. As another example, the second pass voltage may be appropriately adjusted to adjust the amount of charge stored in the charge storage layer 115 under the auxiliary gate electrodes 127 and SG.

Hereinafter, a method of manufacturing a nonvolatile memory device according to embodiments of the present invention will be described.

5 through 9 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a first embodiment of the present invention.

Referring to FIG. 5, a tunneling insulating layer 110 is formed on a semiconductor substrate 105. For example, the tunneling insulating layer 110 may be formed by thermally oxidizing the semiconductor substrate 105 or may be formed using chemical vapor deposition (CVD). Subsequently, the charge storage layer 115 is formed on the tunneling insulating layer 110. For example, the charge storage layer 115 may be formed using chemical vapor deposition.

Subsequently, a plurality of dummy mask layers 130 are formed on the charge storage layer 115. For example, the dummy mask layer 130 may include a lower mask layer 120 and an upper mask layer 125 thereon. For example, the lower mask layer 120 may include an oxide layer and the upper mask layer 125 may include a nitride layer.

Referring to FIG. 6, blocking insulating layers 135a and 135b having trenches are formed on the charge storage layer 115 so as to be limited between the dummy mask layers 130. Subsequently, the control gate electrodes 140 and the selection gate electrodes 145 are formed to fill the trenches of the blocking insulating layers 135a and 135b.

For example, an insulating layer (not shown) is covered to cover the dummy mask layers 130 and the exposed charge storage layer 115, and a conductive layer (not shown) is formed on the insulating layer. Next, the insulating layer and the conductive layer are planarized to expose the dummy mask layers 130. For example, planarization may use etch-back or chemical mechanical polishing (CMP). Accordingly, the blocking insulating layers 135a and 135b may be limited to the remaining insulating layer, and the control gate electrodes 140 and the selection gate electrodes 145 may be limited to the remaining conductive layer. Such a formation method can be called a damascene method.

Thus, according to this embodiment, the dry etching step may be omitted to pattern the blocking insulating layers 135a and 135b and the control gate electrodes 145. Therefore, the deterioration of reliability of the nonvolatile memory device caused by the etching defect of the conventional blocking insulating layers 135a and 135b, for example, the erase speed, may be prevented.

Referring to FIG. 7, dummy mask layers 130 on both sides of the selection gate electrodes 145 are selectively removed. Accordingly, the dummy mask layers 130 may remain between the control gate electrodes 140. For example, the dummy mask layers 130 may be removed using selective wet etching or dry etching, and in the case of using dry etching, an appropriate photoresist pattern may be used as a protective film.

Referring to FIG. 8, source or drain regions 150 are formed in the vicinity of the surface of the semiconductor substrate 105 on both sides of the selection gate electrodes 145. Accordingly, the channel region 155a may be continuously defined near the surface of the semiconductor substrate 105 under the control gate electrodes 140 without the source or drain region.

For example, the source or drain region 150 may be formed by implanting impurities of the second conductivity type into the semiconductor substrate 105 of the first conductivity type. Such impurity implantation may be performed using an ion implantation apparatus.

Referring to FIG. 9, spacer insulating layers 160 are formed on both sidewalls of the selection gate electrodes 145. In addition, spacer insulating layers 160 may be formed on the outermost sidewalls of the control gate electrodes 140. For example, the spacer insulating layers 160 may be formed by depositing an insulating layer and anisotropic etching them. In this case, a void may be defined between the spacer insulating layers 160 between the selection gate electrodes 145 and the control gate electrodes 140 at both ends, depending on the edge coating ability of the insulating layer.

Thereafter, the nonvolatile memory device may be completed according to a method known to those skilled in the art.

10 through 12 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a second embodiment of the present invention. The manufacturing steps of FIGS. 10 to 12 may proceed following the manufacturing steps of FIGS. 5 and 6 of the first embodiment described above, and thus may correspond to variations of FIGS. 7 to 9. Thus, duplicate descriptions are omitted in both embodiments.

Referring to FIG. 10, dummy mask layers 130 on both sides of the selection gate electrodes 145 may be removed, and both pairs of control gate electrodes 140 on both ends of the control gate electrodes 140 may be removed. The dummy mask layers 130 are also removed. Accordingly, the dummy mask layers 130 may remain between the rest except the control gate electrodes 140 at both ends.

Referring to FIG. 11, near the surface of the semiconductor substrate 105 on both sides of the selection gate electrodes 145 and near the surface of the semiconductor substrate 105 on both sides of the pair of control gate electrodes 140 at both ends. , Source or drain regions 150 are formed, respectively. Accordingly, the channel region 155b may be continuously defined to the semiconductor substrate 105 under the control gate electrodes 140 except for the pair of control gate electrodes 140 at both ends.

Referring to FIG. 12, spacer insulating layers 160 are formed on both sidewalls of the selection gate electrodes 145 and both sidewalls of the pair of control gate electrodes 140 at both ends. In addition, spacer insulating layers 160 may be formed on the outermost sidewalls of the remaining control gate electrodes 140.

13 to 16 are cross-sectional views illustrating a method of manufacturing a nonvolatile memory device in accordance with a third embodiment of the present invention. 13 to 16 may correspond to variations of FIGS. 5 to 9 of the above-described first embodiment. Thus, duplicate descriptions are omitted in both embodiments.

Referring to FIG. 13, in the steps of FIGS. 5 and 6, instead of the dummy mask layer 130, the second blocking insulating layers 122 and the auxiliary gate electrodes 127 are formed. For example, the lower mask layers 120 may be replaced with the second blocking insulating layers 122, and the upper mask layers 125 may be replaced with the auxiliary gate electrodes 127.

14 to 16 can be easily implemented by referring to FIGS. 7 to 9, respectively.

17 is a cross-sectional view illustrating a stacked structure 400 of a nonvolatile memory device according to a fourth embodiment of the present invention.

Referring to FIG. 17, the stacked structure 400 may use the nonvolatile memory devices 100 of FIG. 1 as a unit layer structure. The nonvolatile memory devices 100 having a unit layer structure may be stacked on each other. The number of nonvolatile memory devices 100 having a stacked unit layer structure is illustrated as an example, and thus may be two or more.

The bit line electrode 430 and the common source line electrode 405 may be connected to the nonvolatile memory devices 100 having a unit layer structure, respectively. For example, the bit line electrode 430 and the common source line electrode 405 may be connected to source or drain regions 150 at both ends of the control gate electrodes 140, respectively. The bit line electrode 430 may be connected to the source or drain region 150 through the plug 410.

The first interlayer insulating layer 420 may be interposed between the bit line electrode 430 and the control gate electrodes 140. In addition, a second interlayer insulating layer 440 may be interposed between the nonvolatile memory devices 100 having a unit layer structure.

For example, the bit line electrode 430, the common source line electrode 405, and the plug 410 may include a metal, a metal nitride film, or a stack structure thereof. For example, the metal may include tungsten (W), aluminum (Al), or copper (Cu), and the metal nitride film may include a titanium nitride film TiN0 or a tantalum nitride film TaN. The first and second interlayer insulating layers 420 and 440 may include an oxide film, a low-k dielectric layer, or a stack structure thereof, and the oxide film may include SiO ₂ or BPSG.

In the stacked structure 400, it is apparent that the nonvolatile memory devices 100 of the unit layer structure may be replaced with any one of the nonvolatile memory devices 200 and 300 of FIG. 2 or 3.

18 is a block diagram illustrating a system 500 using a nonvolatile memory device according to a fifth embodiment of the present invention.

Referring to FIG. 18, the controller 510, the input / output unit 520, the memory unit 530, and the interface unit 540 may be combined using the bus 550. The controller 510 may include at least one processor for executing an instruction, for example, a microprocessor, a digital signal processor, or a microcontroller.

The input / output unit 520 may receive data or a signal from the outside of the system 500 or output data or a signal to the outside of the system 500. For example, the input / output unit 520 may include a keyboard, a keypad, or a display element. The memory unit 530 may store a command performed by the controller 510. For example, the memory unit 530 may include any one of the nonvolatile memory devices 100, 200, and 300 of FIGS. 1 to 3 or the stacked structure 400 of FIG. 17. The interface unit 540 may communicate with a network to exchange data.

For example, system 500 may be used in mobile systems, such as PDAs, portable computers, web tablets, wireless phones, mobile phones, digital music players, memory cards, or data transmission or receivers. Can be.

The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. The present invention is not limited to the above embodiments, and various modifications and changes can be made by those skilled in the art within the technical spirit of the present invention.

According to the nonvolatile memory device according to the present invention, it is possible to reduce the volume of the memory cell as compared with the prior art, and as a result, the degree of integration can be significantly increased.

In addition, according to the nonvolatile memory device according to the present invention, since the charge storage layer does not extend in the direction of the sidewalls of the control gate electrodes, the data retention characteristics can be significantly improved compared with the related art. Therefore, the nonvolatile memory device according to the present invention can have high reliability compared to the prior art.

In addition, according to the nonvolatile memory device according to the present invention, the source or drain region can be omitted in the memory cell. Therefore, the leakage current and the off current of the nonvolatile memory device can be reduced as compared with the prior art.

Claims (42)

A plurality of control gate electrodes arranged in series on the semiconductor substrate; A charge storage layer interposed between the semiconductor substrate and the plurality of control gate electrodes; A tunneling insulating layer interposed between the semiconductor substrate and the plurality of charge storage layers; And And a plurality of blocking insulating layers interposed between the charge storage layers and the plurality of control gate electrodes, respectively, and extending to cover both sidewalls of the plurality of control gate electrodes. . The nonvolatile memory device of claim 1, wherein the plurality of blocking insulating layers include trenches defined at opposite sides of the charge storage layer, and the control gate electrode is formed by filling the trenches. The nonvolatile memory device of claim 1, further comprising a pair of select gate electrodes on the semiconductor substrate, respectively disposed at both ends of the plurality of control gate electrodes. The nonvolatile memory device of claim 2, wherein the tunneling insulating layer and the charge storage layer are further extended between the pair of gate electrodes and the semiconductor substrate. The semiconductor device of claim 3, wherein a source or drain region is respectively defined near the surface of the semiconductor substrate on both sides of the pair of select gate electrodes, and a channel region is continuously formed near the surface of the semiconductor substrate under the plurality of control gate electrodes. Non-volatile memory device, characterized in that limited. 4. The nonvolatile memory device of claim 3, further comprising a plurality of dummy mask layers interposed between two adjacent ones of the plurality of blocking insulating layers. The nonvolatile memory device of claim 6, further comprising spacer insulating layers formed on both sidewalls of the pair of select gate electrodes. The semiconductor device of claim 6, wherein the dummy mask layer includes a lower mask layer having an etch selectivity with respect to the charge storage layer, and the plurality of blocking insulating layers and the plurality of control gate electrodes disposed on the lower mask layer. And an upper mask layer having an etch selectivity with respect to the non-volatile memory device. 4. A source or drain region according to claim 3, wherein a source or a drain region is provided on both sides of the pair of select gate electrodes and on the surface of the semiconductor substrate on both sides of the pair of control gate electrodes disposed at both ends of the plurality of control gate electrodes. And a channel region is continuously defined near the surface of the semiconductor substrate under the remaining control gate electrodes except for the pair of control gate electrodes disposed at both ends. 10. The nonvolatile memory device of claim 9, further comprising a plurality of dummy mask layers interposed between two adjacent ones of the plurality of blocking insulating layers on the channel region. 10. The nonvolatile memory device of claim 9, further comprising spacer insulating layers formed on both sidewalls of the pair of select gate electrodes and both sidewalls of the pair of control gate electrodes disposed at both ends. . The nonvolatile memory device of claim 1, wherein the charge storage layer comprises a nitride film, polysilicon, dots, or nanocrystals. A plurality of control gate electrodes arranged in series on the semiconductor substrate; A charge storage layer interposed between the semiconductor substrate and the plurality of control gate electrodes; A tunneling insulating layer interposed between the semiconductor substrate and the charge storage layer; A plurality of blocking insulating layers respectively interposed between the charge storage layer and the plurality of control gate electrodes; And And a plurality of auxiliary gate electrodes respectively interposed between adjacent two of the plurality of control gate electrodes. The nonvolatile memory device of claim 13, wherein the plurality of blocking insulating layers are further extended between the plurality of auxiliary gate electrodes and the plurality of control gate electrodes, respectively. 15. The nonvolatile device of claim 14, wherein the plurality of blocking insulating layers includes a plurality of trenches defined on opposite sides of the tunneling insulating layer, and the plurality of control gate electrodes are formed to respectively fill the plurality of trenches. Memory elements. The nonvolatile memory device of claim 13, wherein the tunneling insulating layer and the charge storage layer are further extended between the plurality of auxiliary gate electrodes and the semiconductor substrate. 17. The nonvolatile memory device of claim 16, further comprising a plurality of second blocking insulating layers respectively interposed between the plurality of auxiliary gate electrodes and the tunneling insulating layer. 15. The nonvolatile memory device of claim 13, further comprising a pair of select gate electrodes on the semiconductor substrate, each of which is disposed at both ends of the plurality of control gate electrodes. 19. The semiconductor device of claim 18, wherein a source or a drain region is defined around the surface of the semiconductor substrate on both sides of the pair of select gate electrodes, and the semiconductor under the plurality of control gate electrodes and the plurality of auxiliary gate electrodes. Non-volatile memory device, characterized in that the channel region is continuously defined in the vicinity of the substrate surface. 20. The nonvolatile memory device of claim 19, further comprising spacer insulating layers formed on both sidewalls of the pair of select gate electrodes. The method of claim 13, further comprising a pair of control gate electrodes disposed at both ends of the plurality of control gate electrodes, and a pair of auxiliary gate electrodes interposed between the pair of select gate electrodes. Non-volatile memory device characterized in that. An operating method using the nonvolatile memory device of claim 13, A program step of storing data in a portion of the charge storage layer below the plurality of control gate electrodes; A read step of reading data stored in the charge storage layer; And An erase step of erasing data stored in the charge storage layer; In the programming and reading steps, a first pass voltage is applied to the plurality of control gate electrodes to turn channel regions of the semiconductor substrate under the plurality of control gate electrodes and the plurality of auxiliary gate electrodes. Operating method of a nonvolatile memory device, characterized in that the on. 23. The method of claim 22, wherein in the program step, the read step, and the erase step, the plurality of auxiliary gate electrodes are floated. 23. The method of claim 22, wherein a second pass voltage is applied to the plurality of auxiliary gate electrodes in the program step and the read step. 25. The method of claim 24, wherein in the erase step, an erase voltage is applied to the semiconductor substrate, and the control gate electrodes and the plurality of auxiliary gate electrodes are grounded. The semiconductor device of claim 24, wherein the tunnel insulating layer and the charge storage layer extend between the plurality of auxiliary gate electrodes and the semiconductor substrate. In the programming step, a charge is stored in a portion of the charge storage layer between at least one of the auxiliary gate electrodes and the semiconductor substrate. Forming a tunneling insulating layer on the semiconductor substrate; Forming a charge storage layer on the tunneling insulating layer; Forming a plurality of blocking insulating layers each having a trench defined on an opposite side of the charge storage layer, on the charge storage layer; And And forming a plurality of control gate electrodes to fill the trenches of the plurality of blocking insulating layers. 28. The method of claim 27, prior to forming the blocking insulating layer, And forming a plurality of dummy mask layers on the tunneling insulating layer so as to be defined between adjacent two of the plurality of blocking insulating layers, respectively. 29. The plurality of dummy mask layers of claim 28, wherein the plurality of dummy mask layers are disposed on the lower mask layer and the lower mask layer having an etch selectivity with respect to the charge storage layer, and the blocking insulating layers and the plurality of control gate electrodes. And an upper mask layer having an etch selectivity with respect to each other. 28. The method of claim 27, wherein after forming the plurality of blocking insulating films, And forming a pair of select gate electrodes at both ends of the plurality of control gate electrodes. 31. The semiconductor device of claim 30, further comprising: defining a source or drain region near the semiconductor substrate surface on both sides of the pair of select gate electrodes at both ends, and a channel region near the surface of the semiconductor substrate under the plurality of control gate electrodes. A method of manufacturing a nonvolatile memory device, characterized in that it further comprises the step of continuously defining. 32. The method of claim 31, further comprising forming spacer insulating films on both sidewalls of the pair of select gate electrodes at both ends. 31. The semiconductor device of claim 30, further comprising: defining a source or drain region on both sides of the pair of control gate electrodes disposed near both the semiconductor substrate surface of the pair of select gate electrodes and at both ends of the plurality of control gate electrodes. And continuously defining a channel region near the surface of the semiconductor substrate of the remaining control gate electrodes except for the pair of control gate electrodes. 34. The method of claim 33, further comprising forming spacer insulating films on both sidewalls of the pair of select gate electrodes and both sidewalls of the pair of control gate electrodes disposed at both ends thereof. Method of manufacturing volatile memory device. 28. The method of claim 27, prior to forming the blocking insulating layer, And forming a plurality of auxiliary gate electrodes on the tunneling insulating layer so as to be defined between adjacent two of the plurality of blocking insulating layers, respectively. 36. The method of claim 35, further comprising forming a plurality of second blocking insulating layers between the plurality of auxiliary gate electrodes and the tunneling insulating layer, respectively. A stack structure of a nonvolatile memory device according to any one of claims 1 to 21, wherein a plurality of the unit layer structures are stacked on each other by using the nonvolatile memory device as a unit layer structure. 38. The stacked structure of claim 37, further comprising an interlayer insulating layer interposed between the plurality of unit layer structures. 38. The nonvolatile memory device of claim 37, wherein the plurality of unit layer structures further include a bit line electrode and a common source line electrode respectively connected to the semiconductor substrate at both ends of the plurality of control gate electrodes. Laminated structure. A control unit for performing a command; 22. A memory device comprising: the nonvolatile memory device of any one of claims 1 to 21 for storing the command; And And an input / output unit coupled to the memory unit or the control unit. 41. The system of claim 40, further comprising an interface portion coupled to the control portion or memory portion for communicating with a network. 41. The system of claim 40, wherein the control unit, the memory unit, the input / output unit and the interface unit are coupled to each other via a bus.

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