CN113782437A - Method for manufacturing flash memory - Google Patents
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- CN113782437A CN113782437A CN202110928065.2A CN202110928065A CN113782437A CN 113782437 A CN113782437 A CN 113782437A CN 202110928065 A CN202110928065 A CN 202110928065A CN 113782437 A CN113782437 A CN 113782437A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 52
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 51
- 229920005591 polysilicon Polymers 0.000 claims abstract description 36
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 238000001259 photo etching Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 13
- 238000002955 isolation Methods 0.000 claims description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
Abstract
The invention discloses a method for manufacturing a flash memory, which comprises the following steps: step one, forming a first gate dielectric layer and a first polysilicon layer; step two, forming a hard mask layer; defining a source line forming area by photoetching, carrying out first etching to form a source line opening, and forming a first side surface of the word line polysilicon gate in the first etching; step four, forming a source region; fifthly, forming a first inter-gate dielectric layer and a floating gate on the side surface of the source line opening; sixthly, forming a second inter-gate dielectric layer and a control gate in the source line opening; step seven, forming a third inter-gate dielectric layer and a conductive material layer of the erasing gate, and carrying out photoetching definition and etching to form the erasing gate; removing the hard mask layer to form a first side wall; and step nine, carrying out second etching on the first polysilicon layer and the first gate dielectric layer by taking the first side wall as a self-alignment condition to form a second side surface of the word line polysilicon gate. The invention can self-align to form word line polysilicon gate, reduce photomask level and reduce process cost.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a flash memory.
Background
Fig. 1 is a schematic structural diagram of a conventional 38-flash super memory (SF); the existing 38 super flash memory includes:
a first gate dielectric layer (not shown) and a Word Line (WL) polysilicon gate 102 are formed on a semiconductor substrate 101.
The Floating Gate (FG)104 is composed of a TiN layer. An inter-gate dielectric layer 103 is isolated between the floating gate 104 and the word line polysilicon gate 102.
A Control Gate (CG)106 is formed above the source region 109, and the control gate 106 simultaneously serves as a Source Line (SL).
An intergate dielectric layer 105 is isolated between the control gate 106 and the floating gate 104.
The erase gate 108 covers the top of the control gate 106 and the floating gate 104 and an intergate dielectric layer 107 is isolated between the erase gate 108 and the bottom of the control gate 106 and the floating gate 104.
Lightly doped drain regions 110a and drain regions 110 are also formed in the semiconductor substrate 101 at the sides of the word line polysilicon gate 102 in a self-aligned manner.
Compared with the 3 rd generation SF structure in the industry, 38SF utilizes the writing operation of a horizontal electric field and the erasing operation without voltage coupling of the tip TiN, so that the erasing efficiency is greatly improved, and the operating voltage is reduced. This structure increases the nested window of EG on FG and better tip control, better Endurance (edge) performance.
Disclosure of Invention
The present invention provides a method for manufacturing a flash memory, which can self-align to form word line polysilicon gate, reduce photomask level and thus reduce process cost.
In order to solve the above technical problem, the method for manufacturing a flash memory provided by the present invention comprises the following steps:
step one, forming a first gate dielectric layer and a first polysilicon layer on a semiconductor substrate.
And step two, forming a hard mask layer on the top of the first polycrystalline silicon layer.
Defining a source line forming area by photoetching, sequentially etching the hard mask layer, the first polycrystalline silicon layer and the first gate dielectric layer for the first time according to the photoetching definition to form a source line opening, wherein the bottom of the source line opening exposes the surface of the semiconductor substrate; and the side surface of the first polycrystalline silicon layer formed by the first etching is the first side surface of the word line polycrystalline silicon gate.
And fourthly, forming a source region in the semiconductor substrate at the bottom of the source line opening.
Fifthly, forming a first inter-gate dielectric layer and a floating gate consisting of a TiN layer on the side surface of the source line opening; the first inter-gate dielectric layer realizes the isolation between the floating gate and the word line polysilicon gate, and the first inter-gate dielectric layer is also positioned on the surface of the semiconductor substrate at the bottom of the floating gate to realize the isolation between the floating gate and the source region.
Sixthly, forming a second inter-gate dielectric layer and a control gate consisting of a conductive material layer in the source line opening formed with the first inter-gate dielectric layer and the floating gate; and the second inter-gate dielectric layer realizes the isolation between the control gate and the floating gate.
Step seven, forming a third inter-gate dielectric layer and a conductive material layer of the erasing gate, defining a forming area of the erasing gate by photoetching, and etching the third inter-gate dielectric layer and the conductive material layer of the erasing gate to form the erasing gate; the erasing gate is positioned at the tops of the floating gate and the control gate, and the covering area of the erasing gate is larger than the forming area of the source line opening.
And step eight, removing the hard mask layer to form first side walls, wherein the first side walls are formed on the side surfaces of the erasing gates and the side surfaces of the first inter-gate dielectric layers at the bottoms of the erasing gates.
And ninthly, performing second etching on the first polycrystalline silicon layer and the first gate dielectric layer by taking the first side wall as a self-alignment condition, wherein the side surface of the first polycrystalline silicon layer formed by the second etching is the second side surface of the word line polycrystalline silicon gate.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In a further improvement, the first gate dielectric layer comprises an oxide layer.
In a further improvement, the hard mask layer is formed by stacking a first nitride layer and a second oxide layer.
The further improvement is that the first etching of the third step comprises the following sub-steps:
and etching the hard mask layer in sequence according to the photoetching definition.
And forming a second side wall on the side surface of the hard mask layer.
And etching the first polysilicon layer and the first gate dielectric layer by taking the second side wall as a self-alignment condition to form the source line opening.
In a further improvement, in the first etching, after the etching of the first gate dielectric layer is completed, the method further comprises the step of over-etching the semiconductor substrate.
The further improvement is that before the over-etching of the first etching, the method further comprises the step of forming a third side wall on the side surface of the second side wall and the first side surface of the word line polysilicon gate, and then the over-etching of the first etching is carried out by taking the third side wall as a self-alignment condition.
In a further improvement, the top surface of the floating gate is higher than the top surface of the control gate, the floating gate forming a tip structure over the top surface of the control gate.
In a further improvement, the conductive material layer of the control gate is made of tungsten.
In a further improvement, a plurality of cell structures of the flash memory are formed on the semiconductor substrate, and one source region is shared by two adjacent cell structures.
In a further improvement, the method further comprises the following step after the ninth step:
and performing N + injection by taking the second side surface of the word line polysilicon gate as a self-alignment condition to form a drain region.
In a further improvement, the flash memory is a 38-flash-super memory.
In a further improvement, the material of the first sidewall comprises an oxide layer.
In a further improvement, the material of the second sidewall comprises an oxide layer.
In a further improvement, the material of the third sidewall comprises an oxide layer.
The further improvement is that the material of the first inter-gate dielectric layer comprises an oxide layer;
the material of the second inter-gate dielectric layer comprises an oxide layer;
the material of the third inter-gate dielectric layer comprises an oxide layer.
In the invention, the first side surface of the word line polysilicon gate is formed by self-aligning the photomask with the source line opening, the first side surface of the word line polysilicon gate does not need to be defined by independently adopting the photomask, and the second side surface of the word line polysilicon gate is defined by self-aligning the first side wall formed on the side surface of the erasing gate after the erasing gate is formed.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a conventional 38 super flash memory;
FIG. 2 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the present invention;
fig. 3A-3F are schematic diagrams of device structures in steps of a method for manufacturing a flash memory according to an embodiment of the invention.
Detailed Description
FIG. 2 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the present invention; fig. 3A to 3F are schematic diagrams of device structures in the steps of the method for manufacturing a flash memory according to the embodiment of the invention; the flash memory of the embodiment of the invention is a 38 super flash memory, and the manufacturing method of the flash memory of the embodiment of the invention comprises the following steps:
in step one, as shown in fig. 3A, a first gate dielectric layer (not shown) and a first polysilicon layer 202 are formed on a semiconductor substrate 201.
In the embodiment of the present invention, the semiconductor substrate 201 includes a silicon substrate.
The first gate dielectric layer comprises an oxide layer.
Step two, as shown in fig. 3A, a hard mask layer is formed on top of the first polysilicon layer 202.
In the embodiment of the present invention, the hard mask layer is formed by stacking a first nitride layer 203 and a second oxide layer 204.
Step three, defining a source line forming area by photoetching, sequentially etching the hard mask layer, the first polycrystalline silicon layer 202 and the first gate dielectric layer for the first time according to the photoetching definition to form a source line opening, wherein the bottom of the source line opening exposes the surface of the semiconductor substrate 201; the side surface of the first polysilicon layer 202 formed by the first etching is the first side surface of the word line polysilicon gate 202 a.
In the embodiment of the invention, the first etching comprises the following sub-steps:
and etching the hard mask layer in sequence according to the photoetching definition.
A second sidewall 205 is formed on the side of the hard mask layer.
And etching the first polysilicon layer 202 and the first gate dielectric layer by taking the second side wall 205 as a self-alignment condition to form the source line opening.
Before the over-etching of the first etching, a step of forming a third sidewall 206 on the side surface of the second sidewall 205 and the first side surface of the word line polysilicon gate 202a is further included, and then the over-etching of the first etching is performed with the third sidewall 206 as a self-aligned condition.
In the first etching, after the etching of the first gate dielectric layer is completed, the method further includes a step of over-etching the semiconductor substrate 201.
The second side wall 205 is made of an oxide layer. The third sidewall 206 is made of an oxide layer. In fig. 3A, the second sidewall 205, the third sidewall 206 and the second oxide layer 204 are a unitary structure.
Step four, as shown in fig. 3B, a source region 207 is formed in the semiconductor substrate 201 at the bottom of the source line opening.
In the embodiment of the present invention, a plurality of cell structures of the flash memory are formed on the semiconductor substrate 201, and one source region 207 is shared by two adjacent cell structures.
Step five, as shown in fig. 3B, forming a first inter-gate dielectric layer 208 and a floating gate 209 made of a TiN layer on the side surface of the source line opening; the first inter-gate dielectric layer 208 is used for realizing the isolation between the floating gate 209 and the word line polysilicon gate 202a, and the first inter-gate dielectric layer 208 is also positioned on the surface of the semiconductor substrate 201 at the bottom of the floating gate 209 for realizing the isolation between the floating gate 209 and the source region 207.
In the embodiment of the present invention, the first inter-gate dielectric layer 208 is made of an oxide layer, and the second sidewall 205, the third sidewall 206 and the first inter-gate dielectric layer 208 which are the oxide layer are integrated.
Sixthly, as shown in fig. 3B, forming a second inter-gate dielectric layer 210 and a control gate 211 made of a conductive material layer in the source line opening where the first inter-gate dielectric layer 208 and the floating gate 209 are formed; the second intergate dielectric layer 210 provides isolation between the control gate 211 and the floating gate 209.
In the embodiment of the present invention, the top surface of the floating gate 209 is higher than the top surface of the control gate 211, and the floating gate 209 forms a tip structure over the top surface of the control gate 211.
The conductive material layer of the control gate 211 is made of tungsten.
The material of the second inter-gate dielectric layer 210 includes an oxide layer.
Step seven, as shown in fig. 3B, forming a conductive material layer of the third inter-gate dielectric layer 212 and the erase gate 213, defining a forming area of the erase gate 213 by photolithography, and etching the conductive material layer of the third inter-gate dielectric layer 212 and the erase gate 213 to form the erase gate 213; the erasing gate 213 is positioned on the top of the floating gate 209 and the control gate 211, and the coverage area of the erasing gate 213 is larger than the formation area of the source line opening.
In an embodiment of the present invention, the material of the third inter-gate dielectric layer 212 includes an oxide layer.
A top oxide layer 214 is also formed on the top of the conductive material layer of the erase gate 213; the photolithography process forms a pattern structure of the photoresist 215; the etching is performed by etching the top oxide layer 214 and then etching the bottom conductive material layer of the erase gate 213. The second oxide layer 204 of the hard mask layer is substantially removed.
And step eight, as shown in fig. 3C, removing the hard mask layer. Since the second oxide layer 204 has been substantially removed, the first nitride layer 203 is mainly removed at this time. After that, the photoresist 215 is removed.
As shown in fig. 3D, a first sidewall 216 is formed, where the first sidewall 216 is formed on the side surface of the erase gate 213 and the side surface of the first inter-gate dielectric layer 208 at the bottom of the erase gate 213.
The material of the first sidewall spacers 216 includes an oxide layer.
Step nine, as shown in fig. 3E, performing a second etching on the first polysilicon layer 202 and the first gate dielectric layer under the self-aligned condition of the first sidewall 216, where a side surface of the first polysilicon layer 202 formed by the second etching is a second side surface of the word line polysilicon gate 202 a.
The ninth step is followed by:
and performing N + implantation with the second side of the word line polysilicon gate 202a as a self-aligned condition to form a drain region 219. Typically, a step of forming Lightly Doped Drain (LDD) regions 218 is also included prior to forming the drain regions 219.
In the embodiment of the present invention, the first side surface of the word line polysilicon gate 202a is formed by self-aligning the mask with the source line opening, and it is not necessary to separately define the first side surface of the word line polysilicon gate 202a by using the mask, and the second side surface of the word line polysilicon gate 202a is defined by self-aligning the first sidewall 216 formed on the side surface of the erase gate 213 after the erase gate 213 is formed.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (16)
1. A method for manufacturing a flash memory, comprising the steps of:
forming a first gate dielectric layer and a first polysilicon layer on a semiconductor substrate;
secondly, forming a hard mask layer on the top of the first polycrystalline silicon layer;
defining a source line forming area by photoetching, sequentially etching the hard mask layer, the first polycrystalline silicon layer and the first gate dielectric layer for the first time according to the photoetching definition to form a source line opening, wherein the bottom of the source line opening exposes the surface of the semiconductor substrate; the side surface of the first polycrystalline silicon layer formed by the first etching is the first side surface of the word line polycrystalline silicon gate;
forming a source region in the semiconductor substrate at the bottom of the source line opening;
fifthly, forming a first inter-gate dielectric layer and a floating gate consisting of a TiN layer on the side surface of the source line opening; the first inter-gate dielectric layer realizes the isolation between the floating gate and the word line polysilicon gate, and the first inter-gate dielectric layer is also positioned on the surface of the semiconductor substrate at the bottom of the floating gate to realize the isolation between the floating gate and the source region;
sixthly, forming a second inter-gate dielectric layer and a control gate consisting of a conductive material layer in the source line opening formed with the first inter-gate dielectric layer and the floating gate; the second inter-gate dielectric layer realizes isolation between the control gate and the floating gate;
step seven, forming a third inter-gate dielectric layer and a conductive material layer of the erasing gate, defining a forming area of the erasing gate by photoetching, and etching the third inter-gate dielectric layer and the conductive material layer of the erasing gate to form the erasing gate; the erasing gate is positioned at the tops of the floating gate and the control gate, and the covering area of the erasing gate is larger than the forming area of the source line opening;
removing the hard mask layer to form a first side wall, wherein the first side wall is formed on the side surface of the erasing gate and the side surface of the first inter-gate dielectric layer at the bottom of the erasing gate;
and ninthly, performing second etching on the first polycrystalline silicon layer and the first gate dielectric layer by taking the first side wall as a self-alignment condition, wherein the side surface of the first polycrystalline silicon layer formed by the second etching is the second side surface of the word line polycrystalline silicon gate.
2. The method of manufacturing a flash memory according to claim 1, wherein: the semiconductor substrate includes a silicon substrate.
3. The method of manufacturing a flash memory according to claim 1, wherein: the first gate dielectric layer comprises an oxide layer.
4. The method of manufacturing a flash memory according to claim 1, wherein: the hard mask layer is formed by overlapping a first nitride layer and a second oxide layer.
5. The method of manufacturing a flash memory according to claim 4, wherein: the first etching of the third step comprises the following sub-steps:
etching the hard mask layer in sequence according to the photoetching definition;
forming a second side wall on the side face of the hard mask layer;
and etching the first polysilicon layer and the first gate dielectric layer by taking the second side wall as a self-alignment condition to form the source line opening.
6. The method of manufacturing a flash memory according to claim 5, wherein: in the first etching, after the etching of the first gate dielectric layer is completed, the method further comprises the step of over-etching the semiconductor substrate.
7. The method of manufacturing a flash memory according to claim 6, wherein: before the first etching over-etching, a step of forming a third side wall on the side surface of the second side wall and the first side surface of the word line polysilicon gate is further included, and then the first etching over-etching is performed with the third side wall as a self-alignment condition.
8. The method of manufacturing a flash memory according to claim 6, wherein: the top surface of the floating gate is higher than the top surface of the control gate, the floating gate forming a tip structure over the top surface of the control gate.
9. The method of manufacturing a flash memory according to claim 8, wherein: and the conductive material layer of the control gate adopts tungsten.
10. The method of manufacturing a flash memory according to claim 1, wherein: a plurality of unit structures of the flash memory are formed on the semiconductor substrate, and one source region is shared by two adjacent unit structures.
11. The method of manufacturing a flash memory according to claim 10, wherein: the ninth step is followed by:
and performing N + injection by taking the second side surface of the word line polysilicon gate as a self-alignment condition to form a drain region.
12. The method of manufacturing a flash memory according to claim 1, wherein: the flash memory is 38 super flash.
13. The method of manufacturing a flash memory according to claim 1, wherein: the material of the first side wall comprises an oxide layer.
14. The method of manufacturing a flash memory according to claim 5, wherein: the second side wall is made of an oxide layer.
15. The method of manufacturing a flash memory according to claim 7, wherein: the third side wall is made of an oxide layer.
16. The method of manufacturing a flash memory according to claim 1, wherein: the material of the first inter-gate dielectric layer comprises an oxide layer;
the material of the second inter-gate dielectric layer comprises an oxide layer;
the material of the third inter-gate dielectric layer comprises an oxide layer.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050012137A1 (en) * | 2003-07-18 | 2005-01-20 | Amitay Levi | Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing |
| CN103021952A (en) * | 2012-12-20 | 2013-04-03 | 上海宏力半导体制造有限公司 | Split gate flash memory and forming method thereof |
| US20200303387A1 (en) * | 2019-03-20 | 2020-09-24 | Greenliant Ip, Llc | Process for Manufacturing NOR Memory Cell with Vertical Floating Gate |
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2021
- 2021-08-12 CN CN202110928065.2A patent/CN113782437A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050012137A1 (en) * | 2003-07-18 | 2005-01-20 | Amitay Levi | Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing |
| CN103021952A (en) * | 2012-12-20 | 2013-04-03 | 上海宏力半导体制造有限公司 | Split gate flash memory and forming method thereof |
| US20200303387A1 (en) * | 2019-03-20 | 2020-09-24 | Greenliant Ip, Llc | Process for Manufacturing NOR Memory Cell with Vertical Floating Gate |
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