KR20060081003A - Method of forming nand-type non-volatile memory device - Google Patents

Abstract

Disclosed are a highly integrated NAND type nonvolatile memory device capable of preventing leakage current, and a method of forming the same. The device may include a plurality of device isolation films formed on a semiconductor substrate and defining a plurality of parallel device isolation layers; Recessed regions formed in predetermined portions of the active region and having islands and isolated from each other; A string select line and a ground select line across the device isolation layer and the recessed regions, and a plurality of parallel word lines interposed between the lines, wherein each of the lines is formed of the recessed regions. A tunnel oxide film conformally covering the inner wall and the bottom; A floating gate positioned on the tunnel oxide layer and filling at least a top recessed region; And a gate interlayer insulating film and a control gate film on the floating gate.

NAND Nonvolatile Memory, Recessed Region

Description

Method of forming NAND type non-volatile memory device {Method of forming NAND-type non-volatile memory device}

1 and 2 are cross-sectional views sequentially illustrating a method of forming a NAND type nonvolatile memory device according to an embodiment of the present invention.

The present invention relates to a method of forming a semiconductor device, and more particularly, to a method of forming a NAND type nonvolatile memory device.

Non-volatile memory devices, such as flash memory devices having a NAND type memory cell configuration, program electrons into a floating gate using FN tunneling (Fowler / Nordheim tunneling), program the electrons, and extract and erase the electrons. As the operation is performed through the erasing process, the power consumption is lower than that of the NOR flash memory device. In addition, a plurality of memory cell transistors are connected in series in a cell string connected to a bit line. During reading, a read voltage is applied to a gate of a select transistor, and the remaining cell transistors are read. As the high voltage is applied to the circuit, the current flowing in the cell string is also reduced, which consumes less power. In addition, since the number of cell transistors in the cell string is limited, the sector size is smaller than that of the NOR type nonvolatile memory element, and the erase unit is also small. According to such a feature, a NAND type nonvolatile memory device has been widely used in recent years.

Meanwhile, as semiconductor devices are highly integrated, various methods for reducing the size of NAND type nonvolatile memory devices have been studied. However, as NAND type nonvolatile memory devices are highly integrated, there is an increased risk of leakage current.

Accordingly, an aspect of the present invention is to provide a highly integrated NAND type nonvolatile memory device capable of preventing leakage current and a method of forming the same.

According to an aspect of the present invention, a NAND type nonvolatile memory device includes: a plurality of device isolation layers formed on a semiconductor substrate and defining an active region; Recessed regions formed in predetermined portions of the active region and having islands and isolated from each other; A string select line and a ground select line across the device isolation layer and the recessed regions and a plurality of parallel word lines interposed between the lines, wherein each of the lines is formed of the recessed regions. A tunnel oxide film conformally covering the inner wall and the bottom; A floating gate positioned on the tunnel oxide layer and filling at least a top recessed region; And a gate interlayer insulating film and a control gate film on the floating gate.                     

The device may include a low concentration impurity implantation region located in the active region on both sides of the respective lines; A spacer covering sidewalls of the lines; And a high concentration impurity implantation region located in the active region adjacent to the spacer. The floating gate layer and the control gate layer may be in contact with each other in the ground selection line and the string selection line.

In the device, since the tunnel oxide film is conformally formed along the inner wall and the bottom of the recessed region, the channel length is increased to prevent the leakage current. In addition, when the device structure is applied, horizontal and vertical sizes can be reduced.

The method of forming the device is as follows. First, a plurality of device isolation layers parallel to each other are formed on a semiconductor substrate to define an active region. Certain portions of the active region are etched to form recessed regions having a plurality of island shapes and isolated from each other. A thermal oxidation process is performed to form a tunnel oxide film. A floating gate layer is formed to cover the active region and expose the device isolation layers. A gate interlayer insulating film is formed to expose a predetermined portion of the floating gate film. A control gate film is formed. The control gate layer, the gate interlayer insulating layer, and the floating gate layer may be etched to form a string select line crossing the device isolation layer, a ground select line, and a plurality of parallel word lines interposed between the lines.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosure may be made thorough and complete, and to fully convey the spirit of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Portions denoted by like reference numerals denote like elements throughout the specification.

1 and 2 are cross-sectional views sequentially illustrating a method of forming a NAND type nonvolatile memory device according to an embodiment of the present invention.

Referring to FIG. 1, an isolation region (not shown) is formed on a semiconductor substrate 1 to define an active region. Certain portions of the active region are etched to form recessed regions 2a and 2b. The recessed areas 2a and 2b consist of a first recessed area 2a and a second recessed area 2b. The first recessed region 2a has a wider width than the second recessed region 2b and is where the selection lines are subsequently formed. Word lines are subsequently formed on the second recessed regions 2b.

Referring to FIG. 2, a thermal oxidation process is performed to form the tunnel oxide film 3. The floating gate layer 5 is formed and patterned on the entire surface of the semiconductor substrate 1 to expose the device isolation layer (not shown), but fill the recessed regions 2a and 2b. The floating gate layer 5 may be formed of, for example, polysilicon doped with impurities. A gate interlayer insulating film 7 is formed and patterned on the semiconductor substrate 1 to expose a portion of the floating gate film 5. The gate interlayer insulating film 7 may be formed of, for example, a triple film of an oxide film-nitride film-oxide film. A polysilicon film 9 and a metal containing film 11 forming a control gate film are formed on the entire surface of the semiconductor substrate 1, and a capping film 13 is formed on the control gate film. The capping layer 13, the control gate layers 11 and 9, the gate interlayer insulating layer 7, and the floating gate layer 5 are sequentially etched to expose the semiconductor substrate 1, but the device isolation layer ( A ground select line GSL and a string select line SSL may be formed to cross the plurality of parallel word lines WL interposed between the lines GSL and SSL. In the ground select line GSL and the string select line SSL, the gate interlayer insulating layer 7 is formed to have a width shorter than that of the lines GSL and SSL so that the control poly film 9 and the The floating gate film 5 is in contact. This is to apply a low voltage operating voltage to the ground select line and the string select line.

Subsequently, referring to FIG. 2, a gate reoxidation process is performed to form an oxide film 15. An ion implantation process is performed using the lines WL, SSL, and GSL as an ion implantation mask to form a low concentration impurity region 17 in an active region of the semiconductor substrate. The spacer layer is formed and anisotropically etched to form a spacer 19 covering the sidewalls of the respective lines GSL, SSL, and WL. As the spacing of the word lines WL becomes narrower, spacers 19 covering sidewalls of the word lines may be formed to fill the spaces between the word lines as shown in FIG. 2 without being spaced apart from each other. After the spacer 19 is formed, a high concentration impurity implantation region 21 is formed in the active region by using the lines WL, SSL, GSL and the spacer 19 as an ion implantation mask. Then, the interlayer insulating film 23 is formed. Although not shown, an etch stop film may be conformally formed before the interlayer insulating film is formed. After planarizing an upper portion of the interlayer insulating layer 23, a predetermined portion of the interlayer insulating layer 23 is etched to expose the impurity implantation region 21 between the ground select lines GSL to expose the common source line groove 25. To form. The barrier film 29 is conformally formed and the conductive film 31 is formed to fill the groove 25. The planarization process is performed to expose the interlayer insulating film 23. The barrier layer 29 may be formed of, for example, TiN, and the conductive layer 31 may be formed of, for example, tungsten.

Therefore, in the NAND type nonvolatile memory device and the method of forming the same, the tunnel oxide film is conformally formed along the inner wall and the bottom of the recessed region, and the floating gate layer is formed in the recessed region. Longer length can prevent leakage current. In addition, when the device structure is applied, horizontal and vertical sizes can be reduced.

Claims (6)

Forming a plurality of device isolation layers parallel to each other on a semiconductor substrate to define an active region; Etching portions of the active region to form recessed regions having a plurality of island shapes and isolated from each other; Performing a thermal oxidation process to form a tunnel oxide film; Forming a floating gate layer covering the active region and exposing the device isolation layers; Forming a gate interlayer insulating film exposing a predetermined portion of the floating gate film; Forming a control gate film; Etching the control gate layer, the gate interlayer insulating layer, and the floating gate layer to form a string selection line crossing the device isolation layer, a ground selection line, and a plurality of parallel word lines interposed between the lines; A method of forming a NAND type nonvolatile memory device. The method of claim 1, Conducting a gate re-oxidation process; Forming a low concentration impurity implantation region in the active region using the respective lines; Forming a spacer covering sidewalls of the lines; And And forming a high concentration impurity implantation region in the active region using the spacers and the lines. The method of claim 1, And the floating gate layer and the control gate layer are in contact with each other in the ground selection line and the string selection line. A plurality of device isolation films formed on the semiconductor substrate and defining a plurality of parallel device isolation layers; Recessed regions formed in predetermined portions of the active region and having islands and isolated from each other; A string selection line and a ground selection line crossing the device isolation layer and the recessed regions, and a plurality of parallel word lines interposed between the lines; Each of the lines, A tunnel oxide film conformally covering inner walls and bottoms of the recessed regions; A floating gate positioned on the tunnel oxide layer and filling at least a top recessed region; And a gate interlayer insulating film and a control gate film on said floating gate. The method of claim 4, wherein A low concentration impurity implantation region located in the active region on both sides of each of the lines; A spacer covering sidewalls of the lines; And And a high concentration impurity implantation region located in said active region adjacent said spacer. The method of claim 4, wherein And the floating gate layer and the control gate layer are in contact with each other in the ground selection line and the string selection line.

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