KR100648287B1 - Flash memory device and method of fabricating the same - Google Patents

Abstract

A flash memory device is provided to remarkably increase integration of a semiconductor device by making channel regions of two transistors share one semiconductor pattern and by making source/drain electrodes of two or four transistors share one impurity region. An active pattern is disposed in a predetermined region of a semiconductor substrate(100), composed of channel regions and connection regions disposed between the channel regions. Isolation layer patterns are disposed at both sides of the active pattern. Gate patterns(135) are disposed between the isolation layer pattern and the channel region. A gate insulation layer pattern is interposed between the semiconductor substrate and the gate pattern and between the gate pattern and the active pattern. A tunnel insulation layer is disposed between the gate pattern and the semiconductor substrate, thinner than the gate insulation layer surrounded by the gate insulation layer pattern. Source/drain electrodes are formed in the connection regions. Lower interconnections are disposed in parallel with the active patterns to interconnect the gate patterns. The gate insulation layer pattern is made of at least one selected from a silicon oxide layer, a silicon nitride layer and a high dielectric layer.

Description

Flash memory device and method of manufacturing the same {FLASH Memory Device And Method Of Fabricating The Same}

1A is a plan view illustrating a semiconductor device in accordance with an embodiment of the present invention.

1B and 1C are cross-sectional views illustrating a semiconductor device in accordance with an embodiment of the present invention.

2 is a perspective view showing a transistor structure of a semiconductor device according to a preferred embodiment of the present invention.

3A is a plan view illustrating a semiconductor device according to another embodiment of the present invention.

3B and 3C are cross-sectional views illustrating a semiconductor device in accordance with another embodiment of the present invention.

4A through 10A are plan views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

4B to 10B are perspective views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

11 is a cross-sectional view illustrating a method of manufacturing a semiconductor device in accordance with one embodiment of the present invention.

12 is a perspective view illustrating a method of manufacturing a semiconductor device in accordance with another modified embodiment of the present invention.

13 is a circuit diagram showing a flash memory according to the present invention.

14A to 14D are cross-sectional views illustrating a method of manufacturing a flash memory according to an embodiment of the present invention.

15 is a cross-sectional view illustrating a method of manufacturing a flash memory according to a modified embodiment of the present invention.

The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a flash memory device and a manufacturing method thereof.

The density of semiconductor devices has adhered to Moore's Law or Sulfur's Law, which doubles every 18 months or every year, and this increase is expected to continue. In order to sustain this increase in density, it is necessary to shrink the planar area occupied by the electronic elements constituting the semiconductor device. However, the shrink is constrained by the requirement to meet the various characteristics required in the electronic devices.

Short channel effects, which are an issue with respect to MOS transistors, are representative examples of constraints associated with shrinking semiconductor devices. The short channel effect occurs as the channel length of the transistor (i.e., the gap between the source electrode and the drain electrode) decreases, and causes punch-through and drain induced barrier lowering (DIBL). And deterioration of transistor characteristics such as subthreshold swing. In addition, when the channel length of the transistor decreases, problems such as an increase in parasitic capacitance between the source / drain electrodes and the substrate and an increase in leakage current are also present. By these problems, reducing the channel length of the transistor is constrained as described above.

Meanwhile, in the case of a planar MOS transistor, as another method of increasing the degree of integration of a semiconductor device, it may be considered to reduce the channel width of the transistor. However, since the channel width W is proportional to the drain current I _d as represented by the following equation, the reduction in the channel width reduces the transistor's current transfer capability.

In addition, a general flash memory device includes a gate insulating film having a uniform thickness between the floating gate electrode and the semiconductor substrate. However, because of this uniform thickness of the gate insulating film, there is a limit to improving the product characteristics of the flash memory device. For example, in order to improve the information storage capability of the flash memory device, it is desirable to increase the thickness of the gate insulating film, but the increase in the thickness of the gate insulating film degrades the characteristics of the read and write operations. Thus, the thickness of the gate insulating film is selected so as to compromise desired characteristics. The unit cell of a nonvolatile memory device such as Y pyrom has a selection transistor and a cell transistor to overcome this limitation. However, Y pyrom has a problem in that the area of a unit cell is large because two transistors are provided.

In conclusion, in general planar MOS transistors, technical requests for improving the characteristics of transistors and increasing the degree of integration are difficult. In other words, there is a need for a transistor with a new structure that can meet these technical requirements.

An object of the present invention is to provide a flash memory device that can increase the degree of integration.

An object of the present invention is to provide a flash memory device having an increased channel length.

An object of the present invention is to provide a flash memory device capable of independently improving information storage capability, read operation characteristics, and write operation characteristics.

An object of the present invention is to provide a method for manufacturing a flash memory device that can increase the degree of integration.

An object of the present invention is to provide a method of manufacturing a flash memory device capable of increasing the channel length of a transistor.

An object of the present invention is to provide a method of manufacturing a flash memory device capable of independently improving information storage capability, read operation characteristics, and write operation characteristics.

In order to achieve the above technical problem, the present invention provides a flash memory device having a tunnel insulating film thinner than the vertical channel and gate insulating film. The device is composed of channel regions and connection regions disposed between the channel regions, the active pattern disposed in a predetermined region of the semiconductor substrate, the device isolation layer patterns disposed on both sides of the active pattern, and the device isolation layer pattern. Gate patterns disposed between the channel region, a gate insulating layer pattern interposed between the gate pattern and the semiconductor substrate, and between the gate pattern and the active pattern, and disposed between the gate pattern and the semiconductor substrate, A tunnel insulating layer thinner than the gate insulating layer pattern surrounded by the gate insulating layer, source / drain electrodes formed in the connection regions, and lower wirings connecting the gate patterns.

The gate pattern includes a floating gate pattern in contact with the gate insulating layer pattern, a control gate pattern disposed on the floating gate pattern, and a gate interlayer insulating layer pattern interposed between the floating gate pattern and the control gate pattern. In this case, the lower wiring is electrically connected to the control gate pattern.

In example embodiments, the gate insulating layer pattern may include at least one selected from a silicon oxide layer, a silicon nitride layer, and a high dielectric layer. In addition, according to an embodiment of the present invention, the gate insulating layer pattern may extend between the gate pattern and the device isolation layer pattern.

Tunnel impurity regions may be formed in the semiconductor substrate under the tunnel insulating layer. In this case, the tunnel impurity region is preferably of a different conductivity type from the semiconductor substrate.

In addition, a lower impurity region may be formed in the semiconductor substrate under the gate pattern. In this case, the lower impurity region has the same conductivity type as that of the semiconductor substrate.

In order to achieve the above technical problems, the present invention provides a method of manufacturing a flash memory device comprising forming a gate electrode on the side of the channel and forming a tunnel insulating film thinner than the gate insulating film. In this method, device isolation layer patterns are formed in a predetermined region of a semiconductor substrate, and the preliminary active pattern includes a plurality of channel regions, connection regions disposed between the channel regions, and gate regions disposed on the left and right sides of the channel region. And forming the active patterns consisting of the channel regions and the connection regions by recessing the gate regions of the preliminary active pattern to have a lower surface than the channel region. Subsequently, a tunnel insulating layer formed on the bottom surface of the recessed gate region and a gate insulating layer covering the lower surface of the recessed gate region and the exposed sidewall of the active pattern are formed to surround the tunnel insulating layer. In this case, the gate insulating film is thicker than the tunnel insulating film. Thereafter, gate patterns are formed on both sides of the channel region to fill the recessed gate region in which the gate insulating layer is formed, and then source / drain electrodes are formed in the connection regions of the active pattern.

According to an embodiment of the present disclosure, the forming of the active pattern may include forming a mask pattern covering the active pattern and exposing an upper surface of the gate area, and then using the mask pattern as an etching mask. Anisotropically etching a region to form the recessed gate region that exposes sidewalls of the active pattern. In this case, the etching of the gate region may be performed by using an etching recipe having an etching selectivity with respect to the mask pattern and the device isolation layer pattern.

The forming of the gate pattern may include forming a floating gate conductive layer, a gate interlayer insulating layer, and a control gate conductive layer, which in turn fill the recessed gate region on the resultant product on which the gate insulating layer is formed, and then an upper surface of the device isolation layer pattern. Planar etching the control gate conductive layer, the gate interlayer insulating layer, and the floating gate conductive layer until the exposed portions are formed to form a floating gate pattern, a gate interlayer insulating layer pattern, and a control gate pattern that sequentially fill the recessed gate region. It includes.

The method may further include forming a lower impurity region on the semiconductor substrate under the recessed gate region after forming the active patterns. In this case, the lower impurity region has the same conductivity type as that of the semiconductor substrate.

The forming of the tunnel insulating film and the gate insulating film may include forming a preliminary gate insulating film on a bottom surface of the recessed gate area and an exposed sidewall of the active pattern, and then forming the preliminary gate in the center of the recessed gate area. Forming mask patterns having openings exposing the top surface of the insulating film. Subsequently, by forming the tunnel region exposing the upper surface of the semiconductor substrate by etching the exposed preliminary gate insulating layer using the mask patterns as an etching mask, the mask pattern is removed to expose the preliminary gate insulating layer. Thereafter, a tunnel insulating film is formed in the tunnel area, and the tunnel insulating film is formed to have a thickness thinner than that of the gate insulating film.

In the present specification, when it is mentioned that a film is on another film or substrate, it means that it may be formed directly on another film or substrate or a third film may be interposed therebetween. In addition, in the drawings, the thicknesses of films and regions are exaggerated for effective explanation of technical contents. In addition, in various embodiments of the present specification, terms such as first, second, and third are used to describe various regions, films, and the like, but these regions and films should not be limited by these terms. . These terms are only used to distinguish any given region or film from other regions or films. Thus, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in other embodiments. Each embodiment described and illustrated herein also includes its complementary embodiment.

1A is a plan view illustrating a transistor structure of a semiconductor device in accordance with some embodiments of the inventive concept, and FIGS. 1B and 1C are cross-sectional views illustrating a semiconductor device in accordance with an embodiment of the present invention. Figures 1B and 1C show cross sections taken along the dashed lines I-I 'and II-II' shown in Figure 1A, respectively. .

1A to 1C, a semiconductor pattern 110 used as a channel region of a transistor is formed in a predetermined region of the semiconductor substrate 100. The semiconductor pattern 110 is formed of a semiconductor (eg, silicon) having the same conductivity type as that of the semiconductor substrate 100.

According to the present invention, the semiconductor pattern 110 is preferably a rectangular parallelepiped having first, second, third and fourth side surfaces, and an upper surface and a lower surface (see FIG. 2). In this case, the lower surface of the semiconductor pattern 110 directly contacts the semiconductor substrate 100. In addition, the first side and the second side face each other in one direction, and the third side and the fourth side face each other in the other direction perpendicular thereto.

Impurity patterns 150 are disposed on both sides (eg, the first and second side surfaces) of the semiconductor pattern 110, and on both sides (eg, the third side) of the semiconductor pattern 110. And the fourth side), the gate patterns 135 are disposed. The impurity patterns 150 are used as source / drain electrodes of a transistor. For this purpose, the impurity patterns 150 are disposed to directly contact the semiconductor pattern 110. The impurity patterns 150 may include impurities of a conductive type different from that of the semiconductor pattern 110 and the semiconductor substrate 100.

The gate patterns 135 are used as gate electrodes for controlling the electrical potential of the semiconductor pattern 110, and a gate insulating layer pattern 125 is formed between the gate pattern 135 and the semiconductor pattern 110. It is interposed. The gate insulating layer pattern 125 extends to separate the gate pattern 135 from the semiconductor substrate 100. The gate pattern 135 may be made of at least one material selected from polycrystalline silicon, copper, aluminum, tungsten, tantalum, titanium, tungsten nitride, tantalum nitride, titanium nitride, tungsten silicide, and cobalt silicide. In addition, the gate insulating layer pattern 125 may be formed of at least one selected from a silicon oxide layer, a silicon nitride layer, and a high dielectric layer.

According to the above-described embodiment, one semiconductor pattern 110 corresponds to a channel region shared by two transistors. In addition, the pair of impurity patterns 150 disposed on both sides of one semiconductor pattern 110 also correspond to source / drain electrodes shared by the two transistors. As a result, the pair of transistors formed around the predetermined semiconductor pattern 110 share the semiconductor pattern 110 and the impurity patterns 150 as channel regions and source / drain electrodes, respectively. As such, since the semiconductor pattern 110 and the impurity patterns 150 are shared by two transistors, the number of transistors formed per unit area may be increased. Meanwhile, as shown in FIGS. 10A and 10B, one impurity region used as the source / drain electrode may be shared by four transistors. As a result, the semiconductor device according to the present invention has a higher degree of integration compared to semiconductor devices having conventional planar transistors.

The gate electrode of the MOS transistor according to the present invention is different from the general planar MOS transistor in which the gate electrode is disposed on the side of the channel region (ie, the semiconductor pattern 110). In addition, the heights from the semiconductor substrate 100 to the top surfaces of the gate patterns 135 and the impurity patterns 150 are substantially the same. That is, they have substantially the same thickness. At this time, the expression "the thickness of A and B is substantially the same" means that the difference between the thickness of A and B is less than 20% of the thickness of A or B.

The gate patterns 135 are connected to a gate line 174 to which a gate voltage is applied through a gate plug 172 disposed thereon, and the impurity patterns 150 may include contact plugs disposed thereon. 182 is connected to source / drain lines 184 to which a ground voltage or signal voltage is applied. Preferably, the gate plug 172 and the gate line 174 constitute a lower wiring 170 disposed at a lower level than the source / drain line 184, and the contact plug 182 and the source. The / drain line 184 constitutes the upper wiring 180.

A lower interlayer insulating layer 162 and an upper interlayer insulating layer 164 are disposed on the gate patterns 135 and the impurity patterns 150, so that the gate lines 174 and the source / drain lines ( 184 structurally supporting and electrically insulating at the same time. The gate plug 172 penetrates through the lower interlayer insulating layer 162 to connect to the gate pattern 135, and the contact plug 182 penetrates through the lower and upper interlayer insulating layers 162 and 164. It is connected to the impurity pattern 150.

According to one embodiment of the present invention, two gate patterns 135 formed around one semiconductor pattern 110 are connected to different lower interconnections 170 (see FIG. 1A). Similarly, two impurity patterns 150 formed around one semiconductor pattern 110 may also be connected to different upper interconnections 180, respectively.

Meanwhile, the transistor structure according to the present invention may constitute cell transistors of a floating-gate type flash memory. According to this embodiment, the gate pattern 135 includes a floating gate pattern 136, a gate interlayer insulating film pattern 137, and a control gate pattern 138 that are sequentially stacked (see FIGS. 10A and 10B). In this case, the lower interconnection 170 is electrically connected to the control gate pattern 138, and the floating gate pattern 136 is electrically floated. That is, the floating gate pattern 136 is spaced apart from the semiconductor pattern 110 and the semiconductor substrate 100 by the gate insulating layer pattern 125, and the control gate pattern by the gate interlayer insulating layer pattern 137. Spaced from 138.

In addition, the transistor structure according to the present invention may constitute cell transistors of a floating-trap type flash memory. According to this embodiment, the gate insulating film pattern 125 may be an insulating film including a silicon nitride film, and is preferably composed of a silicon oxide film-silicon nitride film-silicon oxide film that is sequentially stacked. Embodiments of the present invention applied to such a flash memory will now be described in more detail with reference to FIGS. 4 to 10.

According to another embodiment of the present invention, the structure of the lower wiring 170 and the upper wiring 180 may be modified. 3A is a plan view illustrating a semiconductor device having a wired structure according to the modified embodiment. 3B and 3C are process cross-sectional views showing cross sections taken along the dotted lines III-III 'and IV-IV' shown in FIG. 3A, respectively. Since this embodiment is similar to the above-described embodiment except for the wiring structure, a description of overlapping contents with the previous embodiment will be omitted below.

Referring to FIGS. 3A, 3B, and 3C, two gate patterns 135 formed around one semiconductor pattern 110 may be connected by a local wiring 176 crossing the semiconductor pattern 110. (See FIG. 3C), the local wiring 176 is connected to the gate line 174 through an upper gate plug 178 disposed thereon (see FIG. 3A).

According to this embodiment, since the same gate voltage is applied to the gate patterns 135 connected by the local wiring 176, the number of transistors using one semiconductor pattern 110 as a channel region is one. However, the channel width of the transistor according to this embodiment is increased compared to the above-described embodiment.

More specifically, the channel width of the transistor according to the present invention corresponds to the height (H of FIG. 2) of the gate pattern 135 in contact with the channel region (ie, the semiconductor pattern 110). As described above, when the gate patterns 135 are connected by the local wiring 176, an area of the gate pattern 135 in contact with the channel region is lower than that of the embodiment described with reference to FIGS. 1A to 1C. Doubled. Thus, the channel width according to this embodiment is approximately twice that of the previous embodiment. As such, when the channel width of the transistor increases, the current transfer capability of the transistor may increase. Meanwhile, the channel length of the transistor is a length between the source electrode and the drain electrode, and according to the above-described embodiments of the present invention, the length of the semiconductor pattern 110 or the gate pattern 135 (L in FIG. 2) is increased. Corresponds. Thus, in the embodiments shown in FIGS. 1A and 3A, the channel length is the same.

According to this embodiment, one of the impurity patterns 150 is connected to the upper wiring 180 in the same manner as in the previous embodiment, while the other impurity pattern 150 is disposed above the predetermined impurity pattern 150. Is connected to the information storage device 190 of the. The information storage device 190 is a DRAM cell capacitor having a lower electrode 192, an upper electrode 196, and a dielectric film 194 interposed therebetween, as shown in FIG. 3B. Can be.

According to modified embodiments of the present invention, the information storage device 190 may include a magnetic random access memory (MRAM), a ferroelectric RAM (FeRAM), and a phase-change RAM (PRAM). It may be a magnetic tunnel junction (MTJ), a ferroelectric capacitor, and a phase-change resistor used as a structure for storing information.

4A to 10A are plan views illustrating a method of manufacturing a semiconductor device in accordance with some embodiments of the present invention, and FIGS. 4B to 10B illustrate a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention. These are perspective views.

4A and 4B, a mask film 210 is formed on the semiconductor substrate 100. The mask layer 210 may be formed of at least one selected from a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a polycrystalline silicon film. According to some embodiments of the present disclosure, the mask layer 210 may be a silicon oxide layer and a silicon nitride layer that are sequentially stacked.

Subsequently, the mask layer 210 and the semiconductor substrate 100 are patterned to form an isolation trench 102 defining a preliminary active pattern 200. The preliminary active pattern 200 is a region where transistors are formed through a subsequent process, and includes a plurality of channel regions 201, a plurality of connection regions 202, and a plurality of gate regions 203. The channel regions 201 are arranged along one direction (eg, longitudinal direction), the connection regions 202 are disposed between the channel regions 201, and the gate regions 203 Is disposed on the left and right of the channel regions 201 along the other direction (eg, the transverse direction). That is, a pair of connection regions 202 and a pair of gate regions 203 perpendicular thereto are disposed at both sides of one channel region.

The device isolation trench 102 may be formed by anisotropic etching, and the mask layer 210 may be used as an etching mask in this etching process. In this case, the mask layer 210 may be used as an etch stop layer in subsequent planar etching steps (see FIGS. 5B and 8B). The thickness of the mask layer 210 may be determined in consideration of the thickness of the mask layer 210 that is recessed while being used as the etching mask and the etch stop layer. According to the present invention, the mask film 210 may be formed to a thickness of approximately 200 to 3000 mm 3.

Referring to FIGS. 5A and 5B, after forming an isolation layer on a resultant material on which the preliminary active pattern 200 is formed, the isolation layer is planarized and etched until the upper surface of the mask layer 210 is exposed. As a result, the device isolation layer pattern 105 filling the device isolation trench 102 is formed around the preliminary active pattern 200.

According to embodiments of the present invention, the device isolation film is preferably formed using a silicon oxide film, and a silicon nitride film, a polycrystalline silicon film, a spin-on-glass layer (SOG Layer), or the like may be further used. . In addition, in order to cure the etching damage generated in the anisotropic etching process, a thermal oxidation process may be further performed before forming the device isolation layer. By the thermal oxidation process, a silicon oxide film (not shown) is formed on an inner wall of the device isolation trench 102. In addition, a diffusion barrier layer (not shown) may be further formed before the device isolation layer is formed in order to prevent a change in characteristics of the transistor due to infiltration of impurities. The diffusion barrier layer is preferably a silicon nitride film formed through chemical vapor deposition.

On the other hand, according to the present invention, the area of the channel regions 201 used as the channel of the transistor is in contact with the device isolation layer 105 is minimized, compared to the conventional planar transistor structure. Therefore, the thermal oxidation process, the diffusion barrier film forming process, or the like may optionally be omitted.

6A and 6B, a photoresist pattern exposing the gate regions 203 is formed on the preliminary active pattern 200. Thereafter, the mask layer 210 and the preliminary active pattern 200 are etched in the exposed gate regions 203 using the photoresist pattern as an etching mask. As a result, a mask pattern 215 that is an etching result of the active pattern 205 and the mask layer 210 in which the channel regions 201 and the connection regions 202 are alternately disposed below the photoresist pattern. ) Is formed. In addition, a recessed gate region 203 ′ may be formed between the active pattern 205 and the device isolation layer pattern 105 to expose sidewalls of the channel region 201. Thereafter, the photoresist pattern is removed to expose the top surface of the mask pattern 215.

The depth of the recessed gate region 203 ′ determines the channel width H of the transistor according to the invention. The channel width is preferably large because it is a process parameter that affects the electrical characteristics of the transistor, such as the current carrying capability. As described in the prior art, in the case of a semiconductor device having a conventional planar transistor, the increase in the channel width is limited because it leads to an increase in the unit cell area resulting in a decrease in the degree of integration. On the other hand, according to embodiments of the present invention, the channel width corresponds to the height of the channel region 201 exposed by the recessed gate region 203 '. Thus, by increasing the depth of the recessed gate region 203 ', the channel width of the transistor can be increased without increasing the cell area. Accordingly, the present invention is not limited as in the prior art.

Subsequently, a gate insulating layer pattern 125 used as a gate insulating layer of the transistor is formed on the semiconductor substrate 100 exposed through the recessed gate region 203 ′. According to an embodiment of the present invention, the gate insulating layer pattern 125 may be a silicon oxide layer formed through a thermal oxidation process. In this case, the gate insulating layer pattern 125 is formed on the exposed sidewall of the active pattern 205 (ie, the side surfaces of the channel regions 201) and the bottom surface of the recessed gate region 203 ′. do. Meanwhile, the etching damage generated in the etching process for forming the recessed gate region 203 'may be cured by the thermal oxidation process.

Referring to FIGS. 7A and 7B, a gate conductive layer 130 is formed on a resultant product on which the gate insulating layer pattern 125 is formed. The gate conductive layer 130 may be formed of at least one material selected from polycrystalline silicon, copper, aluminum, tungsten, tantalum, titanium, tungsten nitride, tantalum nitride, titanium nitride, tungsten silicide and cobalt silicide, and a method of forming the gate conductive layer 130 Chemical vapor deposition techniques may be used. When the gate conductive layer 130 is formed of copper, an electroplating technique may be used.

According to the exemplary embodiment of the present invention, the gate conductive layer 130 may include a floating gate conductive layer 131, a gate interlayer insulating layer 132, and a control gate conductive layer 133 that are sequentially stacked. Can be done. The floating gate conductive layer 131 and the control gate conductive layer 133 may be formed of polycrystalline silicon, and the gate interlayer insulating layer 132 may be formed of an insulating layer including a silicon nitride layer. Preferably, the gate interlayer insulating film 132 is formed of a silicon oxide film-silicon nitride film-silicon oxide film sequentially stacked.

8A and 8B, the gate conductive layer 130 is planarized and etched until the mask pattern 215 and the device isolation layer pattern 105 are exposed, and thus the recessed gate regions 203 ′ are formed. ) To form gate patterns 135.

According to the present invention, the planarization etching is performed to the extent that the mask pattern 215 is not removed in order to prevent etching damage to the channel region 201. Preferably the planarization etch is carried out using chemical mechanical polishing (CMP) technology.

The gate patterns 135 include a floating gate pattern 136, a gate interlayer insulating layer pattern 137, and a control gate pattern 138 that are sequentially stacked. The gate interlayer insulating layer pattern 137 is formed to contact the side and bottom surfaces of the control gate pattern 138, and the floating gate pattern 136 is formed on the outer and lower surfaces of the gate interlayer insulating layer pattern 137. It is formed to be in contact. The floating gate pattern 136 is surrounded by the device isolation layer pattern 105 and the gate insulating layer pattern 125. The gate insulating layer pattern 125 is interposed between the floating gate pattern 136 and the channel region 201 and between the floating gate pattern 136 and the semiconductor substrate 100.

9A and 9B, a lower interlayer insulating film (see 162 of FIGS. 1B and 1C) is formed on a resultant product on which the gate patterns 135 are formed, and then patterned to form the lower interlayer insulating layer 135. Gate contact holes are formed to expose the top surface. Subsequently, lower interconnections 170 may be formed to connect the gate patterns 135 through the gate contact holes.

Meanwhile, in order to reduce power consumption and increase an operating speed of the semiconductor device, the lower interconnections 170 may be formed of a metallic material. For example, the lower interconnections 170 may be formed of at least one material selected from aluminum, copper, and tungsten.

According to an exemplary embodiment, the lower interconnection 170 may include gate plugs 172 filling the gate contact hole and gate lines 174 connecting the gate plugs 172. According to another embodiment of the present invention, when the thickness of the lower interlayer insulating film is thin, the lower wiring 170 may be formed through a wiring process. In this case, the gate plugs 172 and the gate lines 174 are integrally formed at the same time.

According to the above-described embodiment of the flash memory, the lower wiring 170 (particularly, the gate plugs 172) is connected to the control gate pattern 138. On the other hand, the floating gate pattern 136 is electrically isolated by the device isolation layer pattern 105, the gate insulation layer pattern 125, and the lower interlayer insulation layer.

In addition, the gate patterns 135 disposed on both sides of the active pattern 205 are connected by different lower interconnections 170. That is, the lower wiring 170 connecting the gate patterns 135 disposed on one side of the active pattern 205 has a lower wiring connecting the gate patterns 135 disposed on the other side of the active pattern 205. And electrically separated from 170. In this case, as shown in FIG. 9B, the lower interconnections 170 are disposed on the device isolation layer pattern 105 interposed between the gate patterns 135 and disposed on the mask pattern 215. Have parallel directions.

10A and 10B, an upper interlayer insulating film 164 of FIGS. 1B and 1C is formed on a resultant product on which the lower interconnections 170 are formed, and then patterned to expose the connection region 202. Source / drain contact holes (168 of FIG. 11) are formed. Subsequently, a source / drain electrode 150 of FIG. 11 is formed in the connection regions 202 exposed through the source / drain contact holes 168.

The source / drain electrode 150 may be a doped region containing a high concentration of impurities of a conductivity type different from the channel region 201. The impurity regions 150 may be formed through an ion implantation process using the upper interlayer insulating layer 164 having the source / drain contact holes 168 as an ion implantation mask.

Thereafter, upper interconnections 180 are formed to connect the source / drain electrodes 150. The upper interconnections 180 may also be formed of a metallic material having a low specific resistance. According to an embodiment of the present disclosure, the upper interconnections 180 may include contact plugs 182 filling the source / drain contact holes 168 and source / drain lines connecting the contact plugs 182. 184.

FIG. 11 is a cross-sectional view illustrating a method of forming a source / drain electrode 150 according to a modified embodiment of the present invention, and illustrates a cross section taken along the dashed line V-V ′ of FIG. 10B.

Referring to FIG. 11, the forming of the source / drain electrode 150 may include forming contact holes having a predetermined depth in the connection regions 202 and then exposing the connection regions 202 exposed through the contact holes. Injecting impurities into the inner wall of the) may be further included. The contact holes are formed by anisotropically etching the connection regions 202 exposed through the source / drain contact holes 168 using the upper interlayer insulating layer 164 as an etching mask.

According to this embodiment, the implanting of impurities may use an ion implantation process or a diffusion process. Preferably, injecting the impurities may include filling the contact holes with a highly doped polysilicon plug having a high concentration of impurities. In this case, impurities contained in the polycrystalline silicon plug are diffused to form an impurity region used as the source / drain electrode 150. Such a polycrystalline silicon plug may replace the contact plug 182 constituting the upper interconnection 180, as shown.

12 is a perspective view illustrating a method of manufacturing a semiconductor device in accordance with another modified embodiment of the present invention. More specifically, this embodiment can be applied to the manufacturing method of the floating trap type flash memory.

Referring to FIG. 12, the forming of the gate insulating layer pattern 125 described with reference to FIGS. 6A and 6B may be formed using a chemical vapor deposition technique. In this case, the gate insulating layer pattern 125 may be formed of at least one selected from a silicon oxide layer, a silicon nitride layer, and a high dielectric layer. In addition, a heat treatment process may be further performed to heal the etching damage of the channel region 201.

According to the exemplary embodiment of the floating trap type flash memory, the gate insulating layer pattern 125 may be formed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer that are sequentially stacked. In this embodiment, since the silicon nitride film is rich in trap sites, it can be used as a structure for storing information.

On the other hand, since the material film formed using the chemical vapor deposition technique is formed on the entire surface of the resultant structure, the gate insulating film pattern 125 is between the device isolation film pattern 105 and the gate pattern 135 and the It may also be formed between the mask pattern 215 and the gate pattern 135.

13 is a circuit diagram illustrating a cell array of a flash memory according to an embodiment of the present invention.

Referring to FIG. 13, source / drain electrodes of the cell transistors are connected by a plurality of bit lines BL1, BL2, BL3, BL4, and BL5. The bit lines BL1, BL2, BL3, BL4, BL5 are disposed to cross the plurality of word lines WL1, WL2, WL3, and WL4. The word lines WL1, WL2, WL3, and WL4 connect gate electrodes of a cell transistor.

According to an embodiment of the present invention, a cell transistor of a flash memory is programmed using Hot Carrier Injection and erased using Fowler Nordheim tunneling (FN tunneling). do. More specifically, considering the predetermined cell transistor A selected by the second word line WL2, the second bit line BL2, and the third bit line BL3, the word line selected for the program operation is selected. The program voltage V _PGM is applied to WL2, and a ground voltage is applied to the unselected word lines WL1, WL3, and WL4. In this case, a ground voltage is applied to the first and second bit lines BL1 and BL2, and a drain voltage V _D is applied to the third to fifth bit lines BL3, BL4, and BL5. In this case, the program voltage V _PGM is approximately 12 volts, and the drain voltage V _D is approximately 5 volts.

In this embodiment, for an erase operation, a ground voltage is applied to the selected word line WL2, an erase voltage V _ERASE is applied to the substrate bulk, and bit lines BL1, BL2, BL3, and BL4 are applied. , BL5) electrically floats. In this case, the erase voltage V _ERASE may be applied to the unselected word lines WL1, WL3, and WL4, thereby preventing erasing of unselected cells. The erase voltage V _ERASE may be approximately 15 to 20 volts.

In addition, for a read operation, as in a conventional flash memory, a read voltage V _READ is applied to a selected word line, and ground voltages and bit lines BL2 and BL3 corresponding to the source and drain electrodes are respectively applied. The drain voltage V _D is applied. The read voltage V _READ may be about 1 to 3 volts, and the drain voltage V _D may be about 0.1 to 1 volt.

According to another embodiment of the present invention, the cell transistor of the flash memory may be programmed using FN tunneling. In this case, a program voltage V _PGM is applied to the selected word line WL2, and a ground voltage is applied to the second and third bit lines BL2 and BL3 and the substrate bulk. In this case, in order to prevent the unselected cell transistors from being programmed by the program voltage V _PGM applied to the selected word line WL2, the bit lines BL1, BL4, A predetermined drain voltage V _D is applied to BL5. The erase voltage V _ERASE may be approximately 15 to 20 volts.

The operation method and operating conditions of the cell transistor of the flash memory described above may be variously modified in consideration of the structure of the transistor structure and the characteristics of the wiring structures.

14A through 14D are cross-sectional views illustrating a method of manufacturing a flash memory according to an embodiment of the present invention, and show a cross-sectional view taken along the dotted line II-II ′ of FIG. 1A. This embodiment relates to another method of forming the gate insulating layer pattern 125, and the process up to forming the recessed gate region 203 'is the same as the above-described embodiments. In addition, with respect to the process of forming the gate conductive layer 130 and subsequent processes, the above-described embodiments may be equally applied to this embodiment. In the following description, for the sake of brevity, the overlapping contents with the above-described embodiments will be omitted.

Referring to FIG. 14A, after forming the recessed gate region 203 ′ (see FIGS. 6A and 6B), a lower portion of the semiconductor substrate 100 exposed through the recessed gate region 203 ′ is formed. The impurity region 310 is formed. In detail, the lower impurity region 310 is formed on the bottom surface of the recessed gate region 203 ′ and has the same conductivity type as that of the semiconductor substrate 100. Accordingly, the semiconductor substrate 100 on which the lower impurity region 310 is formed has a higher threshold voltage than the channel region 201.

Due to this difference in threshold voltage, the channel of the transistor according to this embodiment is confined to the channel region 201. That is, when the gate voltage applied to the gate electrode (ie, the gate pattern 135) of the transistor has a value between the threshold voltage of the channel region 201 and the threshold voltage of the lower impurity region 310, the No channel (that is, an electrical passage through which charge can flow) is formed in the semiconductor substrate 100 under the recessed gate region 203 ', that is, the lower impurity region 310. As such, since the limitation of the area used as the channel reduces the variation in the turn-on current of the transistor, the read operation characteristic of the transistor can be improved.

The forming of the lower impurity region 310 may include a predetermined first ion implantation process 300. In this case, the photoresist pattern used as an etch mask in an etching process for forming the recessed gate region 203 ′ may be used as an ion mask in the first ion implantation process 300. According to another embodiment of the present invention, after removing the photoresist pattern, the device isolation layer pattern 105 and the mask pattern 215 may be used as the ion mask.

Referring to FIG. 14B, a thermal oxidation process is performed on a resultant product in which the lower impurity regions 310 are formed, and thus a preliminary gate insulating layer is formed on the sidewall of the channel region 201 and the upper surface of the lower impurity region 310. 122).

According to another embodiment of the present invention, the preliminary gate insulating layer 122 may be one of a silicon oxide film, a silicon nitride film, and a high dielectric film formed using a chemical vapor deposition technique. The method described in connection with FIG. 12 is equally applicable to this embodiment.

According to another embodiment of the present invention, after forming the preliminary gate insulating layer 122, the lower impurity region 310 may be formed. In this case, the preliminary gate insulating layer 122 reduces the problem that ion channeling occurs in the first ion implantation process 300.

Referring to FIG. 14C, a photoresist pattern 325 having openings 328 exposing a portion of an upper surface of the preliminary gate insulating layer 122 is formed on a resultant on which the preliminary gate insulating layer 122 is formed. Preferably, the opening 328 exposes an upper surface of the preliminary gate insulating layer 122 at the center of the recessed gate region 203 ′. Next, a second ion implantation process 320 using the photoresist pattern 325 as an ion implantation mask is performed. Accordingly, the tunnel impurity region 320 is formed in the semiconductor substrate 100 under the opening 328. In this case, the tunnel impurity region 320 may have a different conductivity type from the semiconductor substrate 100 and the lower impurity region 310. In addition, the tunnel impurity region 320 has a higher impurity concentration than the lower impurity region 310.

Meanwhile, according to another embodiment of the present invention, a predetermined spacer 325 ′ may replace the photoresist pattern 325 (see FIG. 15). The forming of the spacer 325 ′ may include forming an spacer layer on a resultant product on which the preliminary gate insulating layer 122 is formed, and then anisotropically etching the spacer layer. In this case, the spacer layer may be formed of a material having an etch selectivity with respect to the preliminary gate insulating layer 122 and the device isolation layer pattern 105. For example, the spacer layer may be a silicon nitride layer or a silicon oxynitride layer. In addition, the anisotropic etching of the spacer layer may be performed until the preliminary gate insulating layer 122 is exposed at the bottom of the recessed gate region 203 ′. As a result, a spacer having the opening 328 may be formed. 325 ') is formed.

Referring to FIG. 14D, the preliminary gate insulating layer 122 is etched using the photoresist pattern 325 or the spacer 325 ′ as an etching mask. As a result, a tunnel region is formed to expose the upper surface of the semiconductor substrate 100 (more specifically, the upper surface of the tunnel impurity region 320).

Thereafter, after removing the photoresist pattern 325 or the spacer 325 ′, a tunnel insulating layer 128 is formed in the tunnel region. Forming the tunnel insulating layer 128 includes a thermal oxidation process, in which case the channel region 201 and the semiconductor substrate 100 covered by the preliminary gate insulating layer 122 are also oxidized. As a result, as shown, the thickness of the preliminary gate insulating layer 122 is increased to form the gate insulating layer pattern 125. The gate insulating layer pattern 125 thus formed has a thickness thicker than that of the tunnel insulating layer 128.

According to another embodiment of the present invention, the tunnel insulating layer 128 may be one of a silicon oxide film, a silicon nitride film, and a high dielectric film formed using a chemical vapor deposition technique. As before, the method described in connection with FIG. 12 is equally applicable to this embodiment.

Subsequently, a gate conductive layer 130 filling the recessed gate region 203 ′ is formed on the tunnel formed layer 128 and the gate insulating layer pattern 125. For the forming of the gate conductive layer 130 and subsequent steps, the embodiments described in connection with the flash memory device may be applied in the same manner (see FIGS. 4 to 11).

14A to 14D and 15, the gate insulating layer pattern 125 is interposed between the channel region 201 and the gate pattern 135, and the tunnel impurity region ( The tunnel insulating layer 128 is interposed between the gate 320 and the gate pattern 135. In this case, since the tunnel insulating layer 128 is thinner than the gate insulating layer pattern 125 as described above, the flash memory device according to the present invention can perform an efficient write operation. Because, as is well known, the probability of Fowler-Nordheim tunneling increases as the thickness of the dielectric film decreases. According to this embodiment, the cell transistor of the flash memory is programmed using Hot Carrier Injection, and erased using Fowler Nordheim tunneling (FN tunneling). The erase operation preferably uses a voltage difference between the semiconductor substrate 100 and the control gate pattern 138.

In addition, according to the present invention, the efficiency of the write operation may be increased by adjusting the impurity concentration of the tunnel impurity region 320 formed under the tunnel insulating layer 128.

According to the present invention, one semiconductor pattern may be shared by the channel region of two transistors. In addition, one impurity region may be shared by the source / drain electrodes of two or four transistors. As a result, the degree of integration of the semiconductor device can be significantly increased.

Further, according to the present invention, since the gate electrode of the transistor is disposed on the side of the channel region, it is possible to increase the channel width of the transistor by increasing the depth of the recessed gate region (ie, the height of the channel region). In this case, the above-mentioned increase in the degree of integration of the semiconductor device can be achieved without reducing the channel width of the transistor. As a result, according to the present invention, it is possible to improve the characteristics of the transistor while increasing the degree of integration of the semiconductor device.

According to an embodiment of the present invention, a gate insulating film pattern is interposed between the gate pattern and the channel region, and a tunnel insulating film is interposed between the gate pattern and the semiconductor substrate. Accordingly, in the flash memory device according to the present embodiment, the channel region for the read operation and the tunnel region for the write operation are spatially separated. As a result, it is possible to independently improve the characteristics of the read operation and the write operation. For example, as described in the embodiments, for the efficient writing operation, it is possible to form the tunnel insulating film thinner than the gate insulating film pattern. The efficiency of the write operation can be further improved by adjusting the conductivity type and concentration of the impurity region formed under the tunnel insulating film. As a result, in the flash memory device according to the present invention, the characteristics of both the read operation and the write operation can be improved.

Claims (20)

An active pattern comprising channel regions and connection regions disposed between the channel regions, the active pattern disposed in a predetermined region of the semiconductor substrate; Device isolation layer patterns disposed on both sides of the active pattern; Gate patterns disposed between the device isolation layer pattern and the channel region; A gate insulating pattern interposed between the gate pattern and the semiconductor substrate and between the gate pattern and the active pattern; A tunnel insulating film disposed between the gate pattern and the semiconductor substrate and thinner than the gate insulating film pattern surrounded by the gate insulating film pattern; Source / drain electrodes formed in the connection regions; And And lower wirings arranged in a direction parallel to the active patterns to connect the gate patterns. The method of claim 1, The gate pattern is A floating gate pattern in contact with the gate insulating layer pattern; A control gate pattern disposed on the floating gate pattern; And A gate interlayer insulating film pattern interposed between the floating gate pattern and the control gate pattern; And the lower wiring is electrically connected to the control gate pattern. The method of claim 1, And the gate insulating layer pattern is at least one selected from a silicon oxide layer, a silicon nitride layer, and a high dielectric layer. The method of claim 1, And the gate insulating layer pattern extends between the gate pattern and the device isolation layer pattern. The method of claim 1, Further comprising a tunnel impurity region formed in the semiconductor substrate under the tunnel insulating film, And the tunnel impurity region is of a different conductivity type from the semiconductor substrate. The method of claim 1, Further comprising a lower impurity region formed in the semiconductor substrate under the gate pattern, And the lower impurity region has the same conductivity type as that of the semiconductor substrate. The method of claim 1, The source / drain electrodes include an impurity region formed in a connection region of the semiconductor substrate, And the impurity region has a different conductivity type from that of the channel region. The method of claim 1, The lower wires Gate plugs connected to the gate patterns; And And a gate line disposed in a direction parallel to the active pattern to connect the gate plugs. The method of claim 1, And upper interconnections connecting the source / drain electrodes while crossing the lower interconnections. Forming device isolation layer patterns in a predetermined region of the semiconductor substrate to form a preliminary active pattern including a plurality of channel regions, connection regions disposed between the channel regions, and gate regions disposed on left and right sides of the channel region; step; Recessing the gate regions of the preliminary active pattern to have a lower top surface than the channel region, thereby forming active patterns consisting of the channel regions and the connection regions; Forming a tunnel insulating film formed on the bottom surface of the recessed gate region and a gate insulating film surrounding the tunnel insulating film and covering the bottom surface of the recessed gate region and the exposed sidewall of the active pattern; Forming gate patterns on both sides of the channel region to fill the recessed gate region in which the gate insulating layer is formed; And Forming source / drain electrodes in connection regions of the active pattern, And the gate insulating film is thicker than the tunnel insulating film. The method of claim 10, Forming the active pattern Forming a mask pattern covering the active pattern and exposing an upper surface of the gate region; And Anisotropically etching the gate region using the mask pattern as an etch mask to form the recessed gate region that exposes sidewalls of the active pattern, The etching of the gate region may be performed using an etching recipe having an etch selectivity with respect to the mask pattern and the device isolation layer pattern. The method of claim 10, Forming the gate pattern Sequentially forming a floating gate conductive film, a gate interlayer insulating film, and a control gate conductive film filling the recessed gate region on the resultant formed with the gate insulating film; And A floating gate pattern, a gate interlayer insulating layer pattern which sequentially fills the recessed gate region by planarizing etching of the control gate conductive layer, the gate interlayer insulating layer, and the floating gate conductive layer until the upper surface of the device isolation layer pattern is exposed; Forming a control gate pattern. The method of claim 12, After forming the gate pattern, further comprising forming lower wirings connecting the gate patterns, Forming the lower wiring Forming gate plugs connecting the control gate patterns; And And forming a gate line arranged in a direction parallel to the active pattern to connect the gate plugs. The method of claim 10, And forming the source / drain electrode comprises forming an impurity region having a different conductivity type from that of the semiconductor substrate in a connection region of the semiconductor substrate. The method of claim 14, Forming the source / drain electrodes Etching a predetermined area of the connection area to form a contact hole having a predetermined depth in the connection area; And And forming an impurity region having a conductivity type different from that of the semiconductor substrate on an inner sidewall of the connection region exposed through the contact hole. The method of claim 13, After forming the source / drain electrodes, forming upper wires connecting the source / drain electrodes while crossing the lower wires. The method of claim 10, After forming the active patterns, And forming a lower impurity region in the semiconductor substrate under the recessed gate region, wherein the lower impurity region has the same conductivity type as that of the semiconductor substrate. The method of claim 10, Forming the tunnel insulating film and the gate insulating film Forming a preliminary gate insulating layer on a bottom surface of the recessed gate region and exposed sidewalls of the active pattern; Forming mask patterns having an opening at a center of the recessed gate region to expose an upper surface of the preliminary gate insulating layer; Forming a tunnel region exposing an upper surface of the semiconductor substrate by etching the exposed preliminary gate insulating layer using the mask patterns as an etching mask; Removing the mask patterns to expose the preliminary gate insulating layer; And Forming a tunnel insulating film in the tunnel region; And the tunnel insulating film is thinner than the gate insulating film. The method of claim 18, And forming the tunnel insulating film using at least one method selected from a thermal oxidation process and a chemical vapor deposition process. The method of claim 18, The mask pattern may be formed of one of a photoresist pattern formed through a photo process and an etching process, and a spacer formed through a deposition process and an anisotropic etching process.

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