KR20080040214A - Method for manufacturing gate electrode of semiconductor memory device - Google Patents

Abstract

A method for manufacturing a gate electrode of a semiconductor memory device is provided to enhance reliability and productivity by suppressing generation of a fitting effect on a semiconductor substrate. A silicon oxide layer, a first polysilicon layer, an ONO layer including upper oxide-nitride-lower oxide layers, and a second polysilicon layer are deposited on a semiconductor substrate(S200). A control gate is formed by etching the second polysilicon layer. A gate interlayer dielectric layer is formed by performing a wet-etch process for the upper oxide layer, a dry-etch process for the nitride layer, and the wet-etch process for the lower oxide layer(S204,S206,S208). A floating gate is formed by patterning the first polysilicon layer(S210). A tunnel oxide layer is formed by etching the silicon oxide layer(S212).

Description

Method for manufacturing gate electrode of semiconductor memory device

1 illustrates a cell array of a conventional NAND flash memory device.

2A and 2B are cross-sectional views illustrating a gate electrode forming process of a flash memory device according to the related art.

3 is a flowchart illustrating a process of forming a gate electrode of a flash memory device according to an exemplary embodiment of the present invention.

4A through 4F are cross-sectional views illustrating a process of forming a gate electrode of a flash memory device according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

300: semiconductor substrate 302: silicon oxide film

304: first polysilicon film 306: lower oxide film

308: nitride film 310: upper oxide film

312: ONO film 314: second polysilicon film

316: capping film 318: photosensitive film pattern

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of manufacturing a gate electrode of a semiconductor memory device.

Semiconductor memory devices used to store data may be generally classified into volatile memory devices and nonvolatile memory devices. In such a semiconductor memory device, first, a volatile memory device represented by DRAM (Dynamic Random Access Memory) or SRAM (Static Rrandom Access Memory) has a drawback in that data input / output operation is fast but data is lost when power supply is interrupted. There is this. On the other hand, nonvolatile memory devices represented by EPROM (Erasable Programmable Read Only Memory) or EEPROM (Electrically Erasable Programmable Read Only Memory), etc., have slower input / output operations than the volatile memory devices, but stored data even when power supply is interrupted. Has the advantage of being kept intact. Therefore, such nonvolatile memory devices are widely used in areas where power cannot always be supplied or power supply is intermittently interrupted, such as a memory card for storing music or image data or a mobile communication system.

Among these non-volatile memory devices, in particular, the flash memory device adopting the 1 Tr / 1 Cell structure of the batch erasing method to overcome the limitation of the integration density of EEPROM can freely input / output data electrically and consumes less power. The high-speed programming is expected to replace the hard disk drive (HDD) of the computer in the future, the demand is gradually increasing. Such a flash memory device is a NAND flash memory in which two or more cell transistors are connected in parallel on one bit line, and a NAND type in which two or more cell transistors are connected in series on one bit line. It can be divided into flash memory. However, these flash memory devices have the advantage of overcoming vulnerabilities that their operation speed is slower than volatile memory devices, despite the excellent advantage that the stored data is preserved even in the event of a power failure. Various cell structures and driving methods for increasing the speed have been actively studied.

1 illustrates a portion of a cell array of a typical NAND flash memory device.

Referring to FIG. 1, a plurality of active regions (not shown) are formed on a semiconductor substrate in parallel in one direction, and a string select line 1 orthogonal to each of the active regions is formed in a plurality of word lines 3. And the ground selection line 5 are formed in parallel with each other. In addition, active regions adjacent to the ground selection line 5 extend in a direction parallel to the ground selection line 5 to form a common source line 7.

In addition, a bit line 9 is formed on the upper portion of each of the active regions and runs in the same direction as the moving direction of the active region and is electrically connected to the active region. The active region adjacent to the string selection line 1 is connected to the upper bit line 9 by a contact 11, and a string is formed at a point where the string selection line 1 and the active region cross each other. A string select transistor portion composed of select transistors is formed, and a cell transistor portion composed of cell transistors is formed at a point where each of the word lines and the active regions cross each other. In addition, a ground select transistor portion composed of a ground select transistor is formed at a point where the ground select line 5 and the active region cross each other.

In addition, in this field, as the size of each unit device constituting the memory cell is reduced due to the trend of high integration and large capacity of semiconductor memory devices, high integration technology for forming a multilayer structure within a limited area has also been remarkably developed. As part of the multilayer gate structure is widely adopted. For example, the stacked gate structure includes a tunnel oxide film made of a silicon oxide film, a floating gate made of polysilicon, a gate interlayer dielectric film made of an oxide-nitride-oxide (ONO) film, and a control gate film made of polysilicon. .

In the stacked gate structure as described above, the floating gate has a structure in which the floating gate is electrically insulated from and completely isolated from the outside, and uses the property that the current of the memory cell changes according to the electron injection and emission to the floating gate. Will be saved. The electron injection (programming) to the floating gate is performed by FN tunneling (Fowler Nordheim tunneling) through the inter-gate dielectric film existing between the floating gate and the control gate or channel hot electron injection (CHEI) using high temperature electrons in the channel. . In addition, electron emission (erasure) injected into the floating gate is performed through F-N (Fowler-Nordheim) tunneling through an inter-gate dielectric layer existing between the floating gate and the control gate. In this case, the F-N tunneling is generated by applying an electric field of 6 to 8 MV / cm to the tunnel oxide film interposed between the floating gate and the semiconductor substrate. The electric field between the floating gate and the semiconductor substrate is induced by applying a high voltage of 15 to 20 V to the control gate located above the floating gate. Therefore, in order to reduce the program voltage and the erase voltage, it is necessary to increase the coupling ratio of the unit cells constituting the flash memory device. The parameter for determining the coupling ratio is the capacitance of the gate interlayer dielectric film composed of the capacitance of the tunnel oxide film and the ONO film, as expressed by Equation 1 below.

[Equation 1]

Here, Ci denotes the capacitance of the gate interlayer dielectric film, and Ct denotes the capacitance of the tunnel oxide film.

The sizes of Ci and Ct are proportional to the area of the floating gate and inversely proportional to the thickness. Therefore, the thinner the thickness of the floating gate and the larger the area of the floating gate, the better the electrical characteristics of the flash memory device.

2A and 2B illustrate a process of forming a gate electrode of a flash memory device according to the prior art.

First, referring to FIG. 2A, a device isolation film (not shown) is formed by performing a conventional shallow trench isolation (STI) process on a semiconductor substrate 100 doped with doped or en-type impurities.

Subsequently, a silicon oxide film 102, a first polysilicon film 104, an ONO film 106, a second polysilicon film 108, and a tungsten silicide film 110 are sequentially deposited on the semiconductor substrate 100. Then, a photolithography process is performed on the tungsten silicide layer 110 to form a photoresist pattern 112.

Referring to FIG. 2B, the tungsten silicide layer 110 is anisotropically etched using the photosensitive layer pattern 112 as an etching mask to form a tungsten silicide pattern 110-1. In this case, as an etchant for anisotropically etching the tungsten silicide layer 110, for example, an SF ₆ / Cl ₂ mixed gas may be used.

Next, the control gate 108-1 is formed by anisotropically etching the second polysilicon layer 108 using the tungsten silicide pattern 110-1 as an etching mask. In this case, as an etchant for anisotropically etching the second polysilicon film 108, for example, a mixed gas of HBr / O ₂ / He / HeO ₂ may be used.

Subsequently, the ONO film 106 is anisotropically etched using the control gate 108-1 as an etch mask to form a gate interlayer dielectric film 106-1. In this case, as an etchant for anisotropically etching the ONO film 106, for example, a CHF ₃ / Ar mixed gas may be used.

Subsequently, the first polysilicon film 104 is anisotropically etched using the control gate 108-1 and the gate interlayer dielectric film 106-1 as an etching mask to form the floating gate 104-1. In this case, as an etchant for anisotropically etching the first polysilicon film 104, for example, a mixed gas of HBr / O ₂ / He / HeO ₂ may be used.

Subsequently, the silicon oxide film 102 is anisotropically etched using the control gate 108-1, the gate interlayer dielectric film 106-1, and the floating gate 104-1 as an etching mask, thereby tunneling the oxide film 102-1. ). As a result, a tungsten silicide pattern 110-1, a control gate 108-1, a gate interlayer dielectric film 106-1, a floating gate 104-1, and a tunnel oxide film 102-are formed on the semiconductor substrate 100. The stacked gate electrode of the flash memory device constituted by 1) is completed.

However, in forming the gate electrode as described above, the ONO film 106 and the first polysilicon film 104 are conventionally patterned using a dry etching process. Typically, dry etching is an etching process using plasma, in which the accelerated plasma particles move vertically, thereby anisotropically etching the ONO film 106 and the first polysilicon film 104. As a result, the semiconductor substrate 100 adjacent to the ONO film 106 and the first polysilicon film 104 is damaged, causing pitting to occur as indicated by reference numeral A of FIG. 2B.

As such, when fitting occurs in the semiconductor substrate 100, metal is filled in the fitting portion A during subsequent metal deposition or reflow, causing leakage current. As a result, the electrical characteristics of the flash memory device are degraded, which adversely affects reliability and productivity.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a gate electrode of a semiconductor memory device that does not cause fitting to a semiconductor substrate.

Another object of the present invention is to provide a method of manufacturing a gate electrode of a semiconductor memory device capable of preventing the electrical characteristics of the semiconductor memory device from deteriorating.

A method of manufacturing a gate electrode of a semiconductor memory device according to the present invention for achieving the above objects, as a material film for forming a gate electrode on a semiconductor substrate, a silicon oxide film, a first polysilicon film, an upper oxide film-nitride film-lower oxide film Sequentially depositing an ONO film and a second polysilicon film; Etching the second polysilicon layer to form a control gate; Patterning the upper oxide film, the nitride film, and the lower oxide film constituting the ONO film by wet etching, dry etching, and wet etching, respectively, to form a gate interlayer dielectric film; Patterning the first polysilicon layer by dry etching to form a floating gate; Etching the silicon oxide film to form a tunnel oxide film.

Preferably, the upper oxide film is wet etched using HF.

Preferably, the nitride film is dry etched with CH ₂ F ₂ / O ₂ / Ar.

Preferably, the lower oxide layer is wet etched using HF.

Preferably, the first polysilicon is dry etched using HBr / O ₂ .

In addition, a method of manufacturing a gate electrode of a semiconductor memory device according to the present invention for achieving the above objects, as a material film for forming a gate electrode on a semiconductor substrate, a silicon oxide film, a first polysilicon film, an upper oxide film- nitride film- Sequentially depositing an ONO film and a second polysilicon film made of a lower oxide film; Etching the second polysilicon layer to form a control gate; Among the materials constituting the ONO layer, the upper oxide layer is patterned by wet etching, the nitride layer is patterned by dry etching using an etchant having an excellent etching selectivity with respect to the oxide layer, and the lower oxide layer is patterned by wet etching to form gate interlayers. Forming a dielectric film; Forming a floating gate by patterning the first polysilicon film by dry etching using an etchant having an excellent etching selectivity with respect to an oxide film; Etching the silicon oxide film to form a tunnel oxide film.

Preferably, the upper oxide film is wet etched using HF.

Preferably, the nitride film is dry etched with CH ₂ F ₂ / O ₂ / Ar.

Preferably, the lower oxide layer is wet etched using HF.

Preferably, the first polysilicon is dry etched using HBr / O ₂ .

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention. The present invention is not limited to the embodiments disclosed below, but can be embodied in various other forms without departing from the scope of the present invention, and only the embodiments allow the disclosure of the present invention to be complete and common knowledge It is provided to fully inform the person of the scope of the invention.

In general, in implementing a stacked gate electrode of a flash memory device including a control gate, a gate interlayer dielectric film, a floating gate, and a tunnel oxide film, conventionally, an ONO film serving as the gate interlayer dielectric film and a polysilicon film serving as a floating gate are used. Patterned using a dry etching process. As a result, fittings are generated in the semiconductor substrate, thereby greatly reducing the electrical characteristics of the flash memory device.

Accordingly, the present invention provides a semiconductor memory device capable of preventing the formation of a native oxide film on the aluminum under an improved etching process that can effectively eliminate the problem of fitting to the semiconductor substrate while effectively etching the ONO film and the floating gate. The present invention provides a method for manufacturing a gate electrode.

Next, a method of manufacturing a gate electrode of a semiconductor memory device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

3 is a flowchart illustrating a process of forming a gate electrode of a semiconductor memory device according to an exemplary embodiment of the present invention. 4A through 4F are cross-sectional views illustrating a process of forming a gate electrode of a flash memory device according to an exemplary embodiment of the present invention.

First, referring to FIGS. 3 and 4A, a device isolation film (not shown) is formed by performing a conventional shallow trench isolation (STI) process on a semiconductor substrate 300 doped with doped or en-type impurities.

Subsequently, a silicon oxide film 302, a first polysilicon film 304, an ONO film 312, a second polysilicon film 314, and a capping film are formed as a material film for forming a gate electrode on the semiconductor substrate 300. 316 is deposited one after the other. Then, a photolithography process is performed on the tungsten silicide layer 316 to form a photoresist pattern 318 (S200). Here, the capping film 316 may be formed of a tungsten silicon film such as WSix or a tungsten (W) film. The ONO film 312 includes an upper oxide film 306, a nitride film 308, and a lower oxide film 310.

3 and 4B, the tungsten silicide layer 316 is anisotropically etched using the photoresist pattern 318 as an etching mask to form a tungsten silicide pattern 316-1. In this case, as an etchant for anisotropically etching the tungsten silicide layer 316, for example, an SF ₆ / Cl ₂ mixed gas may be used.

Subsequently, the second polysilicon layer 314 is anisotropically etched using the tungsten silicide pattern 316-1 as an etching mask to form the control gate 314-1 (S202). In this case, as an etchant for anisotropically etching the second polysilicon layer 314, for example, a mixed gas of HBr / O ₂ / He / HeO ₂ may be used.

3 and 4C, the upper oxide layer 310 is etched from the ONO layer 312 by using the control gate 314-1 as an etch mask to form an upper oxide layer pattern 310-1. . In this case, the upper oxide layer 310 is patterned by wet etching using HF (S204).

3 and 4D, the nitride layer 308-1 is formed by etching the nitride layer 308 of the ONO layer 312 using the upper oxide layer pattern 310-1 as an etching mask. In this case, the nitride layer 308 is an etchant having an excellent etching selectivity with respect to the oxide layer, and is patterned by dry etching using, for example, CH ₂ F ₂ / O ₂ / Ar (S206).

3 and 4E, by using the nitride film pattern 308-1 as an etching mask, the lower oxide film 306 is etched in the ONO film 312 to form a lower oxide film pattern 306-1. A gate interlayer dielectric film is formed. In this case, the lower oxide layer 306 is patterned by wet etching using HF (S208).

3 and 4F, the first polysilicon layer 304 is etched using the lower oxide layer pattern 306-1 as an etch mask to form a floating gate 304-1. In this case, the first polysilicon layer 304 is an etchant having an excellent etching selectivity with respect to the oxide layer, and is patterned by dry etching using, for example, HBr / O ₂ (S210).

Subsequently, the silicon oxide film 302 is anisotropically etched using the floating gate 304-1 as an etching mask to form a tunnel oxide film 302-1 (S212). As a result, the tungsten silicide pattern 316-1, the control gate 314-1, the ONOs 310-1, 308-1, 306-1, the floating gate 304-1, and the tunnel oxide layer are formed on the semiconductor substrate 300. The stacked gate electrode of the flash memory device composed of 302-1 is completed.

Conventionally, in forming the gate electrode of a flash memory element, the ONO film 106 and the polysilicon film which functions as a floating gate were patterned by the dry etching process. As a result, a fitting phenomenon in which the semiconductor substrate is vertically vertically caused by the accelerated plasma particles has occurred, thereby greatly reducing the electrical characteristics of the flash memory device.

However, as in the present invention, the upper oxide film 310, the nitride film 308, the lower oxide film 306, and the first polysilicon film 304 which function as the floating gate, respectively, which constitute the ONO film 312, respectively. When patterning in the order of wet etching, dry etching, wet etching, and dry etching, the influence of the accelerated plasma is alleviated, thereby eliminating the conventional problem of fitting to the semiconductor substrate, and forming a gate electrode having a good profile.

As described above, in implementing the gate electrode of the flash memory device, wet etching, dry etching, and wet etching the first polysilicon film constituting the ONO film as the upper oxide film, the nitride film, the lower oxide film, and the floating gate, respectively, are performed. By sequentially patterning by etching and dry etching, it is possible to solve the problem that the fitting occurs in the semiconductor substrate. In addition, by preventing the fitting from occurring in the semiconductor substrate, the reliability and productivity of the flash memory device can be further improved.

Claims (18)

In the method of manufacturing a gate electrode of a semiconductor memory device: Depositing a silicon oxide film, a first polysilicon film, an ONO film made of an upper oxide film-nitride film and a lower oxide film, and a second polysilicon film in order to form a gate electrode on the semiconductor substrate; Etching the second polysilicon layer to form a control gate; Patterning the upper oxide film, the nitride film, and the lower oxide film constituting the ONO film by wet etching, dry etching, and wet etching, respectively, to form a gate interlayer dielectric film; Patterning the first polysilicon layer by dry etching to form a floating gate; Etching the silicon oxide film to form a tunnel oxide film. The method of claim 1, wherein the upper oxide layer is wet etched using HF. The method of claim 2, wherein the nitride layer is dry etched with CH ₂ F ₂ / O ₂ / Ar. The method of claim 3, wherein the lower oxide layer is wet etched using HF. The method of claim 4, wherein the first polysilicon is dry-etched using HBr / O ₂ . The method of claim 5, wherein the second polysilicon layer is dry etched using HBr / O ₂ / He / HeO ₂ . The method of claim 6, further comprising depositing a capping layer over the second polysilicon layer. 8. The method of claim 7, wherein the capping film is formed of a tungsten silicon film or a tungsten film. The method of claim 8, wherein the capping layer is dry etched using SF ₆ / Cl ₂ . In the method of manufacturing a gate electrode of a semiconductor memory device: Depositing a silicon oxide film, a first polysilicon film, an ONO film made of an upper oxide film-nitride film and a lower oxide film, and a second polysilicon film in order to form a gate electrode on the semiconductor substrate; Etching the second polysilicon layer to form a control gate; Among the materials constituting the ONO layer, the upper oxide layer is patterned by wet etching, the nitride layer is patterned by dry etching using an etchant having an excellent etching selectivity with respect to the oxide layer, and the lower oxide layer is patterned by wet etching to form gate interlayers. Forming a dielectric film; Forming a floating gate by patterning the first polysilicon film by dry etching using an etchant having an excellent etching selectivity with respect to an oxide film; Etching the silicon oxide film to form a tunnel oxide film. The method of claim 10, wherein the upper oxide layer is wet etched using HF. The method of claim 11, wherein the nitride layer is dry etched with CH ₂ F ₂ / O ₂ / Ar. The method of claim 12, wherein the lower oxide layer is wet etched using HF. The method of claim 13, wherein the first polysilicon is dry etched using HBr / O ₂ . 15. The method of claim 14, wherein the second polysilicon layer is dry etched using HBr / O ₂ / He / HeO ₂ . 16. The method of claim 15, further comprising depositing a capping layer over the second polysilicon layer. 17. The method of claim 16, wherein the capping film is formed of a tungsten silicon film or a tungsten film. The method of claim 17, wherein the capping layer is dry etched using SF ₆ / Cl ₂ .

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