KR100714273B1 - butting contact forming method for semiconductor memory device - Google Patents

Abstract

The present invention relates to a method of forming a butt contact in a semiconductor memory device. In the present invention, when the butting contact of the semiconductor memory device is formed, the hard mask layer and the control gate layer thereunder are dry-etched by an in situ process using the same etching etchant. The etching etchant has a low etching selectivity with respect to the material layer forming the hard mask layer and the control gate layer, thereby obtaining a good profile without causing an undercut at the boundary between the conductive layer and the mask layer. It becomes possible. In addition, by using one kind of etching etchant to etch the hard mask layer and the control gate layer in one step process, overall process time can be shortened and particle generation can be minimized. It can be improved more.

Semiconductors, Butting Contacts, Floating Gates, Control Gates, ONO

Description

Butting contact forming method for semiconductor memory device

1 illustrates a portion of a cell array region of a typical NAND flash memory device.

2A and 2B illustrate a cross-sectional structure of a gate region for explaining a butt contact forming method according to the related art.

3A to 3C illustrate a cross-sectional structure of a gate area for explaining a method of forming a butt contact of a flash memory device according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100: semiconductor substrate 102: device isolation film

104: tunnel oxide film 106: floating gate

108: ONO film 110: second polysilicon film

112: tungsten silicide film 114: control gate

116: PEOX film 118: ARL film

120: hard mask layer 122: primary opening

124: Butting Contact Hole

The present invention relates to a method of manufacturing a semiconductor memory device, and more particularly, to a method of forming a butt contact of a semiconductor memory device.

Semiconductor memory devices used to store data may be generally classified into volatile memory devices and nonvolatile memory devices. In the semiconductor memory device, a volatile memory device represented by DRAM (Dynamic Random Access Memory) or SRAM (Static Rrandom Access Memory) is characterized by fast data input / output operation but loss of stored data when power supply is interrupted. On the other hand, nonvolatile memory devices represented by EPROM (Erasable Programmable Read Only Memory) or EEPROM (Electrically Erasable Programmable Read Only Memory) are slow in input / output operation of data but retain stored data even when power supply is interrupted. There is this. Therefore, such a nonvolatile memory device can be widely used in a situation where power cannot always be supplied or power supply is intermittently interrupted, such as a memory card or a mobile telephone system for storing music or image data.

On the other hand, among these non-volatile memory devices, in particular, the flash memory device adopting the 1 Tr / 1 Cell structure of the batch erasing method to overcome the integration limit of the EEPROM can freely input and output data electrically, power consumption It is expected to be able to replace hard disk drive (HDD) of computer in the future because of its low speed and high speed programming, and the demand is gradually increasing. Such a flash memory device is a NAND flash memory in which two or more cell transistors are connected in parallel on one bit line, and a NAND type in which two or more cell transistors are connected in series on one bit line. It can be divided into flash memory. However, the flash memory device has a weakness of operating speed compared to volatile memory device despite the excellent advantage that the stored data is preserved even in the event of power failure. Various cell structures and driving methods have been actively studied.

1 illustrates a portion of a cell array region of a typical NAND flash memory device.

Referring to FIG. 1, a plurality of active regions (not shown) are formed on a semiconductor substrate in parallel in one direction, and a string select line 1 orthogonal to each of the active regions is formed in a plurality of word lines 3. And the ground selection line 5 are formed in parallel with each other. In addition, active regions adjacent to the ground selection line 5 extend in a direction parallel to the ground selection line 5 to form a common source line 7.

In addition, a bit line 9 is formed on the upper portion of each of the active regions and runs in the same direction as the moving direction of the active region and is electrically connected to the active region. The active region adjacent to the string selection line 1 is connected to the upper bit line 9 by a contact 11, and a string is formed at a point where the string selection line 1 and the active region cross each other. A string select transistor portion composed of select transistors is formed, and a cell transistor portion composed of cell transistors is formed at a point where each of the word lines and the active regions cross each other. In addition, a ground select transistor portion composed of a ground select transistor is formed at a point where the ground select line 5 and the active region cross each other.

Meanwhile, the gate region of each transistor includes a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate, and the control gate functions as a word line crossing the active region. The floating gates of the cell transistors are separated from each other by an isolation layer, and the string select transistor, the plurality of cell transistors, and the ground select transistor disposed on one active region constitute a unit string. Here, the string selection transistor for selecting the unit string and the ground selection transistor for selecting the ground are transistors that do not require a floating gate for data storage, so that the floating gate and the control gate are connected to each other using a metal line through a butting contact. To be electrically connected to each other. Thus, the string select transistor and the ground select transistor operate as a MOS transistor having an electrically gate.

The butting contact is generally formed by a photolithography process. The photolithography process forms a hard mask layer pattern on a word line, and then sequentially exposes a word line (control gate) and an interlayer dielectric layer (dielectric film) exposed underneath. It is formed by dry etching. Such butting contact forming methods are disclosed in US Pat. Nos. 6,515,329, 6,380,032, and the like, with reference to FIGS. 2A and 2B below.

First, referring to FIG. 2A, a shallow trench isolation layer 12 is formed on a semiconductor substrate 10 in which a doped or en-type impurity is doped by a conventional shallow trench isolation (STI) process. In addition, a tunnel oxide layer 14, a floating gate 16 made of polysilicon, and an ONO functioning as a dielectric layer are disposed on an active portion defined by the shallow trench isolation layer 12. A control gate 24 film made of a film, polysilicon 20 and tungsten silicide 22 is sequentially stacked to form a gate region.

The floating gate 16 is electrically insulated from the outside and has an isolated structure. The floating gate 16 stores data using a property in which a current of the memory cell changes as electrons are injected into and emitted from the floating gate 16. The electron injection into the floating gate 16 is performed by a channel hot electron injection (CHEI) method using high temperature electrons in the channel, and the electron emission is an inter-gate dielectric between the floating gate 16 and the control gate 24. This is accomplished through Fowler-Nordheim tunneling through the membrane. At this time, the voltage applied to the control gate 24 is applied to the floating gate by a predetermined amount according to the coupling ratio (coupling ratio), the variable that determines the coupling ratio and the capacitance (capacitance) of the tunnel oxide film (capacitance) This is the ONO film 18 capacitance. Therefore, the area of the floating gate that determines the size of the capacitance is important. The thinner the thickness of the floating gate, the larger the area of the floating gate, the better the electrical characteristics of the flash memory device.

On the other hand, in order to form a butt contact in the gate region of the flash memory device as described above, the PEOX film 26 having a thickness of 2300 Å and the ARL film 28 having a thickness of 800 Å are sequentially deposited on the control gate 24. The mask layer 30 is formed. Thereafter, a photoresist film (not shown) is applied on the ARL film 28, followed by a general photolithography process to dry-etch the hard mask layer 30.

Next, referring to FIG. 2B, the tungsten silicide layer 22 and the poly are formed by using the dry etched hard mask 30 as a self-aligned etching mask and using the ONO layer 18 as an etching stopping layer. The control gate 24 film made of the silicon film 20 is dry etched. Subsequently, the ONO layer 18 and the floating gate layer 16 below are dry-etched in order to form a butting contact hole 32 for forming a butting contact.

However, as the degree of integration of semiconductor devices increases and the gate line width of the active region is narrowed, there is a need for a pure flash product with little particle generation. Therefore, in performing the dry etching process for forming the butting contact, the hard mask layer 30 is etched using a first etching etchant consisting of, for example, CHF ₃ and Ar mixed gas, and the control gate 24. ) Was subjected to a two-step process of etching using a second etchant consisting of HBr, O ₂ and He mixed gas. However, the etching etchant consisting of CHF ₃ and Ar mixed gas used to etch the hard mask layer 30 has a high selection for the tungsten silicide 22 and the polysilicon 20 constituting the control gate 24. There is a characteristic that has a ratio. Therefore, there is a problem in that an undercut occurs due to a sudden film change in the boundary portion (reference A) between the hard mask layer 30 and the control gate 24 in the etching process for forming the butting contact. In particular, the boundary region between the etching mask 30 made of the ARL film 28 and the PEOX film 26 and the control gate 24 film made of the polysilicon 20 and the tungsten silicide 22 determines the gate cell distribution. Since it is an important part, when an undercut occurs in such an area, the size of the gate pattern becomes nonuniform, which greatly reduces the productivity and reliability of the entire semiconductor device.
In addition, when the hard mask 30 and the control gate 24 are etched in a two-step process using respective etching etchant, two types of etching etchant should be injected and discharged, so that the overall processing time becomes long. There is this. In addition, since the etching etchant used in the etching process can be seen as particles already, when two kinds of etching etchants are used, they not only increase the contamination of the etching equipment but also adversely affect the semiconductor device manufacturing process. It will lower overall productivity and reliability.

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An object of the present invention for solving the conventional problems as described above, in the etching process for forming a butt contact in the adjacent gate region, it is possible to minimize the occurrence of undercut due to the difference in the quality of the film constituting the hard mask layer and the control gate. The present invention provides a method of forming a butt contact in a semiconductor memory device.

Another object of the present invention is to provide a method of forming a butt contact of a semiconductor memory device which can further shorten the entire etching process time for forming a butt contact.

Another object of the present invention is to provide a method for forming a butt contact of a semiconductor memory device, which can further improve productivity and reliability by minimizing the influence of particles generated when the butt contact is formed.

A butting contact forming method of a semiconductor memory device according to the present invention for achieving the above objects, the first conductive film, dielectric film, control gate functioning as a tunnel oxide film, a floating gate on the active region of the semiconductor substrate; Depositing a conductive film in sequence; After the hard mask layer is formed on the second conductive layer, the hard mask layer and the second conductive layer are in situ using an etching etchant having a low etching selectivity with respect to the hard mask layer and the second conductive layer. Etching to a process; Etching the dielectric layer and the control gate using the hard mask layer and the second conductive layer pattern as an etch mask to form openings for forming butt contacts; Filling a conductive material in the opening to electrically connect the control gate and the floating gate.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention. The present invention is not limited to the embodiments disclosed below, but can be embodied in various other forms without departing from the scope of the present invention, and only the embodiments allow the disclosure of the present invention to be complete and common knowledge It is provided to fully inform the person of the scope of the invention.

3A to 3C are cross-sectional views illustrating a butt contact forming method of a flash memory device according to an exemplary embodiment of the present invention.

First, referring to FIG. 3A, a field trench and an active region may be formed by performing a conventional shallow trench isolation (STI) process on a semiconductor substrate 100 doped with dopant (P) or en (N) type impurities. A device isolation film 102 is formed for definition. In this case, the device isolation layer 102 may be formed of, for example, O ₃ -TEE (Tetra Ethyl Ortho Silicate), BPSG (Boron Phosphorus Silicate Glass), SOG, or the like.

Subsequently, a 100 nm thick tunnel oxide film 104 is deposited in an active region defined by the device isolation film 102, and then, as a floating gate 106, a first polysilicon film having a thickness of 2000 to 2500 ms, for example. It can be formed as.

Subsequently, an ONO film 108 having a thickness of, for example, 150 to 200 Å is deposited on the floating gate 106 as an interlayer dielectric film. Then, a control gate 114 is formed by sequentially depositing a second polysilicon film 110 having a thickness of 1000 mW and a tungsten silicide film 112 having a thickness of 1000 mW, for example, on the ONO film 108. In this case, in addition to the tungsten silicide layer 112 having a low resistance on the second polysilicon layer 110, tungsten may be deposited. In the case of depositing tungsten, it is preferable to further form WSi and WN as barrier metals. Do.

Subsequently, a hard mask layer 120 is formed by sequentially depositing, for example, a PEOX film 116 having a thickness of 2300 μs and an ARL film 118 having a thickness of 800 μs on the control gate 114.

Subsequently, referring to FIG. 3B, after forming a photoresist film (not shown) on the hard mask layer 120, the ARL film 118 forming the hard mask layer 120 using the same etching etchant. ) And the PEOX film 116 is dry-etched, and then the tungsten silicide film 112 and the second polysilicon film 110 forming the control gate 114 are also dry-etched by an in situ process to form a butting contact. To form a primary opening 122.

As such, it is a key process of the present invention to dry-etch and pattern the hard mask layer 120 and the control gate 114 in an in situ process using the same etching etchant. As an etching etchant for etching the hard mask layer 120 and the control gate 114 in an in situ process, an etching selector for a material forming the hard mask 120 and a material forming the control gate 114 is performed. It is required to use etchant with low ratio. Accordingly, in the present invention, as an etchant having a low etching selectivity for each material film forming the hard mask 120 and the control gate 114 as described above, an etchant consisting of a mixture of CF ₄ and He, for example, Is used.

In the dry etching process for etching the hard mask 120 and the control gate 114 in an in situ process, the flow rates of CF ₄ and He are preferably maintained at 1 to 500 sccm, respectively, RF power is preferably maintained at 50 to 1000W. In addition, the pressure inside the chamber is preferably maintained at 5 to 100 mT, and the magnetic flux density is preferably maintained at 0 to 30 Gauss, for example.

Conventionally, in forming a butt contact of a flash memory device, a hard mask is patterned by performing a photolithography process using a first etching etchant. Then, using the second etching etchant (HBr, O ₂ and He mixed gas) of a different component than the first etching etchant (CHF ₃ and Ar mixed gas) to the hard mask pattern to a self-aligned mask pattern 2 step process of dry etching the control gate exposed to the lower part was implemented. The first etching etchant and the second etching etchant are etching etches having a high selectivity with respect to the material film forming the control gate and the hard mask layer, respectively. The first etching etchant and the second etching etchant When each dry etching process is performed on the hard mask and the control gate by using the same, an undercut occurs in a boundary area between the hard mask layer and the control gate, thereby preventing a good profile from being obtained. In addition, since the etching etchant used in the etching process itself is included in the particles in a broad sense, when using two types of etching etchant, there is a disadvantage in that the inside of the etching facility as well as the semiconductor substrate may be contaminated.

Therefore, in the present invention, in order to solve the above-mentioned problems, the same etching etchant is used without dividing the hard mask layer 120 and the control gate 114 into a two-step process using different etching etchant. By using dry etching in the same chamber in the same chamber, the problem that the undercut is generated in the boundary region (reference numeral B) between the hard mask and the control gate is solved. In the etching of the hard mask layer 120 and the control gate 114 as described above, one type of etching etchant is used to minimize particle generation to further reduce the risk of contamination of the semiconductor substrate and the etching facility. do.

Subsequently, referring to FIG. 3C, the ONO film 108 and the floating gate 106 below which the surface thereof is exposed due to the first opening 122 are sequentially etched to dry the second opening, that is, A butting contact hole 124 for forming a butting contact is formed.

Subsequently, although not illustrated in the drawing, a butting contact for electrically connecting the control gate 114 and the floating gate 106 is completed by filling a conductive material such as metal into the butting contact hole 124.

As described above, conventionally, the hard mask layer and the control gate are dry-etched by dividing the hard mask layer and the control gate into two step processes in which different etching etchants are used, thereby causing an undercut in the boundary region between the hard mask layer and the control gate. . Accordingly, in order to solve the conventional problems, the hard mask and the control gate may be identified by using the same etching etchant having the minimum etching selectivity with respect to the material layer forming the hard mask layer and the material layer forming the control gate. Dry etch by the drilling process. Thus, by dry etching the hard mask film and the control gate in a one-step process using the same etching etchant, the conventional problem that undercuts are generated in the boundary area between the hard mask film and the control gate is solved, and a good profile is cut. A contact can be formed. In addition, by using one type of etching etchant to pattern the hard mask and the control gate in an in situ process, particle generation can be minimized to further improve the reliability of the semiconductor device. By shortening, it becomes possible to contribute to productivity improvement.

In the above description of the butt contact forming method according to the present invention, a flash memory device is provided. However, this is only a preferred embodiment of the present invention and may be applied to all semiconductor memory devices including the flash memory device. to be.

As described above, in the present invention, in etching the hard mask layer and the control gate layer thereunder to form a butting contact of the semiconductor memory device, the material layer forming the hard mask layer and the material layer forming the control gate layer are etched. Dry etching is performed in situ using the same etching etchant having low etching selectivity. As such, the etch etchant does not cause undercuts at the boundary between the conductive layer and the mask layer due to the low etch selectivity of the material layers constituting the hard mask layer and the control gate layer, thereby obtaining a good profile.

In addition, by using the same etching etchant to etch the hard mask layer and the control gate layer in the same chamber, the overall process time can be further shortened and particle generation can be minimized. It can be improved.

Claims (20)

In the method of forming a contact of a semiconductor memory device that can minimize the occurrence of undercut: After etching the hard mask layer deposited on the first conductive film functioning as the control gate, the first conductive film is in-situ using the same etching etchant as the etching etchant used to etch the hard mask layer. Etching with; Using the etched hard mask layer and the first conductive layer pattern as an etch mask to etch a second conductive layer serving as a control layer and a dielectric layer under the first conductive layer to form an opening for forming a butt contact. Wow; And electrically connecting the first conductive layer and the second conductive layer by filling a conductive material in the opening. The method of claim 1, wherein the first conductive film is formed of any one of a single conductive film consisting of a polysilicon film having a thickness of 1000 Å, or a double conductive film made of a tungsten silicide film having a thickness of 1000 Å and a polysilicon film having a thickness of 1000 Å. A contact forming method of a semiconductor memory device. The method of claim 1, wherein the hard mask layer is formed by depositing a PEOX film having a thickness of 2300 μs and then further depositing an ARL film having a thickness of 800 μs thereon. The method of claim 1, wherein the etching etchant for etching the hard mask layer and the first conductive layer is a mixed gas comprising CF ₄ and He. In the method of forming a contact of a semiconductor memory device that can minimize the occurrence of undercut: Depositing a first conductive film functioning as a control gate; Depositing a hard mask layer on the first conductive layer; Etching the hard mask layer using an etchant for etching the hard mask layer and the first conductive film in the same ratio, and then etching the first conductive film by an in situ process. A method of forming a contact in a semiconductor memory device. The method of claim 5, wherein the first conductive film is formed of any one of a single conductive film consisting of a polysilicon film of 1000 Å thickness, or a double conductive film consisting of a tungsten silicide film of 1000 Å thickness and a polysilicon film of 1000 Å thickness. A contact forming method of a semiconductor memory device. The method of claim 5, wherein the hard mask layer is formed by depositing a PEOX film having a thickness of 2300 μs and then further depositing an ARL film having a thickness of 800 μs thereon. The contact forming method of claim 5, wherein the etching etchant for etching the hard mask layer and the first conductive layer in the same ratio is a mixed gas consisting of CF ₄ and He. In the method of forming a butt contact of a semiconductor memory device: Depositing a tunnel oxide film, a first conductive film functioning as a floating gate, a dielectric film, and a second conductive film functioning as a control gate on an active region of the semiconductor substrate in sequence; After the hard mask layer is formed on the second conductive layer, the hard mask layer and the second conductive layer are formed by using an etching etchant having low etching selectivity characteristics with respect to the hard mask layer and the second conductive layer. Etching the film in an in-situ process; Etching the dielectric layer and the control gate using the hard mask layer and the second conductive layer pattern as an etch mask to form openings for forming butt contacts; Filling a conductive material in the opening to electrically connect the control gate and the floating gate. 10. The method of claim 9, wherein the first conductive film is formed of a polysilicon film having a thickness of 2000 to 2500 Å. The method of claim 10, wherein the dielectric layer is formed of an ONO layer having a thickness of about 150 to about 200 GHz. 12. The semiconductor device according to claim 11, wherein the second conductive film is formed of a single conductive film made of a polysilicon film having a thickness of 1000 mW, or a double conductive film made of a tungsten silicide film having a thickness of 1000 mW and a polysilicon film having a thickness of 1000 mW. A method of forming a butt contact in a memory device. The method of claim 12, wherein the hard mask layer is formed by depositing a PEOX film having a thickness of 2300 μs and then further depositing an ARL film having a thickness of 800 μs thereon. 15. The method of claim 13, wherein the etching etchant for etching the hard mask layer and the second conductive layer is a mixed gas consisting of CF ₄ and He. 15. The method of claim 14, wherein the flow rates of CF ₄ and He are maintained at 1 to 500 sccm, respectively. 16. The method of claim 15, wherein the RF power in the chamber is maintained at 50 to 100 W during the etching process using CF ₄ and He as an etching etchant. 17. The method of claim 16, wherein the pressure inside the chamber is maintained at 5 to 100 mT during the etching process using CF ₄ and He as an etching etchant. 18. The method of claim 17, wherein the magnetic flux density within the chamber is maintained at 0 to 30 Gauss during the etching process using CF ₄ and He as etching etchant. 19. The method of claim 18, wherein the second conductive film is formed by depositing a 1000 tungsten silicide film and further depositing a tungsten film thereon. 20. The method of claim 19, wherein when the tungsten film is deposited over the tungsten silicide film having a thickness of 1000 으로서 as the second conductive film, WSi and WN are further formed as a barrier metal.

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