KR20060029772A - Non volatile memory device and method for manufacturing thereof - Google Patents

Abstract

The present invention relates to a structure of a nonvolatile memory device and a method of manufacturing the same. In the present invention, in forming a stacked gate of a flash memory device, the floating gate of the stacked gates is formed in a fence-shaped concave-convex structure. As the surface area of the floating gate is greatly increased, the contact area with the inter-gate dielectric film (ONO film) is also increased, thereby improving data program and erase characteristics of the flash memory device. In addition, when the floating gate is formed in a Higgs-shaped concave-convex structure, the surface area can be increased while lowering the deposition thickness of the conductive film functioning as the floating gate, thereby securing a gap fill margin when filling the insulating film for forming the STI. In addition, even when the conductive film is deposited for forming the floating gate, it is possible to minimize the problem that defects in the shape of a seam are generated. In addition, by lowering the deposition thickness of the conductive film serving as the floating gate, the step difference between the cell array region and the peripheral circuit region of the flash memory device can be lowered to facilitate subsequent processing, thereby improving productivity.

Flash Memory, Floating Gate, Control Gate, ONO, Seam

Description

Non-volatile memory device and method for manufacturing the same             

1 illustrates a stacked gate structure of a flash memory device according to the prior art.

2A through 2H sequentially illustrate a method of manufacturing a stacked gate of a flash memory device according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

100 semiconductor substrate 102 pad oxide film

104: silicon nitride film 106: photosensitive film

108: trench 110: insulating film

112: STI film 114: tunnel oxide film

116a: floating gate 118a: gate interlayer dielectric film

120a: control gate

The present invention relates to a nonvolatile memory device and a method of manufacturing the same, and more particularly, to a nonvolatile memory device having an improved floating gate structure that can further improve the program and erase speed, and a method of manufacturing the same.

Semiconductor memory devices used to store data may be generally classified into volatile memory devices and nonvolatile memory devices. In the semiconductor memory device, a volatile memory device represented by DRAM (Dynamic Random Access Memory) or SRAM (Static Rrandom Access Memory) is characterized by fast data input / output operation but loss of stored data when power supply is interrupted. On the other hand, nonvolatile memory devices represented by EPROM (Erasable Programmable Read Only Memory) or EEPROM (Electrically Erasable Programmable Read Only Memory) are slow in input / output operation of data but retain stored data even when power supply is interrupted. There is this. Therefore, such a nonvolatile memory device can be widely used in a situation where power cannot always be supplied or power supply is intermittently interrupted, such as a memory card or a mobile telephone system for storing music or image data. Among these non-volatile memory devices, in particular, the flash memory device adopting the 1 Tr / 1 Cell structure of the batch erasing method to overcome the limitation of the integration density of EEPROM can freely input / output data electrically and consumes less power. It is expected that the high-speed programming will be able to replace the hard disk drive (HDD) of the computer in the future, and the demand is gradually increasing. However, the flash memory device has a weakness of operating speed compared to volatile memory device despite the excellent advantage that the stored data is preserved even in the event of power failure. Various cell structures and driving methods have been actively studied.

On the other hand, as the size of each unit device constituting the memory cell is reduced due to the trend of high integration and large capacity of semiconductor devices, high integration technology for forming a multilayer structure within a limited area is also developing remarkably, and as a part of such high integration technology, The stacked gate structure is widely adopted as a cell transistor of a flash memory device.

Figure 1 below shows a typical stacked gate structure of a flash memory device.

Referring to FIG. 1, a shallow trench isolation layer 12 is formed by a conventional shallow trench isolation (STI) process on a semiconductor substrate doped with doped or en-type impurities. A tunnel oxide film 14, a floating gate 16 made of polysilicon, an ONO (Oxide-Nitride-Oxide) on the channel region (reference A) in an active defined by the shallow trench isolation layer 12 A gate interlayer dielectric film 18 made of a film and a control gate 20 film made of polysilicon are sequentially stacked to form a gate region. In this case, a tungsten silicon film such as WSix or a tungsten (W) film may be further formed on the control gate 20.

The floating gate has an isolated structure that is completely electrically insulated from the outside, and stores data using a property in which a current of a memory cell changes as electrons are injected and emitted into the floating gate. The electron injection into the floating gate is performed by CHEI (Channel Hot Electron Injection) method using high temperature electrons in the channel, and electron emission is carried out through the interlayer gate dielectric film between the floating gate and the control gate. This is done through tunneling. At this time, the voltage applied to the control gate is applied to the floating gate by a certain amount of voltage according to the coupling ratio (coupling ratio), the variable that determines the coupling ratio is the capacitance (capacitance) of the tunnel oxide film and the ONO film The capacitance of the interlayer dielectric film 18 thus formed. Therefore, the area of the floating gate that determines the size of the capacitance is important. The thinner the thickness of the floating gate, the larger the area of the floating gate, the better the electrical characteristics of the flash memory device.

However, as the degree of integration of semiconductor devices increases and the gate line width of the active region is narrowed, the spread of the program and erase voltages of the flash memory device increases according to the dispersion of the photolithography process and the etching process for forming such a gate pattern. There is a problem that arises. In addition, when the thickness of the floating gate is increased to increase the total area of the floating gate, a gap fill margin of the STI film is reduced.

Therefore, as a method for solving such a problem, as described with reference to FIG. 1, after forming the STI, a floating gate was formed in a self aligned structure. However, when forming the STI, a trench is formed to have sidewall slopes of about 85 degrees in order to secure a gap fill margin, which may help secure a gap fill margin of the trench, but may form a subsequent floating gate. In the case of polysilicon deposition for the deposition of the polysilicon film to form a floating gate due to the inclination of the trench sidewalls, there is a problem that a defect occurs in the form of a seam (seam) to form a bridge.

As described above, in the stacked gate structure of the flash memory device according to the related art, when the height of the floating gate is increased to improve the electrical characteristics of the flash memory device, the gap fill margin of the STI film is reduced, as well as the cell array. The high step between the area and the area of the peripheral circuit causes a variety of difficulties in the subsequent process.

In the flash memory device, the program and erase characteristics are very important factors that determine the quality of the device, and in order to sufficiently secure the coupling ratio of the cell transistors that influence the program and erase characteristics, the surface area of the floating gate is increased. Is the main concern. Therefore, there is an urgent need for the development of an improved structure of the floating gate that can secure sufficient surface area without adversely affecting other processes.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile memory device having a floating gate having an increased surface area and a method of manufacturing the same.

Another object of the present invention is to provide a nonvolatile memory device having a floating gate having a sufficiently increased surface area without reducing a gap fill margin of an STI film, and a method of manufacturing the same.

Another object of the present invention is to provide a non-volatile memory device having an improved floating gate that does not cause shim-shaped defects when depositing a conductive film for forming a control gate, and a method of manufacturing the same.

Another object of the present invention is to provide a nonvolatile memory device and a method of manufacturing the same, which may improve the program and erase operations of a flash memory device by improving the floating gate structure.

A nonvolatile memory device according to the present invention for achieving the above objects, the tunnel oxide film formed on the active region of the semiconductor substrate; A floating gate formed on an upper portion of the tunnel oxide layer and having an uneven shape in which an upper surface area is wider than a lower surface area; A gate interlayer dielectric film formed on the floating gate according to a concave-convex shape of an upper surface of the floating gate; And a control gate formed over the gate interlayer dielectric layer.

In addition, a method of manufacturing a nonvolatile memory device according to the present invention for achieving the above objects comprises the steps of: forming a tunnel oxide film on an active region of a semiconductor substrate; Forming a floating gate on the tunnel oxide layer, the floating gate having an uneven shape in which an upper surface area is larger than a lower surface area; Forming a gate interlayer dielectric film on the floating gate according to a concave-convex shape of an upper surface of the floating gate; And forming a control gate over the gate interlayer dielectric layer.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention. The present invention is not limited to the embodiments disclosed below, but can be embodied in various other forms without departing from the scope of the present invention, and only the embodiments allow the disclosure of the present invention to be complete and common knowledge It is provided to fully inform the person of the scope of the invention.

2A through 2H sequentially illustrate a method of manufacturing a stacked gate of a flash memory device according to an exemplary embodiment of the present invention. In this embodiment, a method of manufacturing a stacked gate for one memory cell is described.

First, referring to FIG. 2A, a pad oxide film 102 and a nitride film 104 are sequentially deposited on an upper surface of a semiconductor substrate 100 on which doped or en-type impurities are doped. Then, a positive type or a negative type photosensitive film 106 is coated on the nitride film 104. In this embodiment, a positive type photosensitive film is applied. At this time, the pad oxide film is, for example, deposited at a thickness of 100 GPa, and the nitride film is deposited, for example, at 2000 GPa.                     

Subsequently, a conventional photolithography process is performed on the semiconductor substrate 100 to which the positive photosensitive film 106 is coated to form a trench 108 for forming a shallow trench isolation layer (STI). In this case, the trench 108 is formed to have a positive sidewall slop of about 85 degrees to secure a gap fill margin.

Referring to FIG. 2B, after the photolithography process for forming the trench 108 is completed, the photosensitive layer 106 applied on the nitride layer 104 is removed. Then, the trench 108 is filled to deposit an insulating film 110 for forming an STI. In this case, as the insulating layer 110, for example, O ₃ -TEE (Tetra Ethyl Ortho Silicate), BPSG (Boron Phosphorus Silicate Glass), SOG, or the like may be applied.

Referring to FIG. 2C, an upper surface of the nitride film 104 may be subjected to a planarization process such as etch back or chemical mechanical polishing (CMP) on the semiconductor substrate on which the insulating film 110 is deposited. Expose As a result, the STI 112 defining the active region and the field region with respect to the semiconductor substrate 100 is completed.

Referring to FIG. 2D, the nitride film 104 and the pad oxide film 102 on the semiconductor substrate 100 on which the STI 112 is formed are removed. As a result, an active region indicated by reference numeral B is defined in the semiconductor substrate 100.

In this case, the nitride film 104 may be removed by, for example, phosphoric acid, and the pad oxide film 102 may be removed by, for example, hafnium (HF). In the process of removing the nitride film 104 using the phosphoric acid, the STI is not lost due to an etching selectivity between the nitride film and the insulating film forming the STI. However, in the process of removing the pad oxide film 102 using hafnium, a portion of the STI may be removed due to a low etching selectivity between the insulating film forming the STI and the pad oxide film, but compared to the pad oxide film. The relatively thick thickness does not affect the implementation of the flash memory device according to the invention.

Subsequently, referring to FIG. 2E, the tunnel oxide layer 114 is deposited on the entire surface of the semiconductor substrate 100 in which the active region B is defined. Subsequently, a first polysilicon film 116 is deposited as a conductive film for forming a floating gate on the semiconductor substrate 100 on which the tunnel oxide film 114 is deposited. In this case, the first polysilicon layer 116 is deposited below a predetermined thickness of the CD (Critical Dimension) of the active region indicated by reference B on the FIG. 2D to increase the total surface area. to be. In this way, by depositing the surface area of the first polysilicon film 116 as wide as possible, the deposition thickness in the vertical direction of the first polysilicon film 116 is kept low and does not adversely affect subsequent processes, but between gate layers. The contact area with the ONO film serving as the dielectric film can be increased, so that the electrical characteristics of the flash memory device can be improved.

Referring to FIG. 2F, a dry etching process such as a photolithography process may be performed on the first polysilicon layer 116 to form the floating gate 116a of the stacked gate structure of the flash memory device.                     

As shown, in the present invention, by forming the floating gate 116a in a concave-convex structure having a central concave shape, the surface area of the floating gate 116a can be significantly increased as compared to a conventional stacked structure. By increasing the surface area of the film, it is possible to further increase the contact area with the ONO film functioning as the interlayer dielectric film to be deposited in a subsequent process.

The H-shaped floating gate 116a may be formed by lowering the deposition thickness of the first polysilicon film 116. The floating gate 116a may be formed by thinly forming the first polysilicon film 116 functioning as the floating gate 116a. Accordingly, the thickness of the nitride film 104 for forming the STI can be lowered to secure a gap fill margin of the insulating film when forming the STI, and to solve the problem of a structural seam occurring during deposition of the polysilicon film for forming the floating gate. Will be. As a result, the data program and erase characteristics of the flash memory device can be improved, and the productivity between the cell array region and the peripheral circuit region can be lowered to facilitate the subsequent process.

Referring to FIG. 2G, an ONO film 118 to be patterned as a gate interlayer dielectric film is deposited on the upper surface of the semiconductor substrate 100 where the floating gate 116a is formed, for example, 150-200 占 thick. Subsequently, a second polysilicon film 120 is deposited on the ONO film 118 as a conductive film to be patterned as a control gate.

At this time, after the deposition of the ONO film 118, the horizontal distance (reference C) between the ONO film 118 should be secured at least 50 kHz. This is because when the second polysilicon film 120 for forming the control gate is formed on the ONO film 118, the seam may be generated when the CD between the ONO films 118 is 50 mV or less. Therefore, in order to prevent such a problem in advance, the horizontal distance between the ONO film 118 is maintained to be 50 m 3 or more, thereby minimizing the occurrence of shims.

Although not illustrated, WSix or tungsten having low resistance may be further formed on the second polysilicon film 120. In the case of forming the tungsten, it is preferable to further form WSi and WN as barrier metals.

Referring to FIG. 2H, a dry etching process such as photolithography is performed on the ONO film 118 and the second polysilicon film 120 to form a gate interlayer dielectric film 118a and a control gate 120a. The stacked gate structure of the flash memory device is completed.

As described above, in the present invention, in forming the stacked gates of the flash memory device, by forming the floating gates of the stacked gates in the shape of a fence, the surface area is greatly increased. As such, when the surface area of the floating gate is increased, the contact area with the inter-gate dielectric film (ONO film) also naturally increases, thereby improving the data program and erase characteristics of the flash memory device. In addition, while increasing the surface area of the floating gate while lowering the deposition thickness of the first polysilicon film functioning as the floating gate, it is possible to secure a gap fill margin of the insulating film during STI formation, and to reduce the step difference between the cell array region and the peripheral circuit region. Productivity can also be improved by smoothing subsequent process runs.

 As described above, in the present invention, in forming the stacked gates of the flash memory device, the floating gates of the stacked gates are formed in a H-shaped concave-convex structure. As a result, the surface area of the floating gate is greatly increased, and thus the contact area with the inter-gate dielectric film (ONO film) is also increased, thereby improving the data program and erase operation characteristics of the flash memory device.

In addition, by forming the floating gate into a Higgs-shaped concave-convex structure, the surface area can be increased while lowering the deposition thickness of the conductive film serving as the floating gate, thereby securing a gap fill margin when filling the insulating film for forming the STI. Even when the conductive film is deposited for forming the gate, there is an advantage of eliminating the problem that the defects of the core shape are generated.

In addition, by lowering the deposition thickness of the conductive film serving as the floating gate, it is possible to reduce the step between the cell array region and the peripheral circuit region of the flash memory device so as to facilitate the subsequent process, thereby improving productivity.

Claims (20)

In a nonvolatile memory device that electrically programs and erases data: A tunnel oxide film formed on the active region of the semiconductor substrate; A floating gate formed on an upper portion of the tunnel oxide layer and having an uneven shape in which an upper surface area is wider than a lower surface area; A gate interlayer dielectric film formed on the floating gate according to a concave-convex shape of an upper surface of the floating gate; And And a control gate formed over the gate interlayer dielectric layer. The nonvolatile memory device of claim 1, wherein the floating gate and the control gate are formed of a polysilicon layer. The nonvolatile memory device of claim 1, wherein the floating gate has a H-shaped concave-convex structure having a central portion concave. The nonvolatile memory device of claim 1, wherein the gate interlayer dielectric layer is formed of an ONO layer. 5. The nonvolatile memory device of claim 4, wherein the ohio layer is deposited to a thickness of 150 to 200 microns. 4. The nonvolatile memory device of claim 3, wherein a horizontal distance between the film of the interlayer dielectric film and the film deposited on the concave portion of the floating gate is 50 占 퐉 or more. In a nonvolatile memory device that electrically programs and erases data: A tunnel oxide film formed on the active region of the semiconductor substrate in which an active region is defined by a shallow trench isolation film; A floating gate formed on an upper portion of the tunnel oxide layer, a lower portion of which is formed in a flat structure, and an upper portion of which is formed in an uneven shape having a wider surface area than the lower portion; A gate interlayer dielectric film formed on the uneven shape of the floating gate; And And a control gate formed over the gate interlayer dielectric layer. The nonvolatile memory device of claim 7, wherein the floating gate and the control gate are formed of a polysilicon layer. The nonvolatile memory device of claim 7, wherein the floating gate has a H-shaped concave-convex structure having a central portion concave. 8. The nonvolatile memory device of claim 7, wherein the gate interlayer dielectric layer is formed of an ONO layer. 11. The nonvolatile memory device of claim 10, wherein the ohio film is deposited to a thickness of 150 to 200 microns. 8. The nonvolatile memory device according to claim 7, wherein the horizontal distance between the film of the interlayer dielectric film and the film deposited on the concave portion of the floating gate is 50 kV or more. A method of manufacturing a nonvolatile memory device that electrically programs and erases data: Forming a tunnel oxide film on an active region of the semiconductor substrate; Forming a floating gate on the tunnel oxide layer, the floating gate having an uneven shape in which an upper surface area is larger than a lower surface area; Forming a gate interlayer dielectric film on the floating gate according to a concave-convex shape of an upper surface of the floating gate; And forming a control gate over the gate interlayer dielectric layer. 15. The method of claim 13, further comprising forming WSix or tungsten having low resistance on the control gate. 15. The method of claim 14, further comprising forming WSi and WN as barrier metal when tungsten is formed on the control gate. The method of claim 13, wherein the floating gate and the control gate are formed of a polysilicon layer. The method of claim 13, wherein the floating gate is formed of a H-shaped concave-convex structure having a central portion concave. The method of claim 13, wherein the gate interlayer dielectric layer is formed of an ONO layer. 19. The method of claim 18, wherein the ohio film is deposited to a thickness of 150 to 200 microns. 15. The method of claim 13, wherein the horizontal distance between the film and the film of the interlayer dielectric film deposited on the recessed portion of the floating gate is 50 占 퐉 or more.

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