KR100871372B1 - Method for forming gate in flash memory device - Google Patents

Abstract

The present invention discloses a gate forming method of a flash memory device. The disclosed method includes providing a silicon substrate having a cell region and a test pattern region and defining an active region in each region through a device isolation process, and sequentially forming a tunnel oxide film and a first conductive film on the substrate. Patterning the first conductive film in a line shape, forming a dielectric film on the patterned first conductive film in the substrate cell region, and hardening the second and third conductive films on the substrate resultant. Forming a mask layer in sequence, forming a hard mask layer pattern defining a control gate formation region by patterning the hard mask layer, and etching the third and second conductive layers using the hard mask layer pattern as an etch barrier. Forming a control gate in the substrate cell region, and using the selectivity of the exposed dielectric layer in the cell region with the first conductive layer. Comprises the steps of forming the first gate low voltage transistor of the first conductive film is etched under conditions with a high selectivity to the oxide film to form a floating gate and a test pattern area in the cell region to etch. According to the present invention, the gate forming process can be simplified by changing the etching conditions to form the control gate and the floating gate in-situ, so that the variation of the gate CD and profile and the use of multiple equipments Defects due to and the like can be prevented.

Description

Method for forming gate in flash memory device

1A through 1D are cross-sectional views illustrating processes for forming a gate of a flash memory device according to the related art.

2A through 2C are cross-sectional views illustrating processes of forming a gate of a flash memory device according to an exemplary embodiment of the present invention.
3 is a plan view illustrating a state in which a first conductive film for a floating gate is patterned in the form of a line, corresponding to FIG. 2A.

Explanation of symbols on the main parts of the drawings

21 silicon substrate 22 tunnel oxide film

23: first conductive film 23a: floating gate

24 dielectric film 25 second conductive film

26: third conductive film 27: nitride film

27a: hard mask film pattern 28: photosensitive film pattern

30: control gate 30a: gate of the low voltage transistor

The present invention relates to a method of manufacturing a flash memory device, and more particularly, to a method of forming a control gate and a floating gate in-situ by changing the etching conditions.

Flash memory devices are manufactured using the advantages of EPROM with programming and erasing characteristics and EEPROM with programming and erasing characteristics. . Such a flash memory device realizes a bit storage state as one transistor, and can be electrically programmed and erased.

Unlike DRAM devices, which store data only when power is supplied, such a flash memory device has a property of preserving data even when the power is cut off. A floating gate is formed. Accordingly, the flash memory device is floated by two gate forming processes during its manufacture, that is, a control gate forming process and a Self Align Etch (SAE) process by an etching process using the photoresist as an etch barrier. Gate forming process

1A to 1D are cross-sectional views illustrating processes for forming a gate of a flash memory device according to the prior art, which will be described below.

Referring to FIG. 1A, a tunnel oxide film 2 and a floating gate first conductive film 3 are sequentially formed on a silicon substrate 1 in which active regions in a cell region and a test pattern region are defined through an isolation process. Then, the first conductive film 3 is patterned in a line form. Then, after depositing the dielectric film 4 only on the cell region of the silicon substrate 1 including the patterned first conductive film 3, the second conductive film 5 and the control gate for the control gate on the resultant The three conductive films 6 and the nitride film 7 for hard mask are formed in order. Here, the first and second conductive films 3 and 5 are preferably polysilicon films, and the third conductive film 6 is a tungsten silicide film WSix.

Subsequently, a first photosensitive film pattern 8 defining a control gate formation region is formed on the nitride film 7.

Referring to FIG. 1B, after the nitride film is etched using the first photoresist pattern as an etch barrier, the dielectric film in the cell region is formed using the etched nitride film 7a as an etch barrier while the first photoresist pattern is removed. 4) and the tunnel oxide film 2 in the test pattern region are sequentially etched under the third and second conductive films 6 and 5 by using the etch stop layer, thereby through the active region of the substrate cell region. A control transistor 10 is formed on the line in the form of a line, and at the same time, a driving transistor comprising a stack of first, second, and third conductive films 3, 5, and 6 on the active region of the substrate test pattern region, that is, The gate 10a of the low voltage transistor is formed.

Referring to FIG. 1C, a second photoresist pattern covering a region other than the cell region on the substrate 1 in order to prevent a substrate attack on the region other than the cell region in a subsequent Self Align Etch (SAE) process. 11) form.

Referring to FIG. 1D, the exposed dielectric film 4 and the first conductive film portion below the substrate cell region are etched through a SAE process, thereby forming a floating gate 3a in the substrate cell region. . Thereafter, the second photoresist layer pattern is removed.

However, in the gate forming method of the conventional flash memory device as described above, as a plurality of processes proceed with respect to performing the control gate forming process and the floating gate forming process in a dual manner, first, the threshold dimension of the gate line ( Critical Dimension: Hereafter, CD) fluctuations occur, secondly, gate profile fluctuations occur, and thirdly, defects are generated by the use of multiple devices.

Here, the FICD (Final Inspection CD) variation of the gate causes a problem of coupling coupling (coupling ratio) and threshold voltage (Vt) and resistance (Rs) variation of the flash memory device. The parameter affecting the CD change of the line is increased, which may be a problem in the CD control of the gate line.

The variation of the gate profile is the result of two dry etchings, causing the gate profile to slope, thereby causing sidewall damage of the third conductive film, ie, tungsten silicide, which is substantially difficult to control.

Defects generated due to the use of a plurality of devices are related to securing mass production margin of the flash memory device and improving the yield of the device. That is, defects due to the use of a large number of equipments can not only be improved through process management and equipment management, or through improvement of etching conditions, but the current situation is hardly improved.

Accordingly, the present invention has been made to solve the above problems, and a flash memory capable of preventing defects caused by variations in gate CDs and gate profile variations and the use of a plurality of devices according to a plurality of process applications. It is an object to provide a method of forming a gate of the device.

In order to achieve the above object, the present invention provides a silicon substrate having a cell region and a test pattern region, the active region in each region is defined through a device isolation process; Sequentially forming a tunnel oxide film and a first conductive film on the silicon substrate; Patterning the first conductive film in a line form; Forming a dielectric film on the patterned first conductive film in the cell region; Sequentially forming a second and a third conductive layer and a hard mask layer on the substrate product on which the dielectric layer is formed; Patterning the hard mask layer to form a hard mask layer pattern defining a control gate formation region; Forming a control gate in the cell region by continuously etching the third and second conductive layers using the hard mask layer pattern as an etch barrier; Etching the exposed dielectric film of the cell region using an etch selectivity with respect to the first conductive film; And forming a floating gate in the cell region by etching the first conductive layer under a condition having a high etching selectivity with respect to an oxide layer, and at the same time, a low voltage formed by stacking the first, second, and third conductive layers in the test pattern region. Forming a gate of the transistor; provides a method of forming a gate of a flash memory device comprising a.

Here, preferably, the first and second conductive films are doped or undoped polysilicon films, the third conductive films are tungsten silicide films, and the hard mask films are nitride films.                     

In the method of the present invention, etching of the third and second conductive films, the dielectric film, and the first conductive film is performed under an in-situ etching condition in a single etching chamber, and the third conductive film is etched. Before the step, the natural oxide film generated on the surface of the third conductive film is removed.

The third conductive layer is etched using an end point detection condition, and is performed using any one of a mixed gas of Cl 2 / O 2, Cl 2 / SF 6 / O 2, or Cl 2 / HBr / O 2.

The etching of the second conductive film is performed under the condition that the time point at which the dielectric film of the cell region is exposed and the time point at which the first conductive film of the test pattern region is left by a predetermined thickness are used as the etching end point, and the first pattern of the test pattern region is The residual thickness of one conductive film is 300 kPa or more, and in particular, the flow amount of O2 gas is 2 sccm or less or He gas is added while HBr / O2 gas is used to secure the etching selectivity with the oxide film.

The dielectric film is etched under conditions such that the remaining thickness of the first conductive film in the test pattern region is 100 kPa or more, and is performed using at least one gas selected from C2H6, HBr, O2, CF4, or SF6. do.

The etching of the first conductive film is performed under the condition that the etching selectivity of the polysilicon film to the oxide film is 100: 1 or more, and the flow amount of O2 gas is changed while using HBr / O2 gas to secure the etching selectivity with the oxide film. It is carried out to 2 sccm or less or by adding He gas.                     

According to the present invention, the etching conditions can be changed to form the control gate and the floating gate in-situ, thereby simplifying the gate forming process, thereby preventing defects caused by gate CD and profile variations and the use of multiple equipment. Can be.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2C are cross-sectional views illustrating a method of forming a gate of a flash memory device according to an exemplary embodiment of the present invention, and FIG. 3 is a state in which a first conductive film for floating gates is patterned in a line shape corresponding to FIG. 2A. It is a top view showing the.

2A and 3, an active region in each of the cell region and the test pattern region is defined through an isolation process in a state in which a silicon substrate 21 having a cell region and a test pattern region is provided. Then, the tunnel oxide film 22 of the thin film and the first conductive film 23 for the floating gate are sequentially formed on the entire region of the silicon substrate 21. The first conductive layer 23 is formed of a doped polysilicon layer or an undoped polysilicon layer.
Subsequently, the first conductive film 23 is patterned in a line form according to a known process (see FIG. 3).

Next, the dielectric film 24 is selectively formed only on the cell region, including the patterned first conductive layer 23 portion of the cell region. Here, the selective formation of the dielectric film 24 on the cell region is performed after the dielectric film 24 is formed on the entire surface of the silicon substrate 21 including the first conductive film 23 patterned in the form of the line. , By removing the portion of the dielectric film 24 formed on the test pattern region.
Next, second and third conductive films 25 and 26 for the control gate and the nitride film 27 for the hard mask are sequentially formed on the resultant of the substrate on which the dielectric film 24 is selectively formed only on the cell region. Here, preferably, the second conductive film 25 is a doped or undoped polysilicon film, and the third conductive film 26 is a tungsten silicide film WSix. A photosensitive film pattern 28 defining a control gate formation region is formed on the hard mask nitride film 27.

Referring to FIG. 2B, the nitride film is etched using the photoresist pattern as an etch barrier, and then the photoresist pattern is removed. Here, the photoresist pattern may be left without being removed and used as an etching barrier in a subsequent etching process. Reference numeral 27a denotes an etched nitride film, that is, a hard mask film pattern 27a defining a control gate formation region.

Referring to FIG. 2C, the third and second conductive layers 26 and 25 are sequentially etched using the etched nitride layer, that is, the hard mask layer pattern 27a as an etching barrier, and subsequently, the third and second layers. The conductive layers 26 and 25 are etched to etch the exposed dielectric layer 24, and then the first conductive layer 23 is etched to float with the control gate 30a on the cell region of the silicon substrate 21. A driving transistor, i.e., a low voltage transistor, formed of a stack of first, second, and third conductive films 23, 25, and 26 on the test pattern region of the silicon substrate 21 at the same time as forming the gate 23a. Gate 30a is formed.

Here, the floating gate 23a and the control gate 30 on the cell region and the gate 30a of the low voltage transistor on the test pattern region are in-situ in a single etching chamber by changing the etching process. -situ), specifically the following:

First, although not described above, before the third conductive layer 26 is etched, the natural oxide film formed on the surface of the third conductive layer 26 is etched under conditions having a high etching selectivity with respect to the third conductive layer 26, that is, the polysilicon layer. Remove

Next, the third conductive layer 26 and the second conductive layer 25 are etched using the hard mask layer pattern 27a as an etch barrier to form the second and third conductive layers in the cell region of the silicon substrate 21. A control gate 30 made of a stack of (25, 26) is formed.

Here, the etching of the third conductive layer 26 is a time point at which the third conductive layer 26 is completely removed using a mixed gas of Cl 2 / O 2, Cl 2 / SF 6 / O 2, or Cl 2 / HBr / O 2. Is performed as an end point detection condition using the etch endpoint. In addition, when etching the third conductive layer 26, HBr / O 2 gas is used to improve the loading effect in order to improve the loss of the first conductive layer 23 in the test pattern region.

The etching of the second conductive film 25 is a condition under which a predetermined percentage (%) of transient etching is performed to detect the end point, for example, when the dielectric film 24 is exposed in the cell region and the first conductive pattern in the test pattern. The time point at which the predetermined thickness of the film 23 is left is performed under the condition that the etching end point is used. That is, when the first conductive film 23 in the test pattern region is completely etched, the low voltage in the test pattern region in the subsequent process of etching the dielectric film 24 and the first conductive film 23 in the cell region. The gate oxide film and the substrate 21 of the transistor 30a may be damaged and may not operate normally. Therefore, the etching of the second conductive film 25 should allow the first conductive film 23 in the test pattern region to remain by a predetermined thickness, and therefore, the etching of the second conductive film 25 is an etching choice with the oxide film. In order to secure the ratio, the flow rate of the O2 gas is reduced to 2 sccm or less while using HBr / O2 gas or by adding He gas, and in particular, the condition that the residual thickness of the first conductive film 23 is 300 kPa or more. To do it.

Subsequently, the third and second conductive films 26 and 25 are etched and exposed under conditions having a higher etching selectivity with respect to the first conductive film 23, that is, the polysilicon film, than the normal process conditions for removing the native oxide film. The dielectric film 24 is etched away. Here, the etching of the dielectric film 24 is performed under the condition that the remaining thickness of the first conductive film in the test pattern region is 100 kV or more while using at least one gas selected from C2H6, HBr, O2, CF4, or SF6. do.

In this case, the uniformity of the dielectric film 24 is very important, and the uniformity of the dielectric film 24 is controlled by adjusting the thickness of the first conductive film 23 remaining in the test pattern region to 300 μm or more. You can get the last name.

That is, generally, the F-based gas is used to remove the natural oxide film. In this case, the etching selectivity ratio between the oxide film and the polysilicon is 1.5: 1 to 2.5: 1, and the etching rate of the polysilicon film is lower than that of the oxide film. In addition, the thickness of the dielectric film used in the flash memory device is generally about 100 to 200 microns, including the ONO and ONON structures. To remove this from dry etching, it is necessary to completely remove it by performing 200% transient etching in consideration of the etching loading effect. Can be.

Therefore, in consideration of the 200% transient etching on the dielectric film 24, since the polysilicon film is etched at 100 kPa or more during the 100% transient etching, the loss of the polysilicon of 200 kPa or more in consideration of the uniformity of 5% or more. In the etching of the third and second conductive layers 26 and 25 and the etching of the dielectric layer 24, it is very important to control the remaining thickness of the first conductive layer 23 on the test pattern region. Do.

Next, the etching of the first conductive film 23 is the thickness of the first conductive film remaining in the test pattern area, for example, as the etching target of the formation thickness of the first conductive film 23 in the cell area. For example, it is carried out under the condition that the etching target is about 100 ms. In other words, the etching of the first conductive layer 23 is performed under the condition that the etching selectivity of the first conductive layer, that is, the polysilicon to the oxide layer is 100: 1 or more to minimize damage to the tunnel oxide layer and the substrate in the test pattern region. Perform. In this case, the selection ratio of 100: 1 or more can be secured by using a HBr / O2 gas in a RIE & MERIE type polysilicon etching equipment to reduce the flow amount of the O2 gas to 2 sccm or by adding a He gas. The first conductive film 23 can be etched without changing the gate profile due to the effect, and damage to the tunnel oxide film 22 in the test pattern region can also be prevented.

As described above, the gate forming method of the present invention removes the dielectric film by adding a natural oxide film removal process to an existing control gate etching condition, and in this process, adjusts the remaining thickness of the first conductive film in the test pattern region to control the substrate. In addition, the third and second conductive films, the dielectric film, and the first and the first process films are etched to prevent damage from occurring, and also to etch the first conductive film in a condition where the etching selectivity of the polysilicon to the oxide film is high in a subsequent transient etching process. The etching of the conductive film is performed in-situ.

Therefore, the method of the present invention continuously performs a SAE process for separating and forming a floating gate between the control gate and the control gate in a single chamber, thereby simplifying the entire gate forming process and reducing the number of equipment used. Thus, it is possible to overcome conventional problems such as gate CD fluctuations due to multiple process applications, gate profile fluctuations and defect occurrences due to the use of multiple equipment.

As described above, the present invention can achieve the process simplification because the processes for forming the control gate and the floating gate are successively performed in a single device with a new in-situ etching condition, and the number of equipment used can be reduced. have. Therefore, the present invention can prevent gate CD variation and gate profile variation through process simplification, and also prevent defects caused by equipment use, and thus improve productivity through shortening of the entire process and time. Can be.

In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.

Claims (13)

Providing a silicon substrate having a cell region and a test pattern region, the active region being defined in each region through a device isolation process; Sequentially forming a tunnel oxide film and a first conductive film on the silicon substrate; Patterning the first conductive film in a line form; Forming a dielectric film on the patterned first conductive film in the cell region; Sequentially forming a second and a third conductive layer and a hard mask layer on the substrate product on which the dielectric layer is formed; Patterning the hard mask layer to form a hard mask layer pattern defining a control gate formation region; Forming a control gate in the cell region by continuously etching the third and second conductive layers using the hard mask layer pattern as an etch barrier; Etching the exposed dielectric film of the cell region using an etch selectivity with respect to the first conductive film; And A low voltage transistor formed by etching the first conductive layer under a condition having a high etching selectivity with respect to an oxide layer to form a floating gate in the cell region and stacking the first, second and third conductive layers in the test pattern region Forming a gate of the; Gate forming method of a flash memory device comprising a. 2. The flash memory of claim 1, wherein the first and second conductive layers are doped or undoped polysilicon layers, the third conductive layer is a tungsten silicide layer (WSix), and the hard mask layer is a nitride layer. Method for forming gate of device. The flash memory device of claim 1, wherein the etching of the third and second conductive layers, the dielectric layer, and the first conductive layer is performed in an in-situ etching condition in a single etching chamber. Gate forming method. The gate forming method of claim 1, further comprising removing a native oxide film formed on a surface of the third conductive film before the etching of the third conductive film. The method of claim 1, wherein the etching of the third conductive film is A method of forming a gate of a flash memory device, characterized in that performed under an end point detection condition. The method of claim 1 or 5, wherein the etching of the third conductive film is performed using any one of a mixed gas selected from the group consisting of Cl2 / O2, Cl2 / SF6 / O2 and Cl2 / HBr / O2. A method of forming a gate of a flash memory device. The method of claim 1, wherein the etching of the second conductive film is And a time point at which the dielectric film in the cell region is exposed and a time point in which the first conductive film in the test pattern region is left with a predetermined thickness as a etch end point. The method of claim 7, wherein the etching of the second conductive film is And forming a residual thickness of the first conductive layer in the test pattern region to be 300 Å or more. The method of claim 1 or 7, wherein the etching of the second conductive film is A method of forming a gate of a flash memory device, characterized in that the flow amount of O2 gas is set to 2 sccm or less or He gas is added while using an HBr / O2 gas to secure an etching selectivity with an oxide film. The method of claim 1, wherein the etching of the dielectric film And forming a residual thickness of the first conductive layer in the test pattern region in a range of about 100 GPa or more. The method of claim 1 or 10, wherein the etching of the dielectric film And at least one gas selected from the group consisting of C2H6, HBr, O2, CF4 and SF6. The method of claim 1, wherein the etching of the first conductive film is A method of forming a gate of a flash memory device, characterized in that the etching selectivity of the polysilicon film to the oxide film is 100: 1 or more. The method of claim 1 or 12, wherein the etching of the first conductive film is A method of forming a gate of a flash memory device, characterized in that the flow amount of O2 gas is set to 2 sccm or less or He gas is added while using an HBr / O2 gas to secure an etching selectivity with an oxide film.

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