KR100602077B1 - Semiconductor device and fabricating method thereof - Google Patents

Abstract

 A semiconductor device according to an embodiment of the present invention includes a substrate having a source region, a drain region, and a channel region, an ONO layer formed on the channel region, a first polycrystalline silicon layer formed on the ONO layer, and sidewalls of the first polycrystalline silicon layer. An ONO layer and a first polycrystalline silicon, including an oxide wall formed on the first polycrystalline silicon layer, an insulating layer formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer formed on the insulating layer and insulated from the first polycrystalline silicon layer. The layer and the insulating layer have substantially the same planar pattern.

SONOS, Split gate, step

Description

Semiconductor device and fabrication method thereof

1 is a cross-sectional view illustrating a semiconductor device in accordance with an embodiment of the present invention.

2A to 2G are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

※ Code explanation about main part of drawing ※

10 semiconductor substrate 12 device isolation region

14, 18: oxide layer 16, 20, 26: gate

22: insulating layer 24: oxide wall

28 gate oxide film 30 source and drain regions

32: interlayer insulation film 41-44: via

51 ~ 54: metal wiring layer

The present invention relates to a semiconductor device and a manufacturing method thereof.

Flash memory is a non-volatile semiconductor memory that can be electrically programmed and erased. Flash memory can be mass erased electrically, and memory and logic products can be combined on a single chip, which is widely used in places such as portable computers and digital cameras.

One of the methods of forming a flash memory is composed of three gates, a floating gate made of polycrystalline silicon, a control gate, and a erase gate. The gates are insulated by an insulating film, respectively, and have a high voltage and a low voltage by a gate oxide film having a different thickness. It is mainly used in the form of a split gate driven differently.

The floating gate is written by charging a certain amount of carriers by a voltage applied to the control gate, where a high charging capacity is required to obtain the high gate voltage of the floating gate from the control gate. As a method of obtaining a high charge capacity, there is a method of increasing the overlap area of the floating gate and the control gate or reducing the thickness of the insulating layer.

In the latter case, the charging capacity can be increased, but the leakage current increases, and thus the high charging capacity is obtained mainly using the former method.

However, in the former method, as the overlap area increases, the area of the cell increases, and a high level difference occurs due to the thickness of the gate formed of polycrystalline silicon, which causes difficulty in planarization. Difficult to do

In order to solve the above problems, it is to provide a semiconductor device and a method of manufacturing the semiconductor device having a constant charging capacity and can minimize the step difference.

In order to achieve the above object, a semiconductor device according to an embodiment of the present invention includes a substrate having a source region, a drain region and a channel region, an ONO layer formed on the channel region, a first polycrystalline silicon layer formed on the ONO layer, An oxide wall formed on the sidewall of the first polycrystalline silicon layer, an insulating layer formed on the first polycrystalline silicon layer, and a second polycrystalline silicon layer formed on the insulating layer and insulated from the first polycrystalline silicon layer, The ONO layer, the first polycrystalline silicon layer and the insulating layer have substantially the same planar pattern.

According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method including: forming a device isolation region defining an active region in a semiconductor substrate, wherein the first oxide film, the first nitride film, the second oxide film, and the first oxide film are formed on the semiconductor substrate. 1) sequentially stacking a polycrystalline silicon film and a second nitride film; etching the second nitride film and the second polycrystalline silicon film by a photolithography process to form an insulating layer and a first polycrystalline silicon layer; oxidizing the substrate to oxidize the first polycrystal Forming an oxide layer on the sidewall of the silicon layer, etching the second oxide film, the first nitride film, and the first oxide film using the first polycrystalline silicon layer as a mask to form an ONO layer, and oxidizing the substrate to form a gate oxide film Forming a second polycrystalline silicon layer by forming a polycrystalline silicon film on the substrate and then patterning the second polycrystalline silicon layer; Forming a lane region.

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The oxide wall is preferably formed to a thickness of 50 ~ 300 ~.

The first oxide film is preferably formed to a thickness of 15 to 30 GPa and the gate oxide film is formed to a thickness of 20 to 200 GPa.

Moreover, it is preferable to form a 1st nitride film with a thickness of 60-200 GPa and a 2nd nitride film with 500-1,500 GPa.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is over another part, this includes not only the part directly above the other part but also another part in the middle. On the contrary, when a part is just above another part, it means that there is no other part in the middle.

It will now be described in detail with reference to the drawings with reference to embodiments of the present invention.

1 is a cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 1, an active region in which semiconductor elements and the like are disposed in the semiconductor substrate 10 is defined, and an element isolation region 12 for insulation is formed between the semiconductor elements.

Then, the ONO layers 14, 16 and 18, in which the nitride layer 16 is formed between the oxide layers 14 and 18, are formed above the predetermined region of the active region. The oxide layer 14 of the ONO layer formed directly on the semiconductor substrate 10 is used as a tunnel oxide film in which tunneling occurs when a constant voltage is applied to the first and second polysilicon layers described later.

The first polycrystalline silicon layer 20 is formed on the ONO layers 14, 16, and 18, and the insulating layer 22 is formed on the first polycrystalline silicon layer 20. In addition, the second polycrystalline silicon layer 26 is formed on the entire sidewall of the ONO layer and the first polycrystalline silicon layer 20 on the insulating layer 22. The first polycrystalline silicon layer 20 and the second polycrystalline silicon layer 26 are insulated by the oxide wall 24 formed on the sidewall of the first polycrystalline silicon layer 20.

The first and second polycrystalline silicon layers 20 and 26 are formed of polycrystalline silicon doped with impurities, and the insulating layer 22 is formed of nitride. The ONO layers 14, 16, 18, the first polycrystalline silicon layer 20, and the insulating layer 22 have the same planar pattern. A gate oxide film 28 is formed directly on the exposed active region. The gate oxide film 28 is formed to extend under the second polycrystalline silicon layer 26, and a channel is formed in the semiconductor substrate 10 under the gate oxide film 28 when a voltage is applied to the second polycrystalline silicon layer 26. Is formed.

In a predetermined region of the active region, a source region and a drain region 30 doped with n-type or p-type conductive impurity ions at high concentration are formed. The active regions corresponding to the ONO layers 14, 16, 18 and the second polysilicon layer 26 are regions that are not doped with impurity ions, and separate the source region and the drain region 30.

An interlayer insulating layer 32 is formed on the entire surface of the substrate including the source region and the drain region 30, and the interlayer insulating layer 32 includes the source and drain regions 30, and the first and second polycrystalline silicon layers 20 and 26. ) And plugs 41 to 44 contacting through via holes VH1 to VH4, respectively. The plugs 41 to 44 are connected to the metal wiring layers 51 to 54 formed on the interlayer insulating layer 32 to supply external signals to the source and drain regions 30 and the first and second polycrystalline silicon layers 20 and 26. ). The metal wiring layer 34 may further include a metal wiring layer including a plug contacting the lower wiring layer through the interlayer insulating layer and the via hole, if necessary.

Thus, the operation of the semiconductor device according to the embodiment of the present invention is as follows.

First, write applies a constant voltage to the drain, for example 5V, and grounds the source. When a constant voltage (for example, + 10V) is applied to the first polycrystalline silicon layer 20, and a slight voltage, for example, 1V is applied to the second polycrystalline silicon layer 26, a carrier is generated. By tunneling, charges are trapped in the nitride layer 16 of the ONO layer, thereby increasing the threshold voltage. This state is recognized as a write state.

The erase is performed by applying a constant voltage (minus), for example, -10V, to the first polycrystalline silicon layer 20, thereby causing charges trapped in the ONO layer to escape to the semiconductor substrate 10, thereby lowering the threshold voltage. This state is recognized as a clear state.

At this time, when the charge of the nitride layer 20 is overdischarged and the threshold voltage of the nitride layer 20 shows a negative value, even when no write voltage is applied to the second polysilicon layer 26, the current is maintained. Over-erase may occur. However, leakage current due to over-discharged charges is prevented by the second polycrystalline silicon layer 26. At this time, no voltage is applied to the second polycrystalline silicon layer 26.

A method of manufacturing a semiconductor device according to an embodiment of the present invention described above will be described in detail with reference to the accompanying drawings.

2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

As shown in FIG. 2A, the device isolation region 12 defining the active region is formed on the semiconductor substrate 10 by using a local oxidation silicon (LOCOS) or shallow trench isolation (STI) scheme. The LOCOS method is a method of forming a device isolation region 12 by oxidizing a predetermined region of the substrate 10, and the STI method is a method of forming a device isolation region 12 by filling a insulating material after forming a trench in the substrate. .

Thereafter, the first oxide film 14A, the first nitride film 16A, the second oxide film 18A, the first polycrystalline silicon film 20A, and the second nitride film 22A are sequentially stacked to cover the active region.

The first oxide film 14A is formed by oxidizing the substrate 10 to a thickness of 15 to 30 μm, and the second oxide film 18A is formed by depositing a method such as CVD (chemical vapor deposition). do. The first nitride film 16A is deposited by a CVD method to form a thickness of 60 to 200 GPa, and the second nitride film 22A is deposited by a CVD method to form a thickness of 500 to 1,500 GPa. In addition, the first polycrystalline silicon film 20A is formed by depositing the doped polycrystalline silicon by a method such as CVD to a thickness of 1,000 to 3,000 kPa.

Next, as shown in FIG. 2B, after the photoresist pattern is formed on the second nitride film 22A using a photomask, the second nitride film 22A and the first polycrystalline silicon film 20A are formed using the photoresist pattern as an etching mask. ) Is etched through a dry etching method using plasma to form the insulating layer 22 and the first polycrystalline silicon layer 20.

After removing the photoresist pattern, the substrate 10 is oxidized to form an oxide wall 24 on the sidewall of the first polysilicon layer 20. At this time, since the substrate 10 is covered with the first oxide film 14A, the first nitride film 16A, and the second oxide film 18A, the substrate 10 is protected without being oxidized.

The oxide wall 24 is formed to have a thickness of 50 to 300 kV in order to prevent the high voltage from being applied to the first polycrystalline silicon layer 20 to be destroyed.

As shown in FIG. 2C, after the photoresist layer pattern is removed, the second oxide layer 18A, the first nitride layer 16A, and the first oxide layer 14A are sequentially wet-etched using the insulating layer 22 as a mask to form the oxide layer 14. , 18 to form ONO layers 14, 16, and 18 on which nitride layer 16 is formed. At this time, the wet etchant uses HF, H ₃ PO ₄ and the like.

As shown in FIG. 2D, the substrate 10 is oxidized to form a gate oxide film 28. The gate oxide film 28 is formed in a range of 20 to 200 kHz so as not to be destroyed by voltages applied to the source, drain region 30, second polysilicon layer 26, and the like.

Thereafter, an undoped polycrystalline silicon film is formed on the entire surface of the substrate 10 to a thickness of 1,000 to 3,000 Å, and then doped with P-type impurity ions phosphorus (P), boron (B), and the like at a concentration of 5E15. Thereafter, dry etching is performed by a photolithography process to form a second polycrystalline silicon layer 26.

As shown in FIG. 2E, the source and drain regions 30 are formed by doping phosphorus (P), boron (B), and the like which are P-type impurity ions in the active region. Thereafter, the interlayer insulating layer 32 is formed of an insulating material such as PE-TEOS, FSG, USG, and the like, and the via holes VH1 exposing the source and drain regions 30 and the first and second polycrystalline silicon layers 20 and 26, respectively. To form ~ VH4).

A process of forming a lightly doped region (not shown) may be added before forming the source region and the drain region 30. In order to form a lightly doped region, first, dopant ions are lightly doped in the active region of the substrate. A spacer having a predetermined thickness is then formed on the sidewalls of the ONO layer and the first and second polycrystalline silicon layers. Thereafter, an impurity doping process for forming source and drain regions is performed in the active region. At this time, the lightly doped region is formed only in the active region protected by the spacer.

Then, as shown in FIG. 1, after forming the metal film to fill the via hole VH, the metal film is polished by a method such as chemical mechanical polishing (CMP), and the source and drain regions through the via holes VH1 to VH4, respectively. 30), plugs 41 to 44 in contact with the first and second polycrystalline silicon layers 20 and 26 are formed. After forming a metal film in contact with the upper portion of the plug (41 ~ 44), the metal film is patterned by a photolithography process to be connected to the plug (41 ~ 44) metal wiring layer for inputting an external signal to the source and drain regions 30 ( 51-54). If necessary, a process of forming a metal wiring layer having a plug in contact with the lower metal wiring layer through the interlayer insulating film and the via may be further performed several times.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, when the semiconductor device as in the present invention is formed by using charge trapped in the nitride layer when a constant voltage is applied, the step difference of the semiconductor device can be formed lower than when using polycrystalline silicon. . Therefore, it is easy when forming logic processes.

In addition, since the ONO layer in which charge is trapped is formed in the same pattern as the first polycrystalline silicon layer, the photolithography process for forming a floating gate is omitted in the related art, thereby simplifying the process and reducing the cost.

Claims (6)

A substrate having a source region, a drain region and a channel region, An ONO layer formed on the channel region, A first polycrystalline silicon layer formed on the ONO layer, An oxide wall formed on the sidewall of the first polycrystalline silicon layer, An insulating layer formed on said first polycrystalline silicon layer, and A second polycrystalline silicon layer formed on the insulating layer and insulated from the first polycrystalline silicon layer, And the ONO layer, the first polycrystalline silicon layer, and the insulating layer have substantially the same planar pattern. delete Forming a device isolation region defining an active region in the semiconductor substrate, Sequentially stacking a first oxide film, a first nitride film, a second oxide film, a first polycrystalline silicon film, and a second nitride film on the semiconductor substrate; Etching the second nitride film and the second polycrystalline silicon film by a photolithography process to form an insulating layer and a first polycrystalline silicon layer, Oxidizing the substrate to form an oxide wall on the sidewall of the first polycrystalline silicon layer, Etching the second oxide film, the first nitride film, and the first oxide film using the first polycrystalline silicon layer as a mask to form an ONO layer; Oxidizing the substrate to form a gate oxide film; Forming a second polycrystalline silicon layer by forming and then patterning a polycrystalline silicon film on the substrate; And forming a source and a drain region by doping conductive impurity ions in a predetermined region of the substrate. In claim 3, The oxide wall is a semiconductor device manufacturing method to form a thickness of 50 ~ 300 ~. In claim 3, The first oxide film is formed to a thickness of 15 ~ 30Å, The gate oxide film is a manufacturing method of a semiconductor device to form a thickness of 20 ~ 200Å. In claim 3, The first nitride film is formed to a thickness of 60 ~ 200Å, the second nitride film is a manufacturing method of the semiconductor element to form a thickness of 500 ~ 1,500Å.

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