CN107994021B - Flash memory and manufacturing method thereof - Google Patents
Flash memory and manufacturing method thereof Download PDFInfo
- Publication number
- CN107994021B CN107994021B CN201610936627.7A CN201610936627A CN107994021B CN 107994021 B CN107994021 B CN 107994021B CN 201610936627 A CN201610936627 A CN 201610936627A CN 107994021 B CN107994021 B CN 107994021B
- Authority
- CN
- China
- Prior art keywords
- region
- electrode lead
- layer
- area
- initial
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims abstract description 54
- 239000003990 capacitor Substances 0.000 claims abstract description 52
- 238000005530 etching Methods 0.000 claims abstract description 47
- 230000002093 peripheral effect Effects 0.000 claims abstract description 44
- 230000005641 tunneling Effects 0.000 claims abstract description 28
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 238000000605 extraction Methods 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 235000012239 silicon dioxide Nutrition 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 239000010937 tungsten Substances 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 159
- 239000000463 material Substances 0.000 description 17
- 238000003860 storage Methods 0.000 description 11
- 238000010586 diagram Methods 0.000 description 9
- 239000000126 substance Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000011241 protective layer Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The invention discloses a flash memory and a manufacturing method thereof, wherein the method comprises the following steps: sequentially and simultaneously etching the insulating layer, the floating gate layer and the tunneling oxide layer in the capacitor area and the peripheral area to form an initial source electrode lead-out area and an initial drain electrode lead-out area in the capacitor area; forming a control gate layer on the initial source electrode lead-out region, the initial drain electrode lead-out region and the insulating layer; and etching the control gate layer in the initial source electrode lead-out region, the initial drain electrode lead-out region and the peripheral region simultaneously to form a final source electrode lead-out region and a final drain electrode lead-out region in the capacitor region. According to the invention, the insulating layer, the floating gate layer and the tunneling oxide layer in the capacitor region and the peripheral region are sequentially and simultaneously etched, and then the initial source electrode lead-out region, the initial drain electrode lead-out region and the control gate layer in the peripheral region are simultaneously etched, so that the final source electrode lead-out region and the final drain electrode lead-out region are formed in the capacitor region, and the damage to the active layer is reduced when the source electrode lead-out region and the drain electrode lead-out region are formed.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a flash memory and a manufacturing method thereof.
Background
Flash Memory (Flash Memory) is a long-life nonvolatile (capable of maintaining stored data information in case of power failure) Memory, and generally includes a storage region, a peripheral region, and a capacitor region, and the size and the density of the storage region are much larger than those of the capacitor region.
In the existing flash memory manufacturing process, a source electrode and a drain electrode lead-out region of a capacitor region are etched while a bit line in a storage region is formed by using a control gate etching process, namely the capacitor region and the storage region are etched simultaneously in the control gate etching process. However, as known from the loading effect (loading effect) in the etching process, since the size of the storage region and the density of the storage unit are much larger than the size and the density of the capacitor region, the degree of etching substances consumed in the storage region is relatively serious, which results in that the concentration of the reactive substance in a unit etching area becomes low, while the etching rate is in direct proportion to the concentration of the reactive substance, and under the condition of etching the same material and the same depth, the storage region needs to be etched for a longer time. Because the storage region and the capacitor region are etched simultaneously, after the storage region is etched, the source electrode lead-out region and the drain electrode lead-out region of the capacitor region are over-etched, so that the active layer is damaged. Fig. 1 is a schematic structural diagram of a capacitor region after source and drain lead-out regions are formed in the prior art, and referring to fig. 1, an active layer 11, a tunneling oxide layer 12, a floating gate layer 13, an insulating layer 14 and a control gate layer 15 are sequentially arranged from bottom to top. As can be seen from the figure, after the source lead-out region 16 and the drain lead-out region 17 are formed, the active layer 11 is also etched away partially.
In the prior art, when the source lead-out region 16 and the drain lead-out region 17 are etched in the capacitor region, the capacitor region and the storage region are etched at the same time, so that the source lead-out region 16 and the drain lead-out region 17 are over-etched, and the active layer 11 is damaged.
Disclosure of Invention
The invention provides a flash memory and a manufacturing method thereof, which are used for reducing the damage to an active layer when a source electrode lead-out region and a drain electrode lead-out region are formed.
In a first aspect, the present invention provides a method for manufacturing a flash memory, including:
sequentially and simultaneously etching the insulating layer, the floating gate layer and the tunneling oxide layer in the capacitor area and the peripheral area to form an initial source electrode lead-out area and an initial drain electrode lead-out area in the capacitor area;
forming a control gate layer on the initial source electrode lead-out region, the initial drain electrode lead-out region and the insulating layer;
and simultaneously etching the control gate layer in the initial source electrode lead-out region, the initial drain electrode lead-out region and the peripheral region to form a final source electrode lead-out region and a final drain electrode lead-out region in the capacitor region.
In the foregoing method, optionally, before the sequentially and simultaneously etching the insulating layer, the floating gate layer, and the tunneling oxide layer in the capacitor region and the peripheral region, the method further includes:
and sequentially forming a tunneling oxide layer, a floating gate layer and an insulating layer on the active layer.
In the above method, optionally, the tunneling oxide layer is formed by an in-situ water vapor growth process.
In the foregoing method, optionally, the tunneling oxide layer is made of silicon dioxide.
In the above method, optionally, the floating gate layer is formed by using a chemical vapor deposition process.
In the foregoing method, optionally, the sequentially and simultaneously etching the insulating layer, the floating gate layer, and the tunneling oxide layer in the capacitor region and the peripheral region includes:
and sequentially and simultaneously etching the insulating layer, the floating gate layer and the tunneling oxide layer in the capacitor area and the peripheral area by adopting a wet etching process.
In the above method, optionally, the insulating layer includes a first oxide layer, a nitride layer, and a second oxide layer sequentially formed on the floating gate layer.
In the above method, optionally, after the forming of the final source lead-out region and the final drain lead-out region, the method further includes:
and depositing metal in the final source electrode lead-out area and the final drain electrode lead-out area so as to lead out the source electrode and the drain electrode.
In the above method, optionally, the metal is tungsten.
In a second aspect, the present invention provides a flash memory, which is manufactured by any of the above flash memory manufacturing methods.
The invention provides a flash memory and a manufacturing method thereof.A primary source electrode lead-out area and a primary drain electrode lead-out area are formed in a capacitor area by sequentially and simultaneously etching an insulating layer, a floating gate layer and a tunneling oxide layer in the capacitor area and a peripheral area; forming a control gate layer on the initial source electrode lead-out region, the initial drain electrode lead-out region and the insulating layer; and then, etching the control gate layers in the initial source electrode lead-out region, the initial drain electrode lead-out region and the peripheral region simultaneously to form a final source electrode lead-out region and a final drain electrode lead-out region in the capacitance region, so that the damage to the active layer is reduced when the source electrode lead-out region and the drain electrode lead-out region are formed.
Drawings
FIG. 1 is a schematic diagram of a capacitor region after source and drain lead-out regions are formed in the prior art;
fig. 2A is a schematic flowchart illustrating a method for manufacturing a flash memory according to a first embodiment of the invention;
FIGS. 2B-2D are schematic structural diagrams corresponding to a method for manufacturing a flash memory according to a first embodiment of the present invention;
FIG. 3A is a flow chart illustrating a method for manufacturing a flash memory according to a second embodiment of the present invention;
fig. 3B is a schematic structural diagram of an active layer, a tunnel oxide layer, a floating gate layer and an insulating layer in the second embodiment of the present invention;
fig. 3C is a schematic structural diagram of etching a control gate in the second embodiment of the present invention;
fig. 3D is a schematic structural diagram of the source and drain extraction electrodes in the second embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Example one
Fig. 2A is a flowchart illustrating a method for manufacturing a flash memory according to a first embodiment of the invention. Fig. 2A only shows the steps of forming the source and drain lead-out regions of the capacitor region of the flash memory, and how to form other portions of the flash memory is referred to the prior art and is not described in detail in this embodiment. Fig. 2B-2D are schematic structural diagrams corresponding to a method for manufacturing a flash memory according to a first embodiment of the invention.
Referring to fig. 2A, the method for manufacturing a flash memory of the present embodiment specifically includes the following steps:
and step 210, sequentially and simultaneously etching the insulating layer, the floating gate layer and the tunneling oxide layer in the capacitor area and the peripheral area to form an initial source electrode lead-out area and an initial drain electrode lead-out area in the capacitor area.
Referring to fig. 2B, in the capacitor region of the flash memory, a tunnel oxide layer 22, a floating gate layer 23, and an insulating layer 24 are sequentially formed on an active layer 21. In this embodiment, a photoresist and a mask layer may be formed above the insulating layer 24, the mask layer is illuminated, the photoresist is etched to form an etching pattern, and the insulating layer 24, the floating gate layer 23, and the tunneling oxide layer 22 in the capacitor region and the peripheral region are simultaneously etched in sequence according to the etching pattern, so that the initial source lead-out region 25 and the initial drain lead-out region 26 are formed in the capacitor region. In addition, it should be noted that there is a loading effect during the etching process, specifically, when the material to be etched is exposed to a reactive substance (such as a reactive plasma (e.g., plasma) or a solution), the etching rate of the material to be etched with a larger area is slower than that of the material with a smaller area. This is because the concentration of the reactive material becomes lower due to the more severe consumption of the reactive material in the area of the material to be etched having a larger area, and the etching rate is proportional to the concentration of the reactive material, and the etching rate is correspondingly reduced when the concentration of the reactive material is reduced. In this embodiment, since the difference between the size of the flash memory peripheral region and the density of the structure to be etched and the capacitor region is not large, it can be known from the load effect in the etching process that the etching rate of the material to be etched is in direct proportion to the concentration of the reactive substance in the unit etching area, and the etching time required for etching the peripheral region and the capacitor region is substantially the same when the same material (the insulating layer 24, the floating gate layer 23 and the tunnel oxide layer 22) and the same depth are etched. Therefore, after the tunnel oxide layer 22 is etched in the peripheral region, the tunnel oxide layer 22 can be basically etched in the capacitor region, so that the initial source lead-out region 25 and the initial drain lead-out region 26 are formed while the active layer 21 is prevented from being damaged.
Referring to fig. 2C, a control gate layer 27 is formed on the insulating layer 24, the initial source lead-out region 25, and the initial drain lead-out region 26. The material of the control gate layer 27 is typically polysilicon, and the control gate layer 27 can be formed by using a chemical vapor deposition technique or other prior art, and the chemical vapor deposition technique is preferably used in this embodiment.
And step 230, etching the control gate layers in the initial source electrode lead-out region, the initial drain electrode lead-out region and the peripheral region simultaneously to form a final source electrode lead-out region and a final drain electrode lead-out region in the capacitor region.
Referring to fig. 2D, the initial source lead-out region 25, the initial drain lead-out region 26, and the control gate layer 27 on the peripheral region are simultaneously etched to form a final source lead-out region 28 and a final drain lead-out region 29. Since the size of the flash memory peripheral area and the density of the structure to be etched are not much different from those of the capacitor area, the time required for etching the control gate layer 27 of the peripheral area and the capacitor area is basically the same under the condition of etching the same material (control gate layer 27) and the same depth. Therefore, after the etching of the control gate layer 27 in the peripheral region is completed, the etching of the control gate layer 27 is also substantially completed in the capacitor region, and the final source lead-out region 28 and the final drain lead-out region 29 are formed while avoiding damage to the active layer 21.
In the manufacturing method of the flash memory provided by this embodiment, the insulating layer, the floating gate layer and the tunneling oxide layer in the capacitor region and the peripheral region are sequentially and simultaneously etched, so as to form the initial source electrode lead-out region and the initial drain electrode lead-out region in the capacitor region; forming a control gate layer on the initial source electrode lead-out region, the initial drain electrode lead-out region and the insulating layer; and then, etching the control gate layers in the initial source electrode lead-out region, the initial drain electrode lead-out region and the peripheral region simultaneously to form a final source electrode lead-out region and a final drain electrode lead-out region in the capacitance region, so that the damage to the active layer is reduced when the source electrode lead-out region and the drain electrode lead-out region are formed.
Example two
Fig. 3A is a flowchart illustrating a method for manufacturing a flash memory according to a second embodiment of the invention. On the basis of the above embodiment, before the insulating layer, the floating gate layer, and the tunneling oxide layer in the capacitor region and the peripheral region are sequentially and simultaneously etched, the present embodiment further includes sequentially forming the tunneling oxide layer, the floating gate layer, and the insulating layer on the active layer; after the forming of the final source lead-out region and the final drain lead-out region, depositing metal in the final source lead-out region and the final drain lead-out region to lead out the source and the drain.
Referring to fig. 3A, the method for manufacturing a flash memory according to the present embodiment includes:
and 310, sequentially forming a tunneling oxide layer, a floating gate layer and an insulating layer on the active layer.
Fig. 3B is a schematic structural diagram of an active layer, a tunnel oxide layer, a floating gate layer, and an insulating layer in the second embodiment of the invention. Referring to fig. 3B, a tunnel oxide layer 32, a floating gate layer 33, and an insulating layer 34 are sequentially formed on the active layer 31. In this embodiment, an in-situ water vapor generation process may be employed to form a tunneling oxide layer 32 on the revealed active layer 31; the tunnel oxide layer 32 may also be formed on the surface of the active layer 31 by using a treatment method of oxidizing the active layer 31, and in this embodiment, an in-situ water vapor generation process is preferably used, wherein the material of the tunnel oxide layer may be silicon dioxide. In the present embodiment, a chemical vapor deposition process or other conventional processes may be used to form the floating gate layer 33 and the insulating layer 34 on the surface of the tunnel oxide layer 32, wherein the material of the floating gate layer 33 is typically polysilicon. The insulating layer 34 may include a first oxide layer, a nitride layer, and a second oxide layer sequentially formed on the floating gate layer 33, wherein the first oxide layer and the second oxide layer are both made of an oxide, and they may be the same kind of oxide, such as both silicon dioxide; the material of the nitride layer may be silicon nitride. Illustratively, the insulating layer 34 may be formed by a silicon dioxide layer, a silicon nitride layer, and a silicon dioxide layer sequentially formed on the floating gate layer 33 by a chemical vapor deposition process.
And step 320, sequentially and simultaneously etching the insulating layer, the floating gate layer and the tunneling oxide layer in the capacitor area and the peripheral area to form an initial source electrode lead-out area and an initial drain electrode lead-out area in the capacitor area.
In this embodiment, a wet etching process or a dry etching process may be adopted to sequentially and simultaneously etch the insulating layer, the floating gate layer, and the tunneling oxide layer in the capacitor region and the peripheral region, and in this embodiment, the wet etching process is preferably adopted.
Fig. 3C is a schematic structural diagram of etching a control gate in the second embodiment of the present invention. Referring to fig. 3C, in this embodiment, a final source lead-out region and a final drain lead-out region may be formed in the capacitor region by forming a photoresist layer 36 and a mask layer on the control gate layer 35, then irradiating the mask layer, etching the photoresist to form a final source etched region 361 and a final drain etched region 362, and simultaneously etching the control gate layer 35 in the final source etched region 361, the final drain etched region 362, and the peripheral region. It should be noted that, only the etching region in the capacitor region is shown in the figure, and the etching region in the peripheral region is not shown, which can refer to the prior art. In this embodiment, a wet etching process or a dry etching process may be used to simultaneously etch the control gate layer in the capacitor region and the control gate layer in the peripheral region, and preferably, the wet etching process is used.
And step 350, depositing metal in the final source electrode lead-out area and the final drain electrode lead-out area so as to lead out the source electrode and the drain electrode.
Fig. 3D is a schematic structural view of the source and drain extraction electrodes in the second embodiment of the present invention, and referring to fig. 3D, a protective layer 37 and a source extraction electrode 38 are deposited in the final source extraction region; a protective layer 37 and a drain extraction electrode 39 are deposited in the final drain extraction region. The protective layer 37 is used for isolating the source extraction electrode 38 and the drain extraction electrode 39 from the tunneling oxide layer 32, the floating gate layer 33, the insulating layer 34 and the control gate layer 35 respectively; the material of the source lead-out electrode 38 and the drain lead-out electrode 39 may be a conductive metal such as gold, silver, copper, or tungsten, and tungsten is preferable in this embodiment.
In the manufacturing method of the flash memory provided by this embodiment, the tunneling oxide layer, the floating gate layer and the insulating layer are sequentially formed on the active layer, and the insulating layer, the floating gate layer and the tunneling oxide layer in the capacitor region and the peripheral region are sequentially and simultaneously etched, so that the initial source lead-out region and the initial drain lead-out region are formed in the capacitor region; then forming a control gate layer on the initial source electrode lead-out region, the initial drain electrode lead-out region and the insulating layer; and the control gate layer in the initial source electrode lead-out area, the initial drain electrode lead-out area and the peripheral area is etched at the same time, and the final source electrode lead-out area and the final drain electrode lead-out area are formed in the capacitor area, so that the damage to the active layer is reduced when the source electrode lead-out area and the drain electrode lead-out area are formed.
The embodiment of the invention also provides a flash memory, and the flash memory is manufactured by any one of the manufacturing methods of the flash memory. It should be noted that the flash memory provided by the embodiment of the present invention has the same functions and advantages as the manufacturing method thereof.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A method of manufacturing a flash memory, comprising:
simultaneously etching insulating layers in a capacitance area and a peripheral area, floating gate layers in the capacitance area and the peripheral area and tunneling oxide layers in the capacitance area and the peripheral area to form an initial source electrode lead-out area and an initial drain electrode lead-out area in the capacitance area;
forming a control gate layer on the initial source electrode lead-out region, the initial drain electrode lead-out region and the insulating layer;
and simultaneously etching the control gate layer in the initial source electrode lead-out region, the initial drain electrode lead-out region and the peripheral region to form a final source electrode lead-out region and a final drain electrode lead-out region in the capacitor region.
2. The method of claim 1, further comprising, prior to said simultaneously etching the insulating layer in the capacitive region and the peripheral region, the floating gate layer in the capacitive region and the peripheral region, and the tunnel oxide layer in the capacitive region and the peripheral region:
and sequentially forming a tunneling oxide layer, a floating gate layer and an insulating layer on the active layer.
3. The method of claim 2, wherein the tunnel oxide layer is formed using an in-situ vapor growth process.
4. The method of claim 3, wherein the tunneling oxide layer is formed of silicon dioxide.
5. The method of claim 2, wherein the floating gate layer is formed using a chemical vapor deposition process.
6. The method of claim 1, wherein the simultaneously etching the insulating layer in the capacitive region and the peripheral region, the floating gate layer in the capacitive region and the peripheral region, and the tunneling oxide layer in the capacitive region and the peripheral region comprises:
and sequentially and simultaneously etching the insulating layer, the floating gate layer and the tunneling oxide layer in the capacitor area and the peripheral area by adopting a wet etching process.
7. The method of claim 1, wherein the insulating layer comprises a first oxide layer, a nitride layer, and a second oxide layer sequentially formed on the floating gate layer.
8. The method of claim 1, further comprising, after said forming final source and drain extraction regions:
and depositing metal in the final source electrode lead-out area and the final drain electrode lead-out area so as to lead out the source electrode and the drain electrode.
9. The method of claim 8, wherein the metal is tungsten.
10. A flash memory, characterized in that it is manufactured by the method of any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610936627.7A CN107994021B (en) | 2016-10-24 | 2016-10-24 | Flash memory and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610936627.7A CN107994021B (en) | 2016-10-24 | 2016-10-24 | Flash memory and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107994021A CN107994021A (en) | 2018-05-04 |
| CN107994021B true CN107994021B (en) | 2020-07-10 |
Family
ID=62028362
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610936627.7A Active CN107994021B (en) | 2016-10-24 | 2016-10-24 | Flash memory and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107994021B (en) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4583878B2 (en) * | 2004-10-29 | 2010-11-17 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
| KR100669346B1 (en) * | 2005-11-11 | 2007-01-16 | 삼성전자주식회사 | Non-volatile memory device having floating gate and method of forming the same |
| CN100468744C (en) * | 2006-01-19 | 2009-03-11 | 力晶半导体股份有限公司 | Non-volatile storage and its producing method |
| CN104157615B (en) * | 2013-05-15 | 2017-03-22 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for flash memory |
| JP2016162904A (en) * | 2015-03-03 | 2016-09-05 | ルネサスエレクトロニクス株式会社 | Semiconductor device manufacturing method |
-
2016
- 2016-10-24 CN CN201610936627.7A patent/CN107994021B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN107994021A (en) | 2018-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI427706B (en) | Semiconductor device having nano-pillars and method therefor | |
| US9831354B2 (en) | Split-gate flash memory having mirror structure and method for forming the same | |
| JP2013165266A (en) | Semiconductor device and method of manufacturing the same | |
| JP2005183918A (en) | Method of forming bit-line of semiconductor device | |
| CN106653758B (en) | Method for manufacturing flash memory | |
| JP6355139B2 (en) | Memory structure having self-aligned floating gate and control gate and associated method | |
| JP2007036173A (en) | Flash memory device and manufacturing method of the same | |
| US20090212345A1 (en) | Semiconductor Device and Method for Manufacturing the Same | |
| JP2009010088A (en) | Semiconductor device and its manufacturing method | |
| CN106684088A (en) | Nitride-free spacer or oxide spacer for embedded flash memory | |
| CN100452358C (en) | Method of manufacturing a flash memory device | |
| KR100953050B1 (en) | Nonvolatile memory device and method of manufacturing the same | |
| JP4500668B2 (en) | Method for manufacturing flash memory device | |
| US20100032762A1 (en) | Stack-Type Semiconductor Device | |
| CN106206446B (en) | The production method for being embedded in the flash memory of logic circuit | |
| CN107994021B (en) | Flash memory and manufacturing method thereof | |
| US9595444B2 (en) | Floating gate separation in NAND flash memory | |
| JP2007013171A (en) | Method of manufacturing nand flash memory device | |
| CN105655341A (en) | Method for forming semiconductor device | |
| CN105513954A (en) | Forming method of semiconductor device | |
| US20090004820A1 (en) | Method of Forming Isolation Layer in Flash Memory Device | |
| TWI395290B (en) | Flash memory and method of fabricating the same | |
| US20080102618A1 (en) | Method of manufacturing semiconductor device | |
| JP2008091861A (en) | Manufacturing method of flash memory device | |
| JP2007013170A (en) | Flash memory element, its driving method and manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Room 101, Floor 1-5, Building 8, Yard 9, Fenghao East Road, Haidian District, Beijing 100094 Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 100083 12 Floors, Block A, Tiangong Building, Science and Technology University, 30 College Road, Haidian District, Beijing Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |