CN102054679B - Method for etching interpoly dielectric - Google Patents

Method for etching interpoly dielectric Download PDF

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CN102054679B
CN102054679B CN2009101987880A CN200910198788A CN102054679B CN 102054679 B CN102054679 B CN 102054679B CN 2009101987880 A CN2009101987880 A CN 2009101987880A CN 200910198788 A CN200910198788 A CN 200910198788A CN 102054679 B CN102054679 B CN 102054679B
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layer
dry etching
polysilicon
etching
peripheral circuit
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CN102054679A (en
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吴爱明
李俊
庄晓辉
张世栋
王三坡
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The invention discloses a method for etching an interpoly dielectric. The method comprises the following steps of: depositing the interpoly dielectric on a polycrystalline silicon layer, photoetching and etching to remove the interpoly dielectric by a first dry method, etching the polycrystalline silicon layer by a second dry method and by taking the polycrystalline silicon layer as a stop layer, and finally etching an oxidation layer by a wet method. A flat front oxidation layer can be obtained by the method provided by the invention, damage to a silicon substrate is reduced and failure rate of electrical property thickness of the oxidation layer of a high-voltage device is reduced.

Description

Dielectric etch method between a kind of polysilicon layer
Technical field
The present invention relates to semiconductor fabrication, dielectric etch method between particularly a kind of polysilicon layer.
Background technology
At present; Flash memory is as a kind of main non-effumability (NV; Non-Volatile) memory device, it compares another kind of non-volatility memorizer spare electricallyerasable ROM (EEROM) (EEPROM at smart card, for fields such as controller are widely used; Electrically Erasable Programmable Read Only Memory); Flash memory has the advantage on the tangible area, still, and the electrical thickness Problem of Failure of the high tension apparatus gate oxide of the flash memory long-term existence peripheral circuit region that (minimum dimension) is 0.22 micron; Failure rate is about 30 percent, analyze find the electrical thickness of gate oxide and oxide layer-nitride layer-oxide layer (ONO) dry etching after the anterior layer oxidated layer thickness relevant.
The flash memory of non-volatility memorizer spare comprises parts such as memory cell areas and peripheral circuit region; In the manufacture process of flash memory; Generally can form the different structure of memory cell areas and peripheral circuit region then through steps such as photoetching and etchings according to the needs of difference in functionality in memory cell areas and peripheral circuit region while growth of device layers.Memory cell areas mainly comprises gate oxide, floating boom, ONO polysilicon inter-level dielectric and control gate.Peripheral circuit region mainly contains high tension apparatus gate oxide and high tension apparatus control gate etc.It is as shown in Figure 1 to make in the peripheral circuit region process between polysilicon layer the concrete processing step of dielectric etch in the prior art flash memory, and Fig. 2 a to 2e is a peripheral circuit region generalized section in the dielectric etch flow process between prior art flash memory polysilicon layer:
Step 11, on the anterior layer oxide layer 102 of wafer 101 deposition first polysilicon layer 103, obtain structure shown in Fig. 2 a in memory cell areas and peripheral circuit region, wherein right-hand component is represented peripheral circuit region, left-hand component is represented memory cell areas;
In this step, deposit the growth of first polysilicon layer, 103 usefulness boiler tubes and realize;
Step 12, first polysilicon layer 103 is carried out photoetching and dry etching, remove first polysilicon layer 103 of peripheral circuit region, expose anterior layer oxide layer 102, form floating boom, obtain structure shown in Fig. 2 b in memory cell areas;
Photoetching and dry etching in this step are meant; Earlier smear one deck photoresist on first polysilicon layer, 103 surfaces; As required mask plate pattern makes public and development makes the photoresist patterning then; Then dry etching is not carried out by the part of photoresist pattern covers in first polysilicon layer, 103 surfaces, clean the photoresist that remains in first polysilicon layer, 103 surfaces at last;
In this step, dry etching is to use the plasma gas etching.。
The device side deposit spathic silicon inter-level dielectric of step 13, wafer 101 (IPD, Inter-poly Dielectric) consists of oxide layer-nitride layer-oxide layer (ONO);
In this step, shown in Fig. 2 c, the concrete structure of IPD is to be the following oxide layer 104 of 40 dusts by bottom thickness, and interior thickness is that the nitration case 105 of 100 dusts is last oxide layer 106 compositions of 40 dusts with top thickness.
Dry etching peripheral circuit region IPD after the device side photoetching of step 14, wafer 101;
Photoetching in this step is meant, smears one deck photoresist in wafer 101 device side earlier, and as required mask plate pattern makes public and development makes the photoresist patterning then;
In this step; Shown in Fig. 2 d; Dry etching peripheral circuit region IPD does not remove to be carried out dry etching by the part of photoresist pattern covers, removes oxide layer 106 and nitration case 105 fully through dry etching, and controls this and be dry-etched in down oxide layer 104 and stop;
In this step, the used gas of dry etching is fluoroform (CHF3), argon gas (Ar) and oxygen (O 2).
Step 15, wet etching are removed residual following oxide layer 104 and the part anterior layer oxide layer 102 of peripheral circuit region, obtain structure shown in Fig. 2 e;
In this step, wet etching is to utilize the photoetching window that stays after the photoetching and dry etching in the step 14 as mask, and the photoetching window is meant the photoresist that photoetching stays in the step 14;
In this step, wet etching is with low concentration resilient coating oxide etching method, and obtains the anterior layer thickness of oxide layer and should be controlled at 10 dusts;
In this step,, wet etching also to clean the photoresist that remains in the IPD surface after removing peripheral circuit region residual following oxide layer 104 and part anterior layer oxide layer 102.
The device side growth high tension apparatus gate oxide of step 16, wafer 101;
In this step, growth high tension apparatus gate oxide is to grow with boiler tube.
The device side of step 17, wafer 101 deposits second polysilicon layer;
In this step, second polysilicon layer forms control gate in memory cell areas, forms the high tension apparatus control gate at peripheral circuit region;
In this step, depositing second polysilicon layer is to realize with the boiler tube growth.
In above step; Etching to IPD is to adopt first dry etching; Guarantee to remove fully in the ONO trilaminate material on after oxide layer and the nitration case again with the residual following oxide layer of wet etching removal; Yet because dry etching need be removed the silicon dioxide of oxide layer and two kinds of materials of silicon nitride of nitration case, and existing etch recipe can't find a stable etch rate, and also is difficult to through the adjustment of dry etching prescription (recipe) being found best etch period.Therefore; Above-mentioned dry etching can make residual following thickness of oxide layer inhomogeneous; Even the plasma gas used of dry etching produces damage to the silicon substrate of anterior layer oxide layer below, influence the electrical thickness of high tension apparatus gate oxide that boiler tube is grown in the subsequent technique, causes component failure.
Summary of the invention
In view of this; The technical problem that the present invention solves is: oxide layer is gone up in the dry etching removal and nitration case can cause residual following oxidated layer thickness inhomogeneous; Even cause silicon substrate damage in various degree; Influence the electrical thickness of high tension apparatus gate oxide of boiler tube growth in the subsequent technique, cause component failure.
For addressing the above problem, technical scheme of the present invention specifically is achieved in that
A kind of lithographic method of polysilicon inter-level dielectric is applied to make in the peripheral circuit region process in the flash memory, and this method comprises:
Wafer is provided, has the anterior layer oxide layer on the device side of said wafer;
Deposit spathic silicon layer on said anterior layer oxide layer;
The polysilicon layer of the first dry etching memory cell areas forms floating boom after said polysilicon layer carries out first photoetching;
The deposit spathic silicon inter-level dielectric comprises oxide layer on said polysilicon layer, nitration case and following oxide layer three parts;
The said peripheral circuit region polysilicon of second dry etching inter-level dielectric after second photoetching;
The 3rd dry etching peripheral circuit region polysilicon layer;
Wet etching peripheral circuit region anterior layer oxide layer.
Said deposit spathic silicon layer is to grow with boiler tube.
The used gas of said second dry etching is fluoroform CHF 3, argon Ar and oxygen O 2
Said second dry etching is to remove the polysilicon inter-level dielectric fully, and etching stopping is at polysilicon layer.
Said the 3rd dry etching is to use the plasma gas etching.
Said the 3rd dry etching is to remove polysilicon layer fully, exposes said anterior layer oxide layer.
Said wet etching peripheral circuit region anterior layer oxide layer is with low concentration resilient coating oxide etching method.
Visible by above-mentioned technical scheme, the present invention has improved the processing step of flash memory ONO etching in the prior art, with the stop layer of polysilicon layer as dry etching ONO, behind dry etching ONO, forms floating boom through the etch polysilicon layer in memory cell areas again.The method can obtain more smooth anterior layer oxide layer at peripheral circuit region.Reduce silicon substrate damage, reduce the failure rate of the electrical thickness of high tension apparatus gate oxide.
Description of drawings
Fig. 1 makes in the peripheral circuit region process the concrete processing step of dielectric etch between polysilicon layer in the prior art flash memory;
Fig. 2 a to 2e is memory cell areas and a peripheral circuit region generalized section in the dielectric etch flow process between prior art flash memory polysilicon layer;
Fig. 3 is for making in the peripheral circuit region process the concrete processing step of dielectric etch between polysilicon layer in the flash memory of the present invention;
Fig. 4 a to Fig. 4 e is memory cell areas and peripheral circuit region generalized section in the dielectric etch flow process between flash memory polysilicon layer of the present invention.
Embodiment
For make the object of the invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.
It is as shown in Figure 3 to make in the peripheral circuit region process between polysilicon layer the concrete processing step of dielectric etch in the flash memory of the present invention, and Fig. 4 a to Fig. 4 f representes between flash memory polysilicon layer of the present invention memory cell areas and peripheral circuit region generalized section in the dielectric etch flow process:
Step 31, on the anterior layer oxide layer 102 of wafer 101 deposition first polysilicon layer 103, obtain structure shown in Fig. 4 a, wherein right-hand component is represented peripheral circuit region, left-hand component is represented memory cell areas;
In this step, depositing first polysilicon layer 103 is to realize with the boiler tube growth.
First polysilicon layer of the first dry etching memory cell areas forms floating boom after step 32, first photoetching, keeps peripheral circuit region first polysilicon layer;
In this step, first photoetching is meant, smears one deck photoresist at first polysilicon layer earlier; As required mask plate pattern makes public and development makes the photoresist patterning then; Wherein, the mask plate pattern is compared prior art and is adjusted, and keeps original storage area structure; Change the peripheral circuit region pattern, make peripheral circuit region by the photoresist pattern covers;
In this step, first dry etching can form floating boom in memory cell areas, and the structure of peripheral circuit region does not change;
In this step, also to clean the photoresist that remains in first polysilicon layer surface behind first dry etching.
Deposition ONO IPD on step 33, first polysilicon layer 103;
4b as shown in the figure, the concrete structure of ONO IPD are to be the following oxide layer 104 of 40 dusts by bottom thickness, and interior thickness is that the nitration case 105 of 100 dusts is last oxide layer 106 compositions of 40 dusts with top thickness.
The second dry etching peripheral circuit region ONO IPD after step 34, second photoetching;
Second photoetching in this step is meant, smears one deck photoresist in wafer 101 device side earlier, and as required mask plate pattern makes public and development makes the photoresist patterning then;
In this step, second dry etching can remove the polysilicon inter-level dielectric of peripheral circuit region, exposes first polysilicon layer 103, obtains structure shown in Fig. 4 c;
In this step; The second dry etching peripheral circuit region ONO IPD is to not carried out dry etching by the part of photoresist pattern covers; Remove on the peripheral circuit region oxide layer 106 and nitration case 105 and following oxide layer 104 fully through dry etching, with first polysilicon 103 for stopping layer;
In this step, the used gas of second dry etching is fluoroform (CHF 3), argon gas (Ar) and oxygen (O 2).
In this step, first polysilicon layer of the peripheral circuit region that keeps in step 32 is as the layer that stops of the second dry etching ONO IPD, also as the substrate protective layer in the peripheral circuit region ONO IPD etching.
Step 35, the 3rd dry etching peripheral circuit region first polysilicon layer 103;
In this step, the 3rd dry etching can remove first polysilicon layer 103 of peripheral circuit region, exposes anterior layer oxide layer 102, obtains structure shown in Fig. 4 d;
In this step, the 3rd dry etching utilizes and stays the photoetching window in the step 34 after the photoetching and carry out as mask, and the photoetching window is meant the photoresist that second photoetching stays in the step 34;
In this step, the 3rd dry etching is to use the plasma gas etching.
Step 36, wet etching peripheral circuit region anterior layer oxide layer 102;
In this step, wet etching utilizes and stays the photoetching window in the step 34 after the photoetching and carry out for mask, and the photoetching window is meant the photoresist that photoetching stays in the step 33;
In this step, wet etching peripheral circuit region anterior layer oxide layer 102 is meant, to not carried out wet etching by the part of photoresist pattern covers, obtains the structure shown in Fig. 4 e;
In this step, wet etching is with low concentration resilient coating oxide etching method, and obtains anterior layer oxide layer 102 thickness more than or equal to 15 dusts;
In this step, also to clean the photoresist that remains in the IPD surface after the wet etching peripheral circuit region anterior layer oxide layer 102.
The device side growth high tension apparatus gate oxide of step 37, wafer 101;
In this step, growth high tension apparatus gate oxide is to grow with boiler tube.
The device side of step 38, wafer 101 deposits second polysilicon layer;
In this step, second polysilicon layer forms control gate in memory cell areas, forms the high tension apparatus control gate at peripheral circuit region;
In this step, depositing second polysilicon layer is to grow with boiler tube.
Among the present invention; The second dry etching ONO IPD of step 34 because the polysilicon that ONO IPD below arranged as the etching resilient coating; Therefore control ratio is easier to; As long as guarantee to remove three layers of ONO structure of IPD fully and stop just passablely at first polysilicon layer, need not consider damage to first polysilicon.In step 35, the used gas of the 3rd dry etching only can etch polysilicon and the silicon dioxide of oxide layer under can etching, obtains thickness and descends oxide layer uniformly, and do not damage silicon substrate.Behind the wet etching of step 36, obtain at last the smooth and stable anterior layer oxide layer of thickness, the failure rate of the electrical thickness of the high tension apparatus gate oxide of reduction subsequent technique growth.
Though the present invention has changed the processing step of prior art, can obtain memory cell areas and peripheral circuit region with prior art same structure and function through corresponding adjustment mask blank pattern.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (6)

1. the lithographic method of a polysilicon inter-level dielectric is applied to make in the peripheral circuit region process in the flash memory, and this method comprises:
Wafer is provided, has the anterior layer oxide layer on the device side of said wafer;
Deposit spathic silicon layer on said anterior layer oxide layer;
The polysilicon layer of the first dry etching memory cell areas forms floating boom after said polysilicon layer carries out first photoetching;
The deposit spathic silicon inter-level dielectric comprises oxide layer on said polysilicon layer, nitration case and following oxide layer three parts;
The said peripheral circuit region polysilicon of second dry etching inter-level dielectric after second photoetching;
The 3rd dry etching peripheral circuit region polysilicon layer;
Wet etching peripheral circuit region anterior layer oxide layer.
2. the method for claim 1, it is characterized in that: said deposit spathic silicon layer is to grow with boiler tube.
3. the method for claim 1, it is characterized in that: the used gas of said second dry etching is fluoroform CHF 3, argon Ar and oxygen O 2
4. the method for claim 1, it is characterized in that: said second dry etching is to remove the polysilicon inter-level dielectric fully, and etching stopping is at polysilicon layer.
5. the method for claim 1, it is characterized in that: said the 3rd dry etching is to use the plasma gas etching.
6. the method for claim 1, it is characterized in that: said the 3rd dry etching is to remove polysilicon layer fully, exposes said anterior layer oxide layer.
CN2009101987880A 2009-11-09 2009-11-09 Method for etching interpoly dielectric Active CN102054679B (en)

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CN112635311A (en) * 2020-12-07 2021-04-09 华虹半导体(无锡)有限公司 Gate oxide forming method of semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1420541A (en) * 2001-11-20 2003-05-28 旺宏电子股份有限公司 Method for mfg. system integrated chip
CN101197263A (en) * 2006-12-05 2008-06-11 中芯国际集成电路制造(上海)有限公司 Forming method of high voltage transistor and memory device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1420541A (en) * 2001-11-20 2003-05-28 旺宏电子股份有限公司 Method for mfg. system integrated chip
CN101197263A (en) * 2006-12-05 2008-06-11 中芯国际集成电路制造(上海)有限公司 Forming method of high voltage transistor and memory device

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