CN109065633A - Storage unit and forming method thereof - Google Patents
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- CN109065633A CN109065633A CN201810882381.9A CN201810882381A CN109065633A CN 109065633 A CN109065633 A CN 109065633A CN 201810882381 A CN201810882381 A CN 201810882381A CN 109065633 A CN109065633 A CN 109065633A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000007667 floating Methods 0.000 claims abstract description 46
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 63
- 229920005591 polysilicon Polymers 0.000 claims description 40
- 230000004888 barrier function Effects 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 7
- 230000000903 blocking effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 8
- 230000015654 memory Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- PMHURSZHKKJGBM-UHFFFAOYSA-N isoxaben Chemical group O1N=C(C(C)(CC)CC)C=C1NC(=O)C1=C(OC)C=CC=C1OC PMHURSZHKKJGBM-UHFFFAOYSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
The present invention provides a kind of storage unit and forming method thereof, the storage unit includes FGS floating gate structure, control grid structure and word line structure, and the FGS floating gate structure has tip towards the side of the word line structure.In storage unit provided by the invention and forming method thereof, there is tip towards the side of word line structure in FGS floating gate structure, pass through the point effect at tip, electrons when wiping device in FGS floating gate structure are shifted by tip to word line structure, efficiency of erasing when effective raising erasing operation, to improve the performance of storage unit.
Description
Technical field
The present invention relates to technical field of integrated circuits, in particular to a kind of storage unit and forming method thereof.
Background technique
Memory can be used for storing a large amount of digital information, and presently, there are the memories of numerous types, as RAM is (random
Memory), DRAM (dynamic RAM), ROM (read-only memory), EPROM (Erasable Programmable Read Only Memory EPROM),
FLASH (flash memory) etc..
In the prior art, floating gate type flash memory is as a kind of nonvolatile storage, as shown in Figure 1, floating gate type flash memory is deposited
Storage unit suffers from similar original unit framework, they have the gate structure of stacking, which includes FGS floating gate structure
1, at least partly cover floating gate control grid structure 2 and word line structure 3, wherein control grid structure 2 can be controlled by coupling it is floating
The storage and release of electronics in grid structure 1.When the electric field between control grid structure 2 and word line structure 3 is sufficiently high, floating gate knot
Electronics in structure 1 is drawn out between FGS floating gate structure 1 and word line structure 3, to realize the erasing operation of storage unit.
Therefore, how to provide a kind of storage unit with better erasing effect is that those skilled in the art are urgently to be resolved
A technical problem.
Summary of the invention
The purpose of the present invention is to provide a kind of storage units and forming method thereof, to improve storage unit in the prior art
Erasing effect.
In order to solve the above technical problems, the present invention provides a kind of storage unit, the storage unit includes FGS floating gate structure, control
Grid structure processed and word line structure, the FGS floating gate structure have tip towards the side of the word line structure.
Optionally, in the storage unit, the control gate structure is towards the FGS floating gate structure and towards the word
The side of cable architecture has an ono dielectric layer.
Optionally, in the storage unit, the thickness of silicon oxide layer is all in the ono dielectric layerIts
Middle silicon nitride layer with a thickness of
Optionally, in the storage unit, the FGS floating gate structure and the control grid structure are far from described offline
The side of structure has sidewall structure.
The present invention also provides a kind of forming method of storage unit, the forming method of the storage unit includes:
One substrate is provided, there is the first polycrystalline silicon medium layer on the substrate, have on the first polycrystalline silicon medium layer
First polysilicon layer；
Barrier structure is formed on first polysilicon layer；
First polysilicon layer is performed etching, forms slope in the position close to the barrier structure；
The second polycrystalline silicon medium layer is formed on first polysilicon layer, is formed on the second polycrystalline silicon medium layer
Second polysilicon layer；
It etches second polysilicon and forms control grid structure, then etch first polysilicon layer and retain floating gate knot out
Structure region；
The barrier structure is removed, first polysilicon is performed etching in the position on the slope to be formed with tip
FGS floating gate structure.
Optionally, in the forming method of the storage unit, on first polysilicon layer and the blocking junction
The second polycrystalline silicon medium layer is formed simultaneously on the two sides of structure.
Optionally, in the forming method of the storage unit, second polysilicon layer is ono dielectric layer.
Optionally, in the forming method of the storage unit, the thickness of silicon oxide layer is all in the ono dielectric layerWherein silicon nitride layer with a thickness of
Optionally, in the forming method of the storage unit, the material of the barrier structure includes silicon nitride.
Optionally, in the forming method of the storage unit, further includes: in the FGS floating gate structure and the control gate
Structure forms sidewall structure far from the side of word line structure, and the material of the sidewall structure includes silicon nitride.
In conclusion in storage unit provided by the invention and forming method thereof, in FGS floating gate structure towards word line structure
Side there is tip, by the point effect at tip, electrons when wipe device in FGS floating gate structure pass through tip to word
Cable architecture transfer effectively improves efficiency of erasing when erasing operation, to improve the performance of storage unit.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the storage unit of the prior art；
Fig. 2 is the flow diagram of the forming method of the storage unit of the embodiment of the present invention；
Fig. 3-9 is structural schematic diagram of the storage unit of the embodiment of the present invention in forming process；
Wherein, 1,32- FGS floating gate structure, 2,61- control grid structure, 3,70- word line structure, 10- substrate, 20- first
Polycrystalline silicon medium layer, the first polysilicon layer of 30-, the slope 31-, 40- barrier structure, 50- the second polycrystalline silicon medium layer, 60-
Second polysilicon layer, 80- sidewall structure.
Specific embodiment
In order to keep objects, features and advantages of the present invention more obvious and easy to understand, attached drawing is please referred to.It should be clear that this explanation
Book structure depicted in this specification institute accompanying drawings, ratio, size etc., only to cooperate the revealed content of specification, for being familiar with this
The personage of technology understands and reads, and is not intended to limit the invention enforceable qualifications, therefore does not have technical essence meaning
Justice, the modification of any structure, the change of proportionate relationship or the adjustment of size are not influencing the effect of present invention can be generated and institute
Under the purpose that can reach, should all still it fall in the range of disclosed technology contents obtain and can cover.
As shown in figure 9, the present invention provides a kind of storage unit, the storage unit includes FGS floating gate structure 32, control gate knot
Structure 61 and word line structure 70, the FGS floating gate structure 32 towards the word line structure 70 side have tip, storage unit it is whole
It is close with the floating gate type flash memory in prior art in body structure, but subtle improvement has been done for the shape of FGS floating gate structure, pass through
Towards word line structure side formed tip to promote erasing operation when FGS floating gate structure in electronics transfer, tip can also work as
Make protrusion or part outstanding.
It is corresponding with the structure of storage unit, as shown in Fig. 2, the present invention also provides a kind of formation sides of storage unit
The forming method of method, the storage unit includes:
Step S10: as shown in figure 3, providing a substrate 10, there is the first polycrystalline silicon medium layer 20, institute on the substrate 10
Stating has the first polysilicon layer 30 on the first polycrystalline silicon medium layer 20, the material of the first polycrystalline silicon medium layer includes silica,
Foundation structure in embodiment only for storage unit is described, for other active structures such as source/drain and gold
Belonging to connection (CT, Contact) etc. can refer to prior art processing；
Step S20: as shown in figure 4, forming barrier structure 40 on first polysilicon layer 30, barrier structure 40 can be
Barrier effect is played in the formation of subsequent other structures, can form corresponding film layer on the first polysilicon layer, etch away and do not need
Region i.e. obtain the barrier structure, optionally, the material of the barrier structure 40 includes silicon nitride；
Step S30: as shown in figure 5, being performed etching to first polysilicon layer 30, close to the barrier structure 40
Position forms slope 31, namely can all be formed centainly in two sides under the influence of the position close to barrier structure is in etch rate
The pattern of the gradient, such as gradient size can be 10 degree~80 degree；
Step S40: as shown in fig. 6, then, the second polycrystalline silicon medium layer 50 is formed on first polycrystal layer 30,
The second polysilicon layer 60 is formed on the second polycrystalline silicon medium layer 50；
Step S50: as shown in fig. 7, then, etching second polysilicon 60 and forming control grid structure 61, can control
Then first polysilicon layer 30 is etched on the basis of grid structure 61 and retains FGS floating gate structure region out, at this point, FGS floating gate structure is also
It is unformed so only retain the region out, in the present embodiment, for ease of description, in etching technics for may relate to
To photoresist and its graphical and removal photoetching the specific steps such as lack and have not been described in detail, and be situated between for the first polysilicon
The redundance of matter layer and the second polycrystalline silicon medium layer is removed, further for other dielectric materials that are related to (as aoxidized
Silicon) filling and removal and chemical mechanical grinding etc., those skilled in the art can be implemented by using the prior art in each step
The structure of required formation；
Step S60: as shown in figure 8, followed by, the barrier structure 40 is removed, it can be complete in such a way that wet process removes
Barrier structure is got rid of, performs etching that form tool cuspidated floating to first polysilicon layer 30 in the position on the slope 31
Grid structure 32, that is, continue the first polysilicon layer 30 of etching downwards after barrier structure 40 removes, it will be in the position on slope 31
It sets to form tip (part with reference to shown in the virtual coil A in attached drawing), it is last as shown in figure 9, in control grid structure 61 and floating gate knot
Structure 32 can carry out being formed the technique of word line structure 70 after being formed, that is, deposit wordline polysilicon after forming tunneling oxide layer
Layer.
In the storage unit of the present embodiment, the control grid structure 61 is towards the FGS floating gate structure 32 and towards described
The side of word line structure 70 has an ONO (Oxide-Nitride-Oxide) dielectric layer, that is, control grid structure 61 and floating gate
Between structure 32 and same ono dielectric layer is formed between control grid structure 61 and word line structure 70 to be isolated.Corresponding to depositing
In the forming method of storage unit, is formed simultaneously on first polysilicon layer 30 and on the two sides of the barrier structure 40
Two polycrystalline silicon medium layers 50, can be simultaneously on the first polysilicon layer 30 and barrier structure 40 by modes such as chemical meteorology depositions
Two sides form the second polycrystalline silicon medium layer 50.In the present embodiment, second polysilicon layer 50 is ono dielectric layer.Optionally,
The thickness of silicon oxide layer is all in the ono dielectric layerWherein silicon nitride layer with a thickness of?
Same thickness range can be used in two layers of silicon oxide layer in ono dielectric layer formation process, but the thickness of two layers of silicon oxide layer is not
It is required that consistent.
In storage unit in the present embodiment, refering to what is shown in Fig. 9, the FGS floating gate structure 32 and the control grid structure
61 have sidewall structure 80 in the side far from the word line structure 70, that is, can form sidewall structure in two sides, can pass through
Sidewall structure carries out electrical protection to FGS floating gate structure and control grid structure.The formation side of storage unit in corresponding the present embodiment
In method, sidewall structure 80 is formed far from the side of word line structure 70 in the FGS floating gate structure and the control grid structure 61,
It is exactly that can distinguish each formation sidewall structure 80 in two sides after forming word line structure 70, the material of the sidewall structure 80 includes
Silicon nitride.
Compared with the prior art, in the forming step of storage unit of the invention after forming the first polysilicon layer with regard to shape
At barrier structure, the second polycrystalline silicon medium layer and the second polysilicon layer are formed under the barrier effect of barrier structure.It is existing
It is used in technology and sequentially forms the first polycrystalline silicon medium layer, the first polysilicon layer, the second polycrystalline silicon medium layer and the second polysilicon
Layer, is subsequently formed word line structure, finally completes FGS floating gate structure and control grid structure.And corresponding in the solution of the present invention, first shape
At FGS floating gate structure and control grid structure, word line structure is eventually formed.
In conclusion in storage unit provided by the invention and forming method thereof, in FGS floating gate structure towards word line structure
Side there is tip, by the point effect at tip, electrons when wipe device in FGS floating gate structure pass through tip to word
Cable architecture transfer effectively improves efficiency of erasing when erasing operation, to improve the performance of storage unit.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (10)
1. a kind of storage unit, which is characterized in that the storage unit includes FGS floating gate structure, controls grid structure and word line structure,
The FGS floating gate structure has tip towards the side of the word line structure.
2. storage unit according to claim 1, which is characterized in that the control gate structure towards the FGS floating gate structure and
Side towards the word line structure has an ono dielectric layer.
3. storage unit according to claim 2, which is characterized in that the thickness of silicon oxide layer is all in the ono dielectric layerWherein silicon nitride layer with a thickness of
4. storage unit described in any one of -3 according to claim 1, which is characterized in that the FGS floating gate structure and described
Controlling grid structure has sidewall structure in the side far from the word line structure.
5. a kind of forming method of storage unit, which is characterized in that the forming method of the storage unit includes:
One substrate is provided, there is the first polycrystalline silicon medium layer on the substrate, have first on the first polycrystalline silicon medium layer
Polysilicon layer；
Barrier structure is formed on first polysilicon layer；
First polysilicon layer is performed etching, forms slope in the position close to the barrier structure；
The second polycrystalline silicon medium layer is formed on first polysilicon layer, forms second on the second polycrystalline silicon medium layer
Polysilicon layer；
It etches second polysilicon layer and forms control grid structure, then etch first polysilicon layer and retain FGS floating gate structure out
Region；
The barrier structure is removed, performs etching that form tool cuspidated floating to first polysilicon in the position on the slope
Grid structure.
6. the forming method of storage unit according to claim 5, which is characterized in that on first polysilicon layer and
The second polycrystalline silicon medium layer is formed simultaneously on the two sides of the barrier structure.
7. the forming method of storage unit according to claim 6, which is characterized in that second polysilicon layer is ONO Jie
Matter layer.
8. the forming method of storage unit according to claim 7, which is characterized in that silicon oxide layer in the ono dielectric layer
Thickness be allWherein silicon nitride layer with a thickness of
9. according to the forming method of storage unit described in any one of claim 5-8, which is characterized in that the blocking junction
The material of structure includes silicon nitride.
10. according to the forming method of storage unit described in any one of claim 5-8, which is characterized in that the storage is single
The forming method of member further include: form side wall far from the side of word line structure in the FGS floating gate structure and the control grid structure
Structure, the material of the sidewall structure include silicon nitride.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810882381.9A CN109065633A (en) | 2018-08-06 | 2018-08-06 | Storage unit and forming method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810882381.9A CN109065633A (en) | 2018-08-06 | 2018-08-06 | Storage unit and forming method thereof |
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| CN109065633A true CN109065633A (en) | 2018-12-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110085592A (en) * | 2019-04-30 | 2019-08-02 | 上海华虹宏力半导体制造有限公司 | Flash memory fabrication method |
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| US20110248328A1 (en) * | 2010-04-09 | 2011-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stucture for flash memory cells |
| CN103050446A (en) * | 2012-12-20 | 2013-04-17 | 上海宏力半导体制造有限公司 | Split-gate flash memory and forming method thereof |
| TW201508753A (en) * | 2013-08-29 | 2015-03-01 | Chrong-Jung Lin | Memory cell, memory array and operation method thereof |
| CN104538367A (en) * | 2014-12-30 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Mirror image split gate flash memory and forming method thereof |
-
2018
- 2018-08-06 CN CN201810882381.9A patent/CN109065633A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110248328A1 (en) * | 2010-04-09 | 2011-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Stucture for flash memory cells |
| CN103050446A (en) * | 2012-12-20 | 2013-04-17 | 上海宏力半导体制造有限公司 | Split-gate flash memory and forming method thereof |
| TW201508753A (en) * | 2013-08-29 | 2015-03-01 | Chrong-Jung Lin | Memory cell, memory array and operation method thereof |
| CN104538367A (en) * | 2014-12-30 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Mirror image split gate flash memory and forming method thereof |
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| CN110085592A (en) * | 2019-04-30 | 2019-08-02 | 上海华虹宏力半导体制造有限公司 | Flash memory fabrication method |
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