CN107946311B - Method for controlling critical dimension of channel in 3D NAND flash memory structure - Google Patents
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- 230000015654 memory Effects 0.000 title claims abstract description 29
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- 238000004140 cleaning Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 72
- 238000001259 photo etching Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 17
- 238000000231 atomic layer deposition Methods 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 14
- 238000000206 photolithography Methods 0.000 claims description 10
- 239000011229 interlayer Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical group CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000001312 dry etching Methods 0.000 claims description 4
- 150000004767 nitrides Chemical class 0.000 claims description 4
- 238000001020 plasma etching Methods 0.000 abstract description 8
- 239000011810 insulating material Substances 0.000 abstract description 6
- 230000002349 favourable effect Effects 0.000 abstract description 2
- 238000005728 strengthening Methods 0.000 abstract description 2
- 238000001459 lithography Methods 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 5
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention provides a method for controlling the critical dimension of a channel of a 3D NAND flash memory structure in the channel etching process of the 3D NAND flash memory structure, which can effectively remove harmful oxide insulating materials formed on the back of a substrate by adding a wet cleaning process step before the channel etching process; harmful insulating materials formed on the back of the substrate are removed, so that the electrode on one side of the substrate is favorable for gathering more negative charges, the attraction of the positive charges and the negative charges between the positive electrode and the negative electrode of the plasma source is further enhanced, the vertical descending of the plasma source is ensured, the plasma etching is vertical to the surface of the substrate and downward etching is performed as anisotropic as possible, and useless or even harmful etching in other directions is avoided; based on the strengthening of the anisotropic etching of the plasma etching, the control of the Critical Dimension (CD) of the channel is more convenient, so that the precision of the critical dimension of the channel is effectively ensured, and the overall performance of the 3D NAND flash memory is improved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a preparation process of a 3D NAND flash memory structure, and particularly relates to a method for controlling Critical Dimension (Critical Dimension) in a channel etching process of the 3D NAND flash memory structure.
Background
With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others. In this context, to solve the difficulties encountered by flat flash memories and to maximize the lower production cost of a unit cell, various three-dimensional (3D) flash memory structures, such as 3D NOR (3D NOR) flash memory and 3D NAND (3D NAND) flash memory, have come into force.
Among them, in the 3D flash memory of the NOR type structure, memory cells are arranged in parallel between bit lines and ground lines, and in the 3D flash memory of the NAND type structure, memory cells are arranged in series between bit lines and ground lines. The NAND type flash memory having the series structure has a low read speed but a high write speed, so that the NAND type flash memory is suitable for storing data, and has advantages of small size and large capacity. Flash memory devices may be classified into a stacked gate type and a separated gate type according to the structure of a memory cell, and into a floating gate device and a silicon-oxide-nitride-oxide (SONO) device according to the shape of a charge storage layer. Among them, the SONO type flash memory device has better reliability than the floating gate type flash memory device, and can perform program and erase operations at a lower voltage, and the SONO type flash memory device has a very thin cell and is convenient to manufacture.
For example, in a 3D NAND flash memory manufacturing process including a Top-layer Select gate Cut (Top Select gate Cut) forming step, the Channel etching is usually performed according to the following process:
s1: referring to fig. 1a, a substrate stack structure (O/N Stacks)2 composed of an interlayer dielectric layer 2-1 and a sacrificial dielectric layer 2-2 is deposited on the surface of a substrate 1;
s2: performing photolithography (Photo Etch, abbreviated as PH) to form a Top-layer Select Gate Cut (Top Select Gate Cut), referring to fig. 1b, specifically, first forming a Top-layer Select Gate Cut photolithography layer 3 on the surface of a substrate stack structure (O/N Stacks) 2; then, photoetching is carried out at the position where a selection Gate tangent (Top Select Gate Cut) needs to be formed;
s3: in order to form a Top-layer Select Gate Cut (Top Select Gate Cut) for etching, referring to fig. 1c, specifically, a trench 4 of the Top-layer Select Gate Cut (Top Select Gate Cut) is formed at the aforementioned lithography position by using a conventional etching process, and the Top-layer Select Gate Cut lithography layer is removed to expose the surface of the substrate stack structure (O/N Stacks) 2;
s4: filling a Top-layer Select Gate Cut (Top Select Gate Cut) trench, referring to fig. 1d, specifically, depositing and filling a Top-layer Select Gate Cut oxide material 5 in the trench 4 by using an atomic layer deposition process (ALD);
s5: depositing a Hard Mask layer (Hard Mask, abbreviated as HM)6 for channel etching, and specifically depositing oxide/nitride/oxide in sequence with reference to fig. 1 e;
s6: to form the Channel (CH), photolithography is performed, referring to fig. 1f, specifically, a channel photolithography layer 7 is first formed on the surface of the hard mask layer (HM) 6; then, photoetching is carried out at the position where a channel needs to be formed;
s7: for etching to form a trench, referring to fig. 1g, specifically, a trench 8 is formed at the aforementioned lithography position by using a conventional etching process, and the trench lithography layer 7 is removed to expose the surface of the substrate stack structure (O/N Stacks) 2.
However, in the full process (fulllloop) process including the Top Select gate Cut (Top Select gate Cut) forming step, the Backside (Backside) of the substrate 1 is inevitably deposited with the oxide material 5 during the ALD deposition of the oxide material in step S4, and the Backside of the substrate is more difficult to retain negative charges due to the insulating property of the oxide material 5. As is well known, in the trench etching process step, an anisotropic plasma dry etching process is usually adopted to ensure that the etching occurs in the vertical direction of the substrate to the maximum extent but not in other directions, and in the etching chamber 60, as shown in fig. 2, a large amount of positive charges 20 are collected at the top electrode 10 on the side away from the substrate 1, and negative charges 40 are collected at the bottom electrode 30 on the side of the substrate 1, and the attractive force of the positive charges and the negative charges will strengthen the isotropy of the rf generated plasma source 50 to inhibit the isotropy tendency thereof, thereby better ensuring the downward etching of the plasma etching in the direction perpendicular to the substrate. However, as analyzed above, under the influence of the oxide material 5 on the back surface of the substrate 1, the negative charge 40 will be significantly reduced, so as to weaken the attractive force between the positive electrode and the negative electrode, and further increase the isotropy of the plasma etching to a certain extent, and the etching generated in the direction perpendicular to the substrate (e.g. the direction parallel to the substrate) will undoubtedly result in that it will become more difficult to control the Critical Dimension (CD), and finally the Critical Dimension (CD) will become larger, and further affect the performance of the channel and the performance of the final 3D NAND flash memory.
Therefore, how to reduce or even eliminate the Critical Dimension (CD) expansion caused by the Full process (Full Loop) including the Top Select gate Cut (Top Select gate Cut) forming step has been the direction of research effort of those skilled in the art.
Disclosure of Invention
The invention aims to provide a method for controlling the Critical Dimension (CD) of a channel in the channel etching process of a 3D NAND flash memory structure, which can effectively solve the problem of the expansion of the Critical Dimension (CD) of the channel in the whole process including the forming step of a Top-layer Select gate Cut (Top Select gate Cut), thereby improving the performance of the 3D NAND flash memory.
In order to achieve the above object, the present invention provides a method for controlling a Critical Dimension (CD) of a channel in a channel etching process of a 3D NAND flash memory structure, comprising the steps of:
depositing a substrate stack structure on the surface of the substrate;
photoetching is carried out to form a top layer selection gate tangent line;
etching to form a top selection gate tangent line so as to form a top selection gate tangent line groove;
oxide filling is carried out on the top layer selection gate tangent groove by adopting an atomic layer deposition process;
removing the oxide material formed on the back surface of the substrate by the atomic layer deposition process;
depositing a hard mask layer for channel etching;
photoetching is carried out for forming a channel;
etching is performed to form a trench.
Further, the substrate stack structure is an O/N stack structure (O/N Stacks) composed of an interlayer dielectric layer and a sacrificial dielectric layer, the interlayer dielectric layer is Tetraethylorthosilicate (TEOS), and the sacrificial dielectric layer is silicon nitride (SiN).
Further, the photoetching for forming the top selection gate tangent line comprises the steps of firstly forming a top selection gate tangent line photoetching layer on the surface of the substrate stacking structure; photolithography is then performed where the select gate tangents need to be formed.
Further, the etching for forming the top selection gate tangent line is to form a groove of the top selection gate tangent line at the photoetching position by adopting a conventional etching process, and remove the photoetching layer of the top selection gate tangent line to expose the surface of the substrate stacking structure.
Furthermore, the hard mask layer for depositing the channel etching is formed by sequentially depositing an oxide layer/a nitride layer/an oxide layer on the surface of the oxide material deposited by the atomic layer.
Further, the step of photoetching for forming the channel comprises the steps of firstly forming a channel photoetching layer on the surface of the hard mask layer; photolithography is then performed where trenches need to be formed.
Further, the etching for forming the channel is to form the channel at the photoetching position by adopting a conventional etching process, and remove the channel photoetching layer to expose the surface of the substrate stacking structure.
Further, etching is performed to form a channel, and Plasma Dry etching (Plasma Dry Etch) is adopted.
Further, the oxide material formed on the back surface of the substrate by the atomic layer deposition process is removed, and a Wet cleaning (Wet Clean) process is adopted.
Compared with the prior art, the invention has the following beneficial effects:
firstly, a wet cleaning process step is added before a channel etching process, so that harmful oxide insulating materials formed on the back surface of a substrate can be effectively removed;
secondly, harmful insulating materials formed on the back of the substrate are removed, so that the electrode on one side of the substrate is favorable for gathering more negative charges, the attraction of the positive charges and the negative charges between the positive electrode and the negative electrode of the plasma source is further enhanced, the vertical descending of the plasma source is ensured, the plasma etching is vertical to the surface of the substrate and downward etching is performed as anisotropic as possible, and useless or even harmful etching in other directions is avoided;
thirdly, based on the strengthening of the anisotropic etching of the plasma etching, the Critical Dimension (CD) of the channel can be more conveniently controlled, so that the precision of the critical dimension of the channel is effectively ensured, and the overall performance of the 3D NAND flash memory is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIGS. 1a-1g are schematic diagrams of prior art trench etching and the preceding and following process steps;
FIG. 2 is a schematic diagram illustrating the etching status in a chamber during channel etching in the prior art;
FIGS. 3a-h are schematic diagrams of the channel etching and the preceding and following process steps in the present invention;
FIG. 4 is a schematic diagram of the etching condition in the chamber during the channel etching process of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 3a-h, an embodiment of the present invention provides a method for controlling a Critical Dimension (CD) of a channel during a channel etching process of a 3D NAND flash memory structure, including the following steps:
s100: depositing a substrate stack structure on the surface of the substrate;
s200: photoetching is carried out to form a top layer selection gate tangent line;
s300: etching to form a top selection gate tangent line so as to form a top selection gate tangent line groove;
s400: oxide filling is carried out on the top layer selection gate tangent groove by adopting an atomic layer deposition process;
s500: removing the oxide material formed on the back surface of the substrate by the atomic layer deposition process;
s600: depositing a hard mask layer for channel etching;
s700: photoetching is carried out for forming a channel;
s800: etching is performed to form a trench.
Specifically, in step S100, referring to fig. 3a, a substrate stack structure 110 is deposited on a surface of a substrate 100, where the substrate stack structure 110 is an O/N stack structure (O/NStacks) composed of an interlayer dielectric layer 111 and a sacrificial dielectric layer 112, the interlayer dielectric layer 111 is preferably silicon oxide, more preferably Tetraethoxysilane (TEOS), and the sacrificial dielectric layer 112 is preferably silicon nitride (SiN).
In step S200, referring to fig. 3b, first, in step S210, a top-layer select gate tangent lithography layer 120 is formed on the surface of the substrate stack junction 110; then, step S220 is performed to perform photolithography at the position where the selection gate tangent is to be formed.
In step S300, referring to fig. 3c, a conventional etching process is used to form a top-layer-selective-gate-tangent trench 130 at the aforementioned lithography position, and the top-layer-selective-gate-tangent lithography layer 120 is removed to expose the surface of the substrate stack structure 110.
In step S400, referring to fig. 3d, the top-layer select gate tangential trench 130 is filled with an oxide material 140 by an Atomic Layer Deposition (ALD) process. Due to the atomic layer deposition process, an unnecessary oxide material 141 is inevitably formed on the back surface of the substrate 100, and as already analyzed, the unnecessary oxide material 141 affects the anisotropy of the plasma dry etching of the subsequent channel, thereby enlarging the critical dimension of the channel and causing adverse effects.
In step S500, referring to fig. 3e, an oxide material 141 formed on the back surface of the substrate 100 by an atomic layer deposition process is removed by a Wet Clean (Wet Clean) process to eliminate the adverse effect of the ALD process in the top-level select gate tangent line formation.
In step S600, referring to fig. 3f, a first oxide layer 151/a nitride layer 152/a second oxide layer 153 are sequentially deposited on the surface of the ald oxide material 140 to form a composite ONO hard mask layer 150 for channel etching.
In step S700, referring to fig. 3g, first, in step S710, a trench lithography layer 160 is formed on the surface of the composite ONO hard mask layer 150; then, step S720 is performed to perform photolithography at the position where the trench is to be formed.
In step S800, referring to fig. 3h, a trench 170 is formed at the aforementioned lithography position by using a Plasma Dry Etch (Plasma Dry Etch) process, and the trench lithography layer 160 is removed to expose the surface of the substrate stack structure.
As shown in fig. 4, by adding a wet cleaning process step S500 before the channel etching process, the harmful oxide insulating material 141 formed on the back surface of the substrate 100 can be effectively removed; because the harmful insulating material 141 formed on the back of the substrate 100 is removed, when channel etching is performed in the chamber 210, the negative electrode 181 on one side of the substrate 100 is beneficial to gather more negative charges 191, and further the mutual attraction of the positive charges 192 and the negative charges 191 between the positive electrode 182 and the negative electrode 181 of the plasma source is enhanced, so that the plasma source 200 is ensured to vertically descend, the plasma etching is anisotropic as much as possible and is downward etched perpendicular to the surface of the substrate 100, and useless or even harmful etching in other directions is avoided; and the enhancement of anisotropic etching based on plasma etching is more convenient for controlling the Critical Dimension (CD) of the channel 170, so that the precision of the critical dimension of the channel 170 is effectively ensured, and the overall performance of the 3D NAND flash memory is improved.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (6)
1. A method for controlling a channel Critical Dimension (CD) in a channel etching process of a 3D NAND flash memory structure comprises the following steps:
depositing a substrate stack structure on the surface of the substrate; the substrate stacking structure is an O/N stacking structure (O/N Stacks) composed of an interlayer dielectric layer and a sacrificial dielectric layer, the interlayer dielectric layer is Tetraethylorthosilicate (TEOS), and the sacrificial dielectric layer is silicon nitride (SiN);
photoetching is carried out to form a top layer selection gate tangent line;
etching to form a top selection gate tangent line so as to form a top selection gate tangent line groove;
oxide filling is carried out on the top layer selection gate tangent groove by adopting an atomic layer deposition process;
removing the oxide material formed on the back surface of the substrate by the atomic layer deposition process;
depositing a hard mask layer for channel etching; the hard mask layer for depositing channel etching is formed by sequentially depositing an oxide layer/a nitride layer/an oxide layer on the surface of an oxide material deposited by an atomic layer;
photoetching is carried out for forming a channel;
etching to form a channel; in order to form a channel, etching is carried out by adopting a Plasma dry etching (Plasma DryEtch).
2. The method of claim 1, wherein:
photoetching for forming a top selection gate tangent line, namely firstly forming a top selection gate tangent line photoetching layer on the surface of the substrate stacking structure; photolithography is then performed where the select gate tangents need to be formed.
3. The method of claim 2, wherein:
and etching to form the top selection gate tangent line, namely forming a groove of the top selection gate tangent line at the photoetching position by adopting a conventional etching process, and removing the photoetching layer of the top selection gate tangent line to expose the surface of the substrate stacking structure.
4. The method of claim 1, wherein:
the photoetching for forming the channel comprises the steps of firstly forming a channel photoetching layer on the surface of the hard mask layer; photolithography is then performed where trenches need to be formed.
5. The method of claim 4, wherein:
and the etching for forming the channel comprises the steps of forming the channel at the photoetching position by adopting a conventional etching process, and removing the photoetching layer of the channel to expose the surface of the substrate stacking structure.
6. The method according to any one of claims 1 to 5, wherein:
and removing the oxide material formed on the back surface of the substrate by the atomic layer deposition process, and adopting a Wet cleaning (Wet Clean) process.
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| CN1542923A (en) * | 2003-04-28 | 2004-11-03 | 台湾积体电路制造股份有限公司 | Method for making semiconductor structure |
| CN106935592A (en) * | 2015-12-31 | 2017-07-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of 3D nand flash memories |
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| TWI656575B (en) * | 2014-09-03 | 2019-04-11 | 美商應用材料股份有限公司 | Nanocrystalline diamond carbon film for 3D NAND hard mask applications |
| US10246772B2 (en) * | 2015-04-01 | 2019-04-02 | Applied Materials, Inc. | Plasma enhanced chemical vapor deposition of films for improved vertical etch performance in 3D NAND memory devices |
| CN106941103A (en) * | 2016-01-04 | 2017-07-11 | 中芯国际集成电路制造(北京)有限公司 | The forming method of nand memory |
| US9991128B2 (en) * | 2016-02-05 | 2018-06-05 | Lam Research Corporation | Atomic layer etching in continuous plasma |
| CN106129010B (en) * | 2016-09-07 | 2019-01-22 | 武汉新芯集成电路制造有限公司 | A method of forming 3D nand flash memory |
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| CN1542923A (en) * | 2003-04-28 | 2004-11-03 | 台湾积体电路制造股份有限公司 | Method for making semiconductor structure |
| CN106935592A (en) * | 2015-12-31 | 2017-07-07 | 中芯国际集成电路制造(上海)有限公司 | The forming method of 3D nand flash memories |
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