CN106935592A - The forming method of 3D nand flash memories - Google Patents
The forming method of 3D nand flash memories Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
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Abstract
A kind of forming method of 3D nand flash memories, including：Semiconductor substrate is provided；Bottom composite bed is formed on a semiconductor substrate；Form the first groove through bottom composite bed thickness；After obturator layer is formed in the first groove, the top layer composite bed of covering obturator layer and bottom composite bed is formed；After forming through hole in top layer composite bed and bottom composite bed, gate dielectric layer and channel layer are formed in through-holes；Form the second insulating barrier of covering top layer composite bed, gate dielectric layer and channel layer；The second insulating barrier and top layer composite bed directly over removal obturator layer, form the second groove, then remove the obturator layer, expose the first groove；Afterwards, the second sacrifice layer in the first sacrifice layer and top layer composite bed in removal bottom composite bed, forms opening；After forming control gate in the opening, source cable architecture is formed in a groove.Methods described is avoided that the width of the first groove is too small, so as to avoid puncturing between control gate and source cable architecture.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of forming method of 3D nand flash memories.
Background technology
Flash memory (Flash Memory) is also called flash memory, the information for being mainly characterized by be kept for a long time in the case of not powered storage of flash memory, and have the advantages that integrated level is high, access speed is fast, be easy to wipe and rewrite, therefore the main flow memory as non-volatility memorizer.According to the difference of structure, flash memory is divided into not gate flash memory (NOR Flash Memory) and NAND gate flash memory (NAND Flash Memory).Can be provided and cell density high compared to NOR Flash Memory, NAND Flash Memory, can reach high storage density, and write and erasing speed also faster.
With the development of plane flash memory, the production technology of semiconductor achieves huge progress.But the development of current plane flash memory encounters various challenges：Physics limit, such as the exposure technique limit, the developing technique limit and the storage electron density limit.In this context, it is the production cost that solves the plane flash memory difficulty for running into and pursue lower unit storage unit, three-dimensional (3D) flash memory application and gives birth to, such as 3D nand flash memories.
The structural representation of existing 3D nand flash memories, with reference to Fig. 1, including：Semiconductor substrate 100；The control gate 110 of some layer stackups in Semiconductor substrate 100；First insulating barrier 120, between the control gate 110 of adjacent layer, between the control gate 110 of bottom and Semiconductor substrate 100, the surface of control gate 110 of top layer；Through the through hole (not shown) of the thickness of the insulating barrier 120 of the control gate 110 and first；Positioned at the substrate extension 101 of the via bottoms；Gate dielectric layer 130, the side wall of the through hole on substrate extension 101 and the part surface of substrate extension 101；Channel layer 140, in the through hole and positioned at the surface of gate dielectric layer 130；Raceway groove dielectric layer 150, wraps up in the through hole and by the channel layer 140；Second insulating barrier 160, the first insulating barrier 120 of covering, control gate 110, gate dielectric layer 130, channel layer 140 and raceway groove dielectric layer 150；Groove 170, through the thickness of second insulating barrier 160, the first insulating barrier 120 and control gate 110；Source line doped region 180, in the Semiconductor substrate 100 under the groove 170；Source cable architecture (not shown), the full groove 170 of filling；Positioned at some wordline connectors 111 on each surface of layer control gate 110；Positioned at some wordline 112 at the top of some wordline connectors 111；Bit line plugs 190, are connected through the thickness of the second insulating barrier 160 and with the channel layer 140；Some discrete bit lines 191, positioned at the top surface of some bit line plugs 190, and across the source cable architecture.
However, the performance of the 3D nand flash memories for being formed in the prior art has much room for improvement.
The content of the invention
The problem that the present invention is solved is to provide a kind of forming method of 3D nand flash memories, it is to avoid the width of the first groove is too small, so as to the phenomenon for avoiding puncturing between control gate and source cable architecture.
To solve the above problems, the present invention provides a kind of forming method of 3D nand flash memories, including：Semiconductor substrate is provided；Bottom composite bed is formed on the semiconductor substrate, if if the bottom composite bed includes the insulating sublayer of dried layer first layer of intersecting and the sacrifice layer of dried layer first, and the bottom of the bottom composite bed is the first insulating sublayer layer, the top layer of the bottom composite bed is the first sacrifice layer；The bottom composite bed is etched, the first groove through the bottom composite bed thickness is formed；After obturator layer is formed in first groove, form the top layer composite bed of the covering obturator layer and bottom composite bed, if if the top layer composite bed includes the insulating sublayer of dried layer second layer of intersecting and the sacrifice layer of dried layer second, and the bottom and top layer of the top layer composite bed are the second insulating sublayer layer；After forming through hole in the top layer composite bed and bottom composite bed, gate dielectric layer is formed in the through-hole side wall；Channel layer is formed in the through hole, the channel layer is located at the surface of the gate dielectric layer；Form the second insulating barrier of the covering top layer composite bed, gate dielectric layer and channel layer；The second insulating barrier and top layer composite bed directly over the obturator layer are removed, the second groove is formed；After forming the second groove, the obturator layer is removed, expose the first groove, the first groove and the second groove insertion constitute groove；After forming the groove, first sacrifice layer and the second sacrifice layer are removed, form opening；After forming control gate in said opening, source cable architecture is formed in the groove.
Optionally, the technique for etching the bottom composite bed is anisotropy dry carving technology.
Optionally, the material of the obturator layer is silica, silicon oxynitride or silicon oxide carbide.
Optionally, the method for the formation obturator layer is：In first groove obturator initiation layer is formed with the bottom composite bed top surface；Removal forms obturator layer higher than the obturator initiation layer of the bottom composite bed top surface.
Optionally, the material of second insulating barrier is silica, silicon oxynitride or silicon oxide carbide.
Optionally, the technique for removing the second insulating barrier directly over the obturator layer and top layer composite bed is anisotropy dry carving technology.
Optionally, the technique for removing the obturator layer is wet-etching technology.
Optionally, the parameter of the wet etching is：The etching solution for using is NH4With the mixed solution of HF, NH4Concentration of volume percent for 25%~60%, HF concentration of volume percent be 30%~60%, etching temperature be 20 degrees Celsius~30 degrees Celsius.
Optionally, the material of the first insulating sublayer layer and the second insulating sublayer layer is silica, silicon oxynitride or silicon oxide carbide.
Optionally, the material of first sacrifice layer and the second sacrifice layer is silicon nitride.
Optionally, the step of formation source cable architecture is：Source separation layer is formed in the side wall of the groove and bottom；The source conductive layer of the full groove of filling is formed in the source insulation surface, the source separation layer and the source conductive layer constitute source cable architecture.
Optionally, before forming the obturator layer, also include：Form the first protective layer positioned at the first recess sidewall and bottom；The second insulating barrier and top layer composite bed directly over the obturator layer and the first protective layer are removed, the second groove is formed；After forming second groove, also include：The second protective layer is formed in the second recess sidewall；After removing the obturator layer as mask with first protective layer and the second protective layer, first protective layer and the second protective layer are removed, expose the first groove.
Optionally, after forming second insulating barrier, also include：Sequentially form mask protection layer and patterned agraphitic carbon mask layer from down to up on second insulating barrier；Obturator layer described in the patterned agraphitic carbon mask layer as mask etching and the mask protection layer directly over the first protective layer, the second insulating barrier and top layer composite bed, form the second groove；The obturator layer is removed by mask of mask protection layer, the first protective layer and the second protective layer.
Compared with prior art, technical scheme has advantages below：
Due to before top layer composite bed is formed, the first groove is formd in the bottom composite bed, then obturator layer is formed in the first groove and occupies the position of the first groove to carry out follow-up step (including the step of formation top layer composite bed, through hole, gate dielectric layer, channel layer, second insulating barrier), after the completion for the treatment of above-mentioned steps, remove the second insulating barrier and top layer composite bed directly over the obturator layer, form the second groove, after control gate to be formed, source cable architecture is formed in first groove and the second groove.It can be seen that, only needed to before the top layer composite bed is formed, the bottom composite bed is performed etching can just form the first groove, without after top layer composite bed and the second insulating barrier is formed, the first groove that could be formed through bottom composite bed thickness being performed etching to the second insulating barrier, top layer composite bed and bottom composite bed.Because the thickness of bottom composite bed is smaller relative to the gross thickness of top layer composite bed, bottom composite bed and the second insulating barrier, the width of the first groove of formation in bottom composite bed can be avoided too small.First groove and the second groove insertion constitute groove, so that the present invention can avoid the bottom width of the groove too small, it is to avoid the phenomenon punctured between control gate and source cable architecture.
Brief description of the drawings
Fig. 1 is the structural representation of 3D nand flash memories in the prior art；
Fig. 2 to Fig. 4 is the structural representation of 3D nand flash memories forming process in the prior art；
Fig. 5 to Figure 28 is the structural representation of 3D nand flash memory forming processes in one embodiment of the invention.
Specific embodiment
As described in background, the 3D nand flash memory performances that prior art is formed have much room for improvement.
With reference to Fig. 1, the structural representation of Fig. 1 3D nand flash memories in the prior art.To form the 3D nand flash memories shown in Fig. 1, need to carry out following step in the prior art：
With reference to Fig. 2, there is provided Semiconductor substrate 100；Composite bed 122 is formed in the Semiconductor substrate 100, if if the composite bed 122 includes first insulating barrier of dried layer 120 and dried layer sacrifice layer 121 of intersecting, and the top layer and bottom of the composite bed 122 are the first insulating barrier 120；The through hole (not shown) through the thickness of the composite bed 122 is formed in the composite bed 122；Substrate extension 101 is formed in the via bottoms；After forming substrate extension 101, gate dielectric layer 130 is formed on the surface of the through-hole side wall and section substrate extension area 101, then channel layer 140 and raceway groove dielectric layer 150 are formed in the through hole, the channel layer 140 is located at the surface of gate dielectric layer 130, and the raceway groove dielectric layer 150 is wrapped up by the channel layer 140；Form the second insulating barrier 160 of the covering composite bed 122, gate dielectric layer 130, channel layer 140 and raceway groove dielectric layer 150；Form the groove 170 of the thickness through second insulating barrier 160 and the composite bed 122；The formation source line doped region 180 in the Semiconductor substrate 100 of the bottom of the groove 170.
With reference to Fig. 3, after forming source line doped region 180, the sacrifice layer 121 is removed, form opening 113.
With reference to Fig. 4, control gate 110 is formed in the opening 113；After forming control gate 110, the formation source cable architecture 190 in the groove 170 (referring to Fig. 3).
It is follow-up also to include (referring to Fig. 1)：Some wordline connectors 111 are formed on each surface of layer control gate 110；Wordline 112 is formed at the top of wordline connector 111；Form the bit line plugs 190 for running through the thickness of the second insulating barrier 160 and being connected with the channel layer 140；Some discrete bit lines 191 are formed, the bit line 191 is located at the top surface of some bit line plugs 190 and across the source cable architecture 190.
Research finds that in the 3D nand flash memories for being formed in the prior art, the bottom width of groove 170 is smaller, causes to be susceptible to puncture between the source cable architecture 190 in the control gate 110 and groove 170 that are located at around groove 170, and reason is：
Due to the gate dielectric layer 130, channel layer 140 and the raceway groove dielectric layer 150 that are initially formed in through hole and the through hole, then the second insulating barrier 160 is formed, re-form the source cable architecture 190 in the groove 170 and the groove 170 of second insulating barrier 160 and the thickness of composite bed 122, so that when groove 170 is formed, the gross thickness of the second insulating barrier 160 and composite bed 122 is thicker.Generally need to use anisotropy dry carving technology to etch the second insulating barrier 160 and composite bed 122 to form groove 170, during etching, with the increase of depth, the width of the groove 170 of formation can diminish.And because the gross thickness of second insulating barrier 160 and composite bed 110 is thicker, the depth-to-width ratio of groove 170 increases, the bottom width of the groove 170 for resulting in is too small, easily triggers the phenomenon punctured between the source cable architecture 190 in the control gate 110 and groove 170 of the both sides of groove 170.
On this basis, the present invention provides a kind of forming method of 3D nand flash memories, including：Semiconductor substrate is provided；Bottom composite bed is formed on the semiconductor substrate, if if the bottom composite bed includes the insulating sublayer of dried layer first layer of intersecting and the sacrifice layer of dried layer first, and the bottom of the bottom composite bed is the first insulating sublayer layer, the top layer of the bottom composite bed is the first sacrifice layer；The bottom composite bed is etched, the first groove through the bottom composite bed thickness is formed；After obturator layer is formed in first groove, form the top layer composite bed of the covering obturator layer and bottom composite bed, if if the top layer composite bed includes the insulating sublayer of dried layer second layer of intersecting and the sacrifice layer of dried layer second, and the bottom and top layer of the top layer composite bed are the second insulating sublayer layer；After forming through hole in the top layer composite bed and bottom composite bed, gate dielectric layer is formed in the through-hole side wall；Channel layer is formed in the through hole, the channel layer is located at the surface of the gate dielectric layer；Form the second insulating barrier of the covering top layer composite bed, gate dielectric layer and channel layer；The second insulating barrier and top layer composite bed directly over the obturator layer are removed, the second groove is formed；After forming the second groove, the obturator layer is removed, expose the first groove, the first groove and the second groove insertion constitute groove；After forming the groove, first sacrifice layer and the second sacrifice layer are removed, form opening；After forming control gate in said opening, source cable architecture is formed in the groove.The present invention can avoid the width of first groove too small, so as to the phenomenon punctured between avoiding the control gate that is subsequently formed and source cable architecture.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, specific embodiment of the invention is described in detail below in conjunction with the accompanying drawings.
Fig. 5 to Figure 28 is the structural representation of 3D nand flash memory forming processes in one embodiment of the invention.
With reference to Fig. 5, there is provided Semiconductor substrate 200；Bottom composite bed 210 is formed in the Semiconductor substrate 200.
The Semiconductor substrate 200 can be monocrystalline silicon, polysilicon or non-crystalline silicon；The Semiconductor substrate 200 can also be the semi-conducting materials such as silicon, germanium, SiGe, GaAs, no longer illustrate one by one.In the present embodiment, the Semiconductor substrate 200 is silicon.
If if the bottom composite bed 210 includes the insulating sublayer of dried layer first layer 211 of intersecting and the first sacrifice layer of dried layer 212, and the bottom of the bottom composite bed 210 is the first insulating sublayer layer 211, the top layer of the bottom composite bed 210 is the first sacrifice layer 212.In actual process, can as needed select the specific number of plies of the first insulating sublayer layer 211 and the first sacrifice layer 212, Fig. 4 it is merely illustrative go out 3 layer of first insulating sublayer, 211 and 3 layer of first sacrifice layer 212 of layer.
In the bottom composite bed 210, first sacrifice layer 212 is used to be planted oneself for the part control gate being subsequently formed, subsequently remove first sacrifice layer 212, and forming part control gate in the position left after the first sacrifice layer 212 of removal, in order to aspect is illustrated, the control gate for subsequently being formed in the position left after removing the first sacrifice layer 212 is referred to as the first control gate.The first insulating sublayer layer 211 is located between the first sacrifice layer 212 of adjacent two layers and between the first sacrifice layer 212 and Semiconductor substrate 200, after the position of follow-up first sacrifice layer 212 is replaced by the first control gate, so that the first insulating sublayer layer 211 is used between the first control gate of adjacent layer, electric isolation, and the control gate of electric isolation first and gate dielectric layer, the channel layer being subsequently formed is carried out between the first control gate and Semiconductor substrate 200.
The first insulating sublayer layer 211 is different with the material of the first sacrifice layer 212, make during the first sacrifice layer 212 of follow-up removal, first sacrifice layer 212 has etching selection ratio higher relative to the first insulating sublayer layer 211, so as to the pattern for ensureing the first insulating sublayer layer 211 is good, accurate size, so that the pattern of the first control gate being subsequently formed is good, accurate size.Additionally, first sacrifice layer 212 needs the material that selection is easily removed.The material of the first insulating sublayer layer 211 is silica, silicon oxynitride or silicon oxide carbide；In the present embodiment, the material of the first insulating sublayer layer 211 is silica；The material of first sacrifice layer 212 is silicon nitride.
After forming the bottom composite bed 210, the bottom composite bed 210 is etched, form the first groove through the thickness of bottom composite bed 210.
The technique for etching the bottom composite bed 210 is anisotropy dry carving technology, such as anisotropic plasma etch technique or reactive ion etching process, specifically, with reference to Fig. 6, patterned mask layer 220 is formed on the bottom composite bed 210, the patterned mask layer 220 defines the position of the first groove 220；With reference to Fig. 7, with the patterned mask layer 220 as mask etching described in bottom composite bed 210 until expose the surface of the Semiconductor substrate 200, form the first groove 230 through the thickness of bottom composite bed 210；Then, with reference to Fig. 8, the patterned mask layer 220 is removed.
It should be noted that, the material of patterned mask layer 220 is different from the material of first insulating sublayer layer 211 and the first sacrifice layer 212, so that during etching bottom composite bed 210 is to form the first groove 230, the first insulating sublayer layer 211 has etching selection ratio higher relative to patterned mask layer 220, and first sacrifice layer 212 relative to the patterned mask layer 220 have etching selection ratio higher, enable to the figure of the patterned mask layer 220 relatively stable.In addition, being needed using the larger material of physical strength in the patterned mask layer 220, to avoid during etching bottom composite bed 210, the patterned mask layer 220 is completely removed.In the present embodiment, the material of the patterned mask layer 220 is amorphous carbon.
With reference to Fig. 9, Fig. 9 is the top view of corresponding diagram 8, and show the first groove 230 is shaped as strip.
With reference to Figure 10, Figure 10 is the schematic diagram formed on the basis of Fig. 8, and obturator layer 240 is formed in first groove 230.
The material of the obturator layer 240 is silica, silicon oxynitride or silicon oxide carbide.
The method for forming obturator layer 240 is：In first groove 230 obturator initiation layer (not shown) is formed with the top surface of bottom composite bed 210, the technique of the obturator initiation layer is formed for depositing operation, such as fluid chemistry vapour deposition (FCVD) technique or sub-atmospheric pressure chemical vapor deposition (SACVD) technique；Using flatening process, such as chemical mechanical milling tech or dry carving technology, removal forms obturator layer 240 higher than the obturator initiation layer of the top surface of bottom composite bed 210, and the obturator layer 240 is flushed with the top surface of the bottom composite bed 210.
In the present embodiment, before forming the obturator layer 240, also include：Form the first protective layer 241 positioned at the side wall of the first groove 230 and bottom; so that follow-up during removal obturator layer 240; first protective layer 241 can protect the first insulating sublayer layer 211 and the first sacrifice layer 212 of obturator 240 side wall of layer not to be subject to etching injury, especially protect the first insulating sublayer layer 211 of obturator 240 side wall of layer.Specifically, the top surface using depositing operation in the side wall of first groove 230 and bottom and the bottom composite bed 210 forms the first protective layer material layer (not shown)；The obturator initiation layer of full first groove 230 of filling is formed in the first protective layer material layer surface；Then removal is higher than the first protective layer material layer and obturator initiation layer of the top surface of bottom composite bed 210; the first protective layer 241 and obturator layer 240 are formed in the first groove 230, the obturator layer 240 is flushed with the top surface of the bottom composite bed 210.The material of first protective layer 241 is silicon nitride.
With reference to Figure 11, the top layer composite bed 250 of the covering obturator layer 240 and bottom composite bed 210 is formed.
If if the top layer composite bed 250 includes the insulating sublayer of dried layer second layer 251 of intersecting and the second sacrifice layer of dried layer 252, and the bottom and top layer of the top layer composite bed 250 are the second insulating sublayer layer 251.In actual process, can as needed select the specific number of plies of the second insulating sublayer layer 251 and the second sacrifice layer 252, Figure 10 it is merely illustrative go out 4 layer of second insulating sublayer, 251 and 3 layer of second sacrifice layer 252 of layer.
In the present embodiment, the top layer composite bed 250 is also covered with the first protective layer 241.
In the top layer composite bed 250, second sacrifice layer 252 is used to be planted oneself for the part control gate being subsequently formed, subsequently remove second sacrifice layer 252, and forming part control gate in the position left after the second sacrifice layer 252 of removal, in order to aspect is illustrated, the control gate for subsequently being formed in the position left after removing the second sacrifice layer 252 is referred to as the second control gate.The second insulating sublayer layer 251 is between the second sacrifice layer 252 of adjacent two layers, between the second sacrifice layer 252 and bottom composite bed 210 and on the second sacrifice layer 252 of top layer, after the position of follow-up second sacrifice layer 252 is replaced by the second control gate so that the second insulating sublayer layer 251 is used to carry out electric isolation between the second control gate of adjacent layer, between the second control gate and bottom composite bed 210 and the control gate of electric isolation second and the gate dielectric layer, the channel layer that are subsequently formed.
The second insulating sublayer layer 251 is different with the material of the second sacrifice layer 252, make during the second sacrifice layer 252 of follow-up removal, second sacrifice layer 252 has etching selection ratio higher relative to second insulating sublayer layer 251, so as to the pattern for ensureing the second insulating sublayer layer 251 is good, accurate size, so that the pattern of the second control gate being subsequently formed is good, accurate size.Additionally, second sacrifice layer 252 needs the material that selection is easily removed.The material of the second insulating sublayer layer 251 is silica, silicon oxynitride or silicon oxide carbide；In the present embodiment, the material of the second insulating sublayer layer 251 is silica.The material of second sacrifice layer 252 is silicon nitride.
First insulating sublayer layer 211 and the second insulating sublayer layer 251 constitute the first insulating barrier.
Then, it is necessary to form gate dielectric layer and channel layer in the top layer composite bed 250 and bottom composite bed 210.Figure 12 to Figure 20 is the structural representation of gate dielectric layer and raceway groove layer formation process.
With reference to Figure 12, Figure 12 is that schematic diagram is formed on the basis of Figure 11, etches the top layer composite bed 250 and bottom composite bed 210, forms the through hole 260 through the top layer composite bed 250 and the thickness of bottom composite bed 210.
Before through hole 260 is formed, need to form the patterned mask layer (not shown) for defining the position of through hole 260, its material is agraphitic carbon, then with the patterned mask layer etching top layer composite bed 250 and bottom composite bed 210, specifically, the top layer composite bed 250 and bottom composite bed 210 are etched using anisotropy dry carving technology until exposing the surface of Semiconductor substrate 200, through hole 260 is formed, then removal defines the patterned mask layer of the position of through hole 260.
With reference to Figure 13, Figure 13 is the top view of corresponding diagram 12, show shape and the position of through hole 260, the through hole 260 is shaped as cylindrical, the through hole 260 along the first groove 230 the discrete arrangement of bearing of trend, in the present embodiment, 4 through holes 260 are respectively formed along each column of the bearing of trend of the first groove 230, only as an example.In other embodiments, can be needed to set the quantity of through hole 260 according to technique.
With reference to Figure 14, Figure 14 is the schematic diagram formed on the basis of Figure 12, and substrate extension 270 is formed in the bottom of the through hole 260；After forming substrate extension 270, gate dielectric layer 280 is formed in the top surface of the bottom of the through hole 260 and side wall and top layer composite bed 250.
The material of the substrate extension 270 is identical with the material of Semiconductor substrate 200.The technique for forming substrate extension 270 is selective epitaxial growth process.Substrate extension 270 act as improve electron mobility.
In the present embodiment; the gate dielectric layer 280 includes the top dielectric layer (not shown), capture charge layer (not shown), tunneling medium layer (not shown) and the protective layer (not shown) that are sequentially depositing, and the structure that the top dielectric layer, capture charge layer, tunneling medium layer and protective layer are constituted is referred to as ONON structure sheafs.In the bottom of through hole 260 and the top surface of top layer composite bed 250; top dielectric layer, capture charge layer, tunneling medium layer and protective layer are stacked gradually from down to up; in the side wall of through hole 260, top dielectric layer, capture charge layer, tunneling medium layer and protective layer ecto-entad are stacked gradually.
The material of the tunneling medium layer and top dielectric layer is silica；The material of the capture charge layer and protective layer is silicon nitride.In the present embodiment, in order that the thickness for obtaining the top dielectric layer of the side wall of through hole 260, capture charge layer, tunneling medium layer and protective layer is uniform, pattern is good, selection formation top dielectric layer, capture charge layer, tunneling medium layer and protective layer in boiler tube.In other embodiments, it would however also be possible to employ depositing operation is formed, such as atom layer deposition process.
It should be noted that; in other embodiments; gate dielectric layer 280 can be ONO structure layer; i.e. gate dielectric layer 280 only includes top dielectric layer, capture charge layer and tunneling medium layer; do not include protective layer; the material of top dielectric layer, capture charge layer and tunneling medium layer composition ONO structure layer, top dielectric layer and tunneling medium layer is silica, and the material for capturing charge layer is silicon nitride.
Compared to ONO structure layer, the formation of ONON structure sheafs can increase the life-span of 3D nand flash memories.
With reference to Figure 15, the first channel layer 290 is formed on 280 surface of gate dielectric material layer.
The material of first channel layer 290 is polysilicon.The first channel layer 290 is formed in boiler tube.First channel layer 290 act as：The channel layer 290 of gate dielectric layer 280 and first of the bottom of subsequent etching through hole 260 is so that during the top surface for exposing substrate extension 270, the first channel layer 290 can protect the gate dielectric layer 280 of the side wall of through hole 260 not to be subject to etching injury.
With reference to Figure 16, first channel layer 290 and gate dielectric layer 280 are etched back to, the channel layer 290 of gate dielectric layer 280 and first of the bottom of through hole 260 is cut through and exposes the top surface of substrate extension 270.
During first channel layer 290 and gate dielectric layer 280 is etched back to, also the first channel layer 290 of the top surface of top layer composite bed 250 is removed with gate dielectric layer 280.
It should be noted that; during first channel layer 290 and gate dielectric layer 280 is etched back to; first channel layer 290 of the side wall of through hole 260 protects the gate dielectric layer 280 of the side wall of through hole 260 not to be subject to etching injury; although and the thickness of the first channel layer 290 of the side wall of through hole 260 has reduced; do not interfere with to form total channel region; because follow-up will also form the second channel layer, the second channel layer can make up the thickness of the reduction of the first channel layer 290.
Then, with reference to Figure 17, the second channel layer 300 is formed in the top surface of the side wall of the first channel layer 290, (the referring to Figure 16) bottom of through hole 260 and top layer composite bed 250, the raceway groove dielectric layer 310 of the full through hole 260 of filling is then formed on the surface of the second channel layer 300.
The material of second channel layer 300 is polysilicon.The second channel layer 300 is formed in boiler tube.
The material of raceway groove dielectric layer 310 is silica.The technique for forming raceway groove dielectric layer 310 is depositing operation, such as plasma activated chemical vapour deposition technique, atom layer deposition process, low-pressure chemical vapor deposition process or sub- aumospheric pressure cvd technique.Or, raceway groove dielectric layer 310 is formed in boiler tube.
With reference to Figure 18, raceway groove dielectric layer 310, the raceway groove dielectric layer 310 on removal top layer composite bed 250 are etched back to, and remove the raceway groove dielectric layer 310 of Partial Height in through hole 260, form depression 320.
With reference to Figure 19, in 320 (referring to Figure 18) of the depression and the surface of the second channel layer 300 forms triple channel layer 330.
The material of the triple channel layer 330 is polysilicon, and triple channel layer 330 is formed in boiler tube.
With reference to Figure 20, the triple channel layer 330 and the second channel layer 300 are planarized until exposing the top surface of top layer composite bed 250.
The technique of the triple channel layer 330 and the second channel layer 300 is planarized for mechanical-chemistry grinding technique or technique is etched back to.
After planarizing the triple channel layer 330 and the second channel layer 300, triple channel the 330, second channel layer 300 of layer and the constituting channel of the first channel layer 290 layer, then to carrying out ion implanting at the top of the channel layer, make the top of the channel layer doped with ion, so as to form drain region (not shown) at the top of the channel layer.
It should be noted that in the present embodiment, yet forms both raceway groove dielectric layer 310, it is therefore intended that：So that the thinner thickness of the second channel layer 300, the thickness of the second channel layer 300 is smaller, and the thickness of the second channel layer 300 can be broken up the crystal grain that the second channel layer 300 will be formed not as good as a size for crystal grain so that threshold voltage distribution band is narrower.In other embodiments, raceway groove dielectric layer 310 can not be formed.
Now, the step of forming gate dielectric layer 280 and channel layer has been implemented.
Then, with reference to Figure 21, the second insulating barrier 340 of the covering top layer composite bed 250, gate dielectric layer 280 and channel layer is formed.
The material of second insulating barrier 340 is silica, silicon oxynitride or silicon oxide carbide.The technique of second insulating barrier 340 is formed for depositing operation, such as plasma activated chemical vapour deposition technique, atom layer deposition process, low-pressure chemical vapor deposition process or sub- aumospheric pressure cvd technique.
In the present embodiment, the second insulating barrier 340 also covers raceway groove dielectric layer 310.
Formed after the second insulating barrier 340, it is necessary to remove the second insulating barrier 340 and top layer composite bed 250 directly over the obturator layer 240, form the second groove.
In the present embodiment, including：The second insulating barrier 340 and top layer composite bed 250 directly over the obturator layer 240 and the first protective layer 241 are removed, the second groove is formed.
Figure 22 to Figure 23 is second insulating barrier 340 and the specific steps of top layer composite bed 250 of the removal obturator layer 240 and the surface of the first protective layer 241.
With reference to Figure 22, mask protection layer 350, agraphitic carbon mask layer 351, bottom anti-reflection layer 352 and patterned photoresist layer 353 are sequentially formed from down to up on second insulating barrier 340.
The patterned photoresist layer 353 defines the position of the second groove to be formed.
The bottom anti-reflection layer 352 causes that the figure pattern of the patterned photoresist layer 353 for being formed is good.The bottom anti-reflection layer 352 is nonessential layer.
Agraphitic carbon mask layer 351 and second insulating sublayer layer 251, second sacrifice layer 252, first insulating sublayer layer 211 is different with the material of the first sacrifice layer 212, so that during second insulating barrier 340 and top layer composite bed 250 of subsequent etching removal obturator layer 240 and the surface of the first protective layer 241, second insulating sublayer layer 251, second sacrifice layer 252, first insulating sublayer layer 211 and the first sacrifice layer 212 have etching selection ratio higher with agraphitic carbon mask layer 351, after enabling to graphical agraphitic carbon mask layer 351, the figure of the patterned agraphitic carbon mask layer 351 for being formed is relatively stable.In addition; the physical strength of agraphitic carbon mask layer 351 is larger; during the second insulating barrier 340 and top layer composite bed 250 directly over etching removal obturator layer 240 and the first protective layer 241 can be avoided, patterned agraphitic carbon mask layer 351 is too early to be depleted.
The material of the mask protection layer 350 is silicon nitride.It is depositing operation to form 350 technique of the mask protection layer.
In the present embodiment, the mask protection layer 350 is formd, it act as：(1) follow-up that mask protection layer 350 is graphical, mask protection layer 350 is used as the second insulating barrier 340 and a part for the mask of top layer composite bed 250 directly over etching removal obturator layer 240 and the first protective layer 241；(2) after second insulating barrier 340 and top layer composite bed 250 of subsequent etching removal obturator layer 240 and the surface of the first protective layer 241, the mask protection layer 350 can be retained；During follow-up removal packed layer 240, the mask protection layer 350 can protect the top surface of the second insulating barrier 340 not to be subject to etching injury, it is to avoid expose gate dielectric layer 280 and channel layer.In other embodiments, it is also possible to do not form the mask protection layer 350, during follow-up removal packed layer 240, the second insulating barrier 340 of segment thickness can be lost.
With reference to Figure 23, with the patterned photoresist layer 353 (referring to Figure 22) as mask etching described in bottom anti-reflection layer 352 and agraphitic carbon mask layer 351, form patterned bottom anti-reflection layer 352 and patterned agraphitic carbon mask layer 351；Then with the patterned agraphitic carbon mask layer 351 as mask etching described in mask protection the 350, second insulating barrier 340 of layer and top layer composite bed 250 directly over obturator layer 240 and the first protective layer 241, form the second groove 360.
Specifically; the technique of mask protection the 350, second insulating barrier 340 of layer and top layer composite bed 250 directly over the etching obturator layer 240 and the first protective layer 241 is anisotropy dry carving technology, such as anisotropic plasma etch technique or reactive ion etching process.
In the present embodiment; during mask protection the 350, second insulating barrier 340 of layer and top layer composite bed 250 directly over etching removal obturator layer 240 and the first protective layer 241, the patterned photoresist layer 353, patterned agraphitic carbon mask layer 351 and patterned bottom anti-reflection layer 352 can be depleted.In other embodiments; after mask protection 350, second insulating barrier 340 of layer and top layer composite bed 250 of etching removal obturator layer 240 and the surface of the first protective layer 241; the agraphitic carbon mask layer 351 of segment thickness is there remains, now needs to remove remaining agraphitic carbon mask layer 351.
It should be noted that; when without the first protective layer 241 is formed; only need to the patterned agraphitic carbon mask layer 351 as mask etching described in mask protection layer the 350, second insulating barrier 340 and top layer composite bed 250 directly over obturator layer 240, form the second groove 360；When without formed the first protective layer 241 and mask protection layer 350 when, it is only necessary to the patterned agraphitic carbon mask layer 351 as mask etching described in obturator layer 240 surface the second insulating barrier 340 and top layer composite bed 250.
With reference to Figure 24, the second protective layer 370 is formed in the side wall of second groove 360.
The material of second protective layer 370 is silicon nitride.Second protective layer 370 act as：During follow-up removal obturator layer 240, the second insulating sublayer 251, second sacrifice layer 252 of layer and the second insulating barrier 340 of the side wall of the second groove 360 is protected not to be subject to etching injury.
Specifically; the second protected material bed of material (not shown) is formed in the side wall of second groove 360 and bottom and mask protection 350 top surface of layer; then the second protected material bed of material of the bottom of the second groove 360 and mask protection 350 top surface of layer is removed, so as to form the second protective layer 370 in the side wall of second groove 360.The technique for forming the second protected material bed of material can be depositing operation；In the present embodiment, using forming the second protected material bed of material in pipe furnace so that the pattern of the second protected material bed of material of the side wall of the second groove 360 is good, the second protective layer 370 of uniform thickness can be formed in the side wall of the second groove 360.In other embodiments, it is also possible to do not form the second protective layer 370.
Then, with reference to Figure 25,240 (referring to Figure 23) of the obturator layer are removed.
In the present embodiment; remove obturator layer 240 and be with the mask protection the 350, first protective layer 241 of layer and the second protective layer 370 as mask in the presence of removal; during the obturator layer 240 is removed, mask protection the 350, first protective layer 241 of layer and the second insulating barrier 340 of common protection of the second protective layer 370, the 251, second sacrifice layer 252 of the second insulating sublayer layer, the first insulating sublayer layer 211 and the first sacrifice layer 212 are not subject to etching injury.
Preferably; before removal obturator layer 240; the thickness of mask protection layer 350 more than first the second protective layer 370 of protection thickness, and mask protection layer 350 thickness of the thickness more than the first protective layer 241, further increase the protection to the top surface of the second insulating barrier 340.
Specifically, the technique for removing the obturator layer 240 is wet-etching technology, the etching solution for using is NH4With the mixed solution of HF, NH4Concentration of volume percent be 25%~60%, such as 25%, 40%, the concentration of volume percent of 60%, HF be 30%~60%, such as 30%, 49%, 60%, etching temperature is 20 degrees Celsius~30 degrees Celsius.
Then, with reference to Figure 26, the protective layer 370 of the first protective layer 241 and second is removed；After removing the protective layer 370 of first protective layer 241 and second, the second sacrifice layer 252 and the first sacrifice layer 212 are removed.
After removing the first protective layer 241 and the second protective layer 370, the first groove 230 is exposed, the first groove 230 and the insertion of the second groove 360 constitute groove；After removing the second sacrifice layer 252 and the first sacrifice layer 212, opening 380 is formed in the position of the second sacrifice layer 252 and the first sacrifice layer 212.
It should be noted that during the first protective layer 241, the second protective layer 370, the second sacrifice layer 252 and the first sacrifice layer 212 is removed, mask protection layer 350 is also removed.
Specifically; in the present embodiment; for Simplified flowsheet; the first protective layer 241, the second protective layer 370, the second sacrifice layer 252, the first sacrifice layer 212 and mask protection layer 350 is removed in one step; the etching solution for using is phosphoric acid solution; the concentration of phosphoric acid is 85%~90%, and temperature is 120 degrees Celsius~200 degrees Celsius.
It should be noted that after exposing the first groove 230, source line doped region (not shown) is formed also in the Semiconductor substrate 200 of the bottom portion of groove, the second sacrifice layer 252 and the first sacrifice layer 212 are then removed again.
With reference to Figure 27, control gate 390 is formed in 380 (referring to Figure 26) of the opening.
The material of the control gate 390 is metal, such as tungsten.
The technique of the control gate 390 is formed for depositing operation, such as chemical vapor deposition method.
In the present embodiment, before control gate 390 is formed, the side wall ecto-entad also in the opening 380 forms control gate spacer (not shown) and barrier layer (not shown).The material for controlling gate spacer is silica；The material on the barrier layer is titanium nitride.
It should be noted that, if during control gate 390 is formed, the material of control gate 390 is also form in the first groove 230 and the second groove 360, the material of the control gate 390 in the first groove 230 and the second groove 360 can be removed using anisotropic etch process.
With reference to Figure 28, after forming control gate 390, source separation layer 400 is formed in the side wall of the groove 360 of first groove 230 and second and bottom；The source conductive layer 410 of the full groove 360 of first groove 230 and second of filling is formed on the surface of source separation layer 400.
Specifically, the step of forming the source separation layer 400 and source conductive layer 410 is：Using depositing operation, source separation layer 400 is formed in the side wall of the groove 360 of first groove 230 and second and the top surface of bottom and second insulating barrier 340；Using depositing operation, the source conductive layer 410 of the full groove 360 of first groove 230 and second of filling is formed on the surface of the source separation layer 400；Then removal is higher than the source separation layer 400 and source conductive layer 410 of the top surface of the second insulating barrier 340.The material of the source separation layer 400 is silica, silicon oxynitride or silicon oxide carbide, and the material of the source conductive layer 410 can be tungsten.
The source separation layer 400 and the source conductive layer 410 constitute source cable architecture.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, without departing from the spirit and scope of the present invention, can be made various changes or modifications, therefore protection scope of the present invention should be defined by claim limited range.
Claims (13)
1. a kind of forming method of 3D nand flash memories, it is characterised in that including：
Semiconductor substrate is provided；
Bottom composite bed is formed on the semiconductor substrate, if the bottom composite bed includes intersecting
If the insulating sublayer of dried layer first layer and the sacrifice layer of dried layer first, and the bottom of the bottom composite bed is first
Insulating sublayer layer, the top layer of the bottom composite bed is the first sacrifice layer；
The bottom composite bed is etched, the first groove through the bottom composite bed thickness is formed；
After obturator layer is formed in first groove, the covering obturator layer and bottom composite bed are formed
Top layer composite bed, if if the insulating sublayer of dried layer second layer of the top layer composite bed including intersecting and
The sacrifice layer of dried layer second, and the bottom and top layer of the top layer composite bed are the second insulating sublayer layer；
After forming through hole in the top layer composite bed and bottom composite bed, form grid in the through-hole side wall and be situated between
Matter layer；
Channel layer is formed in the through hole, the channel layer is located at the surface of the gate dielectric layer；
Form the second insulating barrier of the covering top layer composite bed, gate dielectric layer and channel layer；
The second insulating barrier and top layer composite bed directly over the obturator layer are removed, the second groove is formed；
After forming the second groove, the obturator layer is removed, expose the first groove, the first groove and second
Groove insertion constitutes groove；
After forming the groove, first sacrifice layer and the second sacrifice layer are removed, form opening；
After forming control gate in said opening, source cable architecture is formed in the groove.
2. the forming method of 3D nand flash memories according to claim 1, it is characterised in that etching institute
The technique for stating bottom composite bed is anisotropy dry carving technology.
3. the forming method of 3D nand flash memories according to claim 1, it is characterised in that described to fill out
The material for filling body layer is silica, silicon oxynitride or silicon oxide carbide.
4. the forming method of 3D nand flash memories according to claim 1, it is characterised in that form institute
State obturator layer method be：Formed with the bottom composite bed top surface in first groove
Obturator initiation layer；Removal is formed higher than the obturator initiation layer of the bottom composite bed top surface
Obturator layer.
5. the forming method of 3D nand flash memories according to claim 1, it is characterised in that described
The material of two insulating barriers is silica, silicon oxynitride or silicon oxide carbide.
6. the forming method of 3D nand flash memories according to claim 1, it is characterised in that removal institute
The technique for stating the second insulating barrier directly over obturator layer and top layer composite bed is anisotropy dry etching work
Skill.
7. the forming method of 3D nand flash memories according to claim 1, it is characterised in that removal institute
The technique for stating obturator layer is wet-etching technology.
8. the forming method of 3D nand flash memories according to claim 7, it is characterised in that described wet
Method etching parameter be：The etching solution for using is NH4With the mixed solution of HF, NH4Volume
Percent concentration is 30%~60% for the concentration of volume percent of 25%~60%, HF, and etching temperature is
20 degrees Celsius~30 degrees Celsius.
9. the forming method of 3D nand flash memories according to claim 1, it is characterised in that described
The material of one insulating sublayer layer and the second insulating sublayer layer is silica, silicon oxynitride or silicon oxide carbide.
10. the forming method of 3D nand flash memories according to claim 1, it is characterised in that described
The material of one sacrifice layer and the second sacrifice layer is silicon nitride.
The forming method of 11. 3D nand flash memories according to claim 1, it is characterised in that form institute
The step of stating source cable architecture be：
Source separation layer is formed in the side wall of the groove and bottom；
The source conductive layer of the full groove of filling, the source separation layer and institute are formed in the source insulation surface
State source conductive layer and constitute source cable architecture.
The forming method of 12. 3D nand flash memories according to claim 1, it is characterised in that form institute
Before stating obturator layer, also include：
Form the first protective layer positioned at the first recess sidewall and bottom；
The second insulating barrier and top layer composite bed directly over the obturator layer and the first protective layer are removed, is formed
Second groove；
After forming second groove, also include：The second protective layer is formed in the second recess sidewall；
After removing the obturator layer as mask with first protective layer and the second protective layer, described the is removed
One protective layer and the second protective layer, expose the first groove.
The forming method of 13. 3D nand flash memories according to claim 12, it is characterised in that form institute
After stating the second insulating barrier, also include：
Sequentially form mask protection layer from down to up on second insulating barrier and patterned agraphitic carbon is covered
Film layer；
Obturator layer and the first protective layer described in the patterned agraphitic carbon mask layer as mask etching are just
The mask protection layer of top, the second insulating barrier and top layer composite bed, form the second groove；Covered with described
Film protective layer, the first protective layer and the second protective layer are that mask removes the obturator layer.
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