CN109148467A - 3D-NAND flash memory - Google Patents
3D-NAND flash memory Download PDFInfo
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- CN109148467A CN109148467A CN201811037782.0A CN201811037782A CN109148467A CN 109148467 A CN109148467 A CN 109148467A CN 201811037782 A CN201811037782 A CN 201811037782A CN 109148467 A CN109148467 A CN 109148467A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
- H01L29/7926—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
Abstract
A kind of 3D-NAND flash memory, comprising: semiconductor substrate；Stacked structure in the semiconductor substrate, the stacked structure include several layer insulatings and several layers conductive layer of intersecting；Through the channel structure of the stacked structure, the channel structure includes high-K gate dielectric layer and channel sacrificial layer, the high-K gate dielectric layer is continuously distributed on the direction perpendicular to semiconductor substrate, channel sacrificial layer is between the high-K gate dielectric layer and the insulating layer, and channel sacrificial layer is separated in the direction perpendicular to the semiconductor substrate by the conductive layer.The performance of the 3D-NAND flash memory is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of 3D-NAND flash memories.
Background technique
Flash memory (Flash Memory) is also known as flash memory, and flash memory is mainly characterized by energy in the case where not powered
The long-term information for keeping storage, and have many advantages, such as that integrated level is high, access speed is fast, be easy to wipe and rewrite, therefore become non-
The mainstream memory of volatile storage.According to the difference of structure, flash memory be divided into NOT gate flash memory (NOR Flash Memory) and
NAND gate flash memory (NAND Flash Memory).Can be provided compared to NOR Flash Memory, NAND Flash Memory and
High cell density, can achieve high storage density, and be written and the speed of erasing also faster.
With the development of plane flash memory, the production technology of semiconductor achieves huge progress.But current plane
The development of flash memory encounters various challenges: physics limit, such as the exposure technique limit, the developing technique limit and storage electron density pole
Limit etc..In this context, to solve the difficulty that encounters of plane flash memory and pursue being produced into for lower unit storage unit
This, three-dimensional (3D) flash memory is applied and is given birth to, such as 3D-NAND flash memory.
However, the performance of the 3D-NAND flash memory formed in the prior art is to be improved.
Summary of the invention
Problems solved by the invention is to provide a kind of 3D-NAND flash memory, to improve the performance of 3D-NAND flash memory.
To solve the above problems, the present invention provides a kind of 3D-NAND flash memory, comprising: semiconductor substrate；It is partly led positioned at described
Stacked structure in body substrate, the stacked structure include several layer insulatings and several layers conductive layer of intersecting；Run through
The channel structure of the stacked structure, the channel structure include high-K gate dielectric layer and channel sacrificial layer, the high-K gate dielectric
Layer is continuously distributed on the direction perpendicular to semiconductor substrate, and channel sacrificial layer is located at the high-K gate dielectric layer and the insulation
Between layer, and channel sacrificial layer is separated in the direction perpendicular to the semiconductor substrate by the conductive layer.
Optionally, the material of the channel sacrificial layer is different with the material of the high-K gate dielectric layer；The channel sacrificial layer
Material be silica, silicon oxynitride, silicon oxide carbide or high K dielectric material.
Optionally, the overall thickness of the channel sacrificial layer and the high-K gate dielectric layer is first size；The channel structure
Corresponding diameter is the second size at the position with channel sacrificial layer and high-K gate dielectric layer, and first size is the second size
2%~30%.
Optionally, described second having a size of 50 nanometers~500 nanometers；The channel sacrificial layer with a thickness of 1 nanometer~50
Nanometer, the high-K gate dielectric layer with a thickness of 1 nanometer~50 nanometers.
Optionally, the channel structure further includes channel composite layer, and the channel composite layer is located at the high-K gate dielectric layer
Surface, and the high-K gate dielectric layer is between the channel sacrificial layer and the channel composite layer.
Optionally, the channel composite layer includes being located at the intrinsic gate dielectric layer of the high-K gate dielectric layer surface and being located at
The channel layer on the intrinsic gate dielectric layer surface；The intrinsic gate dielectric layer includes block media layer, capture charge layer and tunnelling
Dielectric layer, the block media layer, capture charge layer and tunneling medium layer are perpendicular to channel structure side wall and from channel structure
Outside to stacking gradually on the direction in channel structure.
Optionally, further includes: the substrate extended layer between the channel structure and the semiconductor substrate.
Optionally, the channel sacrificial layer is also located at the part of the surface of the substrate extended layer；Substrate extended layer portion
The channel sacrificial layer on point surface connects and L-shaped with the channel sacrificial layer of channel structure side bottom.
Compared with prior art, technical solution of the present invention has the advantage that
In the 3D-NAND flash memory that technical solution of the present invention provides, the channel structure includes that channel sacrificial layer and high K grid are situated between
Matter layer.The high-K gate dielectric layer is not necessarily to occupy the space between adjacent insulating layer.The channel sacrificial layer is perpendicular to described half
Separated on the direction of conductor substrate by the conductive layer, i.e., the described conductive layer edge extends between the channel sacrificial layer of adjacent layer.
Therefore, in the case that diameter of the channel structure at the position with channel sacrificial layer and high-K gate dielectric layer is certain, energy
Enough so that conductive layer is larger in the size of transverse direction.Make to sufficiently grow conducive to conductive layer longitudinally in this way, conductive layer is sealing
Gap is less prone at mouthful.To sum up, the performance of 3D-NAND flash memory is improved.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of 3D-NAND flash memory；
Fig. 2 to Figure 24 is the structural schematic diagram of 3D-NAND flash memory forming process in one embodiment of the invention.
Specific embodiment
As described in background, the performance for the 3D-NAND flash memory that the prior art is formed is to be improved.
A kind of 3D-NAND flash memory, referring to FIG. 1, including: semiconductor substrate 100；Several layers in semiconductor substrate 100
The conductive layer 110 of stacking；The insulating layer 120 of several layer stackups, insulating layer 120 is located between the conductive layer 110 of adjacent layer, bottom
Conductive layer 110 and semiconductor substrate 100 between and the conductive layer 110 of top layer on；Through the conductive layer 110 and insulation
The channel hole (not shown) of layer 120；Positioned at the substrate extension 101 of channel hole bottom；Side wall and substrate positioned at channel hole
The intrinsic gate dielectric layer 130 of the part of the surface of extension area 101, channel layer 140, channel layer 140 is located in the channel hole and position
In intrinsic 130 surface of gate dielectric layer；The channel dielectric layer 150 wrapped up in channel hole and by channel layer 140；Positioned at conductive layer
High-K gate dielectric layer (not shown) between 110 and intrinsic gate dielectric layer 130；Cover intrinsic gate dielectric layer 130, channel layer 140,
The dielectric layer 160 of channel dielectric layer 150 and insulating layer 120；Through dielectric layer 160, the grid of insulating layer 120 and conductive layer 110
Separate slot 170；Source line doped region 180 in 170 base semiconductor substrate 100 of grid separate slot；Fill full grid separate slot 170
Source cable architecture (not shown).
The method for forming the 3D-NAND flash memory includes: to provide semiconductor substrate 100；It is formed on a semiconductor substrate 100
Compound medium layer, compound medium layer include several layer insulatings 120 and several layers sacrificial layer of intersecting, and compound medium layer
Top layer and bottom be insulating layer；Form the channel hole for running through compound medium layer；Substrate extension is formed in channel hole bottom
101；Intrinsic gate dielectric layer 130, channel layer 140 and channel dielectric layer 150 are formed in channel hole later；It is formed and covers compound Jie
Matter layer, intrinsic gate dielectric layer 130, channel layer 140 and channel dielectric layer 150 dielectric layer 160；It is formed and runs through 160 He of dielectric layer
The grid separate slot 170 of compound medium layer；Source line doped region 180 is formed in the semiconductor substrate 100 of 170 bottom of grid separate slot；
Later, sacrificial layer is removed, opening is formed；High-K gate dielectric layer is formed in the inner wall of opening；It is formed in said opening later conductive
Layer 110；Source cable architecture is formed in grid separate slot 170 later.
However, the performance for the 3D-NAND flash memory that the above method is formed is poor, it has been investigated that, reason is:
When total number of plies of compound medium layer is more, the overall thickness of the compound medium layer is thicker.It is usually necessary to use each
Anisotropy dry carving technology etches compound medium layer to form channel hole.The raising of the depth-to-width ratio in the channel hole will receive each to different
The limitation of property dry carving technology etching technics ability, therefore the aperture in the channel hole is difficult to very little.And in order to improve 3D-
The integrated level of nand flash memory needs to compress adjacent the distance between channel hole.On this basis, growth sky is provided for conductive layer
Between opening size in the horizontal direction it is smaller.
During forming conductive layer 110, conductive layer 110 is raw along the top and bottom of channel hole side wall and opening
It is long.Since the opening for providing growing space for conductive layer 110 size in the horizontal direction is smaller, when conductive layer 110 is grown
It is not grown adequately also longitudinal, just the premature closure between adjacent channel hole, the conductive layer between such adjacent channel hole
There are gaps after 110 sealings.To sum up, cause the performance of 3D-NAND flash memory poor.
In order to solve the above technical problem, the present invention provides a kind of 3D-NAND flash memories, comprising: semiconductor substrate；Positioned at institute
The stacked structure in semiconductor substrate is stated, the stacked structure includes several layer insulatings and several layers conduction of intersecting
Layer；Through the channel structure of the stacked structure, the channel structure includes high-K gate dielectric layer and channel sacrificial layer, the high K
Gate dielectric layer is continuously distributed on the direction perpendicular to semiconductor substrate, and channel sacrificial layer is located at the high-K gate dielectric layer and institute
It states between insulating layer, and channel sacrificial layer is separated in the direction perpendicular to the semiconductor substrate by the conductive layer.It is described
The performance of 3D-NAND flash memory is improved.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Figure 24 is the structural schematic diagram of 3D-NAND flash memory forming process in one embodiment of the invention.
With reference to Fig. 2, semiconductor substrate 200 is provided；Compound medium layer 210 is formed in the semiconductor substrate 200, it is described
Several layer insulatings 211 and several layers sacrificial layer 212 of the compound medium layer 210 including intersecting, and the compound medium layer
210 bottom and top layer is insulating layer 211.
The semiconductor substrate 200 can be monocrystalline silicon, polysilicon or amorphous silicon；The semiconductor substrate 200 can also be with
It is the semiconductor materials such as silicon, germanium, SiGe, GaAs, no longer illustrates one by one.In the present embodiment, the semiconductor substrate 200 is
Silicon.
Each layer is laminated from bottom to top in the compound medium layer 210, and the direction of each layer stackup is vertical in compound medium layer 210
In the surface of semiconductor substrate 200.
The sacrificial layer 212 is used to plant oneself for the conductive layer being subsequently formed, the subsequent removal sacrificial layer 212, and
Conductive layer is formed in the position left after removing sacrificial layer 212；The insulating layer 211 is located at the sacrificial layer 212 of adjacent two layers
Between, between sacrificial layer 212 and semiconductor substrate 200 and on the sacrificial layer 212 of top layer.The position of subsequent sacrificial layer 212 by
After conductive layer replaces, so that insulating layer 211 is used between the conductive layer of adjacent layer, between conductive layer and semiconductor substrate 200
Carry out electric isolation.
The insulating layer 211 is different with the material of sacrificial layer 212, makes during subsequent removal sacrificial layer 212, described
Sacrificial layer 212 is relative to the etching selection ratio with higher of insulating layer 211, thus guarantee that the pattern of the insulating layer 211 is good,
Accurate size, so that the pattern for the conductive layer being subsequently formed is good, accurate size.In addition, the sacrificial layer 212 needs to select
Select the material being easily removed.The material of the insulating layer 211 is silica, silicon oxynitride or silicon oxide carbide.The sacrificial layer 212
Material be silicon nitride, agraphitic carbon or polysilicon.
In the present embodiment, the material of the insulating layer 211 is silica, and the material of the sacrificial layer 212 is silicon nitride.
The technique for forming insulating layer 211 is depositing operation, such as plasma activated chemical vapour deposition technique, sub-atmospheric pressure chemistry
Gas-phase deposition or low-pressure chemical vapor deposition process.The technique for forming sacrificial layer 212 is depositing operation, such as plasma
Chemical vapor deposition process, sub-atmospheric pressure chemical vapor deposition process or low-pressure chemical vapor deposition process.
With reference to Fig. 3, channel hole 220 is formed in the compound medium layer 210.
The technique for forming the channel hole 220 includes anisotropy dry carving technology.
The aperture in the channel hole 220 is 50 nanometers~500 nanometers.The depth-to-width ratio in the channel hole 220 be 10:1~
1000:1。
It is the top view of Fig. 3 with reference to Fig. 4, Fig. 4, and Fig. 3 is the sectional view of the cutting line M-N along Fig. 4, Fig. 4 shows ditch
The shape of the shape in road hole 220 and position, the channel hole 220 is cylindrical, and the channel hole 220 is along the direction x and the side y
To discrete arrangement.
The quantity in the channel hole 220 is multiple.
It is schematic diagram on the basis of Fig. 3 with reference to Fig. 5, Fig. 5, forms substrate extended layer in the bottom in the channel hole 220
230。
After forming substrate extended layer 230, the side wall in the channel hole 220 forms channel sacrificial layer and high K from outside to inside
Gate dielectric layer；Channel composite layer is formed in the channel hole 220, the channel composite layer is located at the high-K gate dielectric layer
Surface.
In the present embodiment, the channel composite layer includes intrinsic gate dielectric layer, channel layer and channel dielectric layer.In other realities
It applies in example, the channel composite layer includes intrinsic gate dielectric layer and channel layer, without including channel dielectric layer.
In the present embodiment, after forming the channel sacrificial layer and high-K gate dielectric layer, the channel composite layer is formed.
The specific steps for forming channel sacrificial layer and high-K gate dielectric layer are specifically introduced below with reference to Fig. 6 to Fig. 7.
With reference to Fig. 6, ditch is formed in the bottom and side wall in the channel hole 220 and the top surface of compound medium layer 210
Road expendable film 240；After forming channel expendable film 240, bottom and side wall and compound medium layer 210 in the channel hole 220
Top form high-K gate dielectric film 250, the high-K gate dielectric film 250 is located at the surface of channel expendable film 240.
The technique for forming the channel expendable film 240 is depositing operation, such as low-pressure chemical vapor deposition process or atomic layer
Depositing operation.The technique for forming the high-K gate dielectric film 250 is depositing operation, such as low-pressure chemical vapor deposition process or atom
Layer depositing operation.
The material of the channel expendable film 240 is different from the material of the sacrificial layer 212, and the material of channel expendable film 240
Expect different from the material of the high-K gate dielectric film 250.The material of the channel expendable film 240 is silica, silicon oxynitride, carbon
Silica or high K dielectric material.
In the present embodiment, the material of the channel expendable film 240 and the material of insulating layer 211 are similar and different.
With reference to Fig. 7, it is etched back to the channel expendable film 240 and high-K gate dielectric film 250, by the channel of 220 bottom of channel hole
Expendable film 240 and high-K gate dielectric film 250 cut through and expose the top surface of substrate extended layer 230, make channel expendable film 240
The channel sacrificial layer 241 is formed, high K dielectric film 250 is made to form the high-K gate dielectric layer 251.
It, also will be compound during being etched back to the channel expendable film 240 and high-K gate dielectric film 250 in the present embodiment
The channel expendable film 240 and high-K gate dielectric film 250 at 210 top of dielectric layer remove.
In the present embodiment, it is etched back to the high K dielectric film 250 and channel expendable film 240, by the high K of 220 bottom of channel hole
The step of deielectric-coating 250 and channel expendable film 240 are cut through carries out before forming channel composite layer.It is being etched back to the height in this way
When K deielectric-coating 250 and channel expendable film 240, the crystalline state of high K dielectric film 250 is not by the work for forming channel composite layer
The influence of skill.Therefore etching high K dielectric film 250, the technique for being etched back to the high K dielectric film 250 and channel expendable film 240 are easy
Difficulty reduce.
It should be noted that if high K dielectric film crystallizes at a high temperature of the material layer of channel composite layer, then etching
The difficulty of high K dielectric film is larger.
The material of the channel sacrificial layer 241 is different with the material of the sacrificial layer 212, and the channel sacrificial layer 241
Material and the high-K gate dielectric layer 251 material it is different.
In the present embodiment, the bottom surface in channel hole 220 also has channel sacrificial layer close to the region of 220 side wall of channel hole
241, i.e. the part of the surface of substrate extended layer 230 has channel sacrificial layer 241.The ditch of 230 part of the surface of substrate extended layer
Road sacrificial layer 241 and L-shaped positioned at the channel sacrificial layer 241 of 220 side wall of channel hole.
The bottom in the channel hole 220 also has high-K gate dielectric layer 251, high K grid close to the region of 220 side wall of channel hole
Dielectric layer 251 is L-shaped.
For the high-K gate dielectric layer 251 and channel sacrificial layer 241 of 220 side wall of channel hole, channel sacrificial layer 241 and high K grid
251 ecto-entad of dielectric layer stacks gradually.
For the high-K gate dielectric layer 251 and channel sacrificial layer 241 of 220 bottom of channel hole, channel sacrificial layer 241 is located at lining
230 surface of bottom extended layer, high-K gate dielectric layer 251 are located on channel sacrificial layer 241.
In one embodiment, channel sacrificial layer 241 with a thickness of 1 nanometer~50 nanometers；The high-K gate dielectric layer 251
With a thickness of 0.1 nanometer~10 nanometers.The overall thickness of the channel sacrificial layer 241 and the high-K gate dielectric layer 251 occupies described
The 2%~30% of the aperture in channel hole 220.
With reference to Fig. 8, intrinsic grid are formed in the bottom and side wall in the channel hole 220 and the top of compound medium layer 210
Deielectric-coating 260, and intrinsic gate dielectric film 260 is located at the surface of high-K gate dielectric layer 251；After forming intrinsic gate dielectric film 260,
Polysilicon protection film 270 is formed on the bottom and side wall in the channel hole 220 and the top of compound medium layer 210, and polysilicon is protected
Cuticula 270 is located at the surface of intrinsic gate dielectric film 260.
In the present embodiment, the intrinsic gate dielectric film 260 includes the block media film (not shown) being sequentially depositing, capture electricity
Lotus film (not shown) and Tunnel dielectric film (not shown), in the bottom in channel hole 220 and the top surface of compound medium layer 210,
Block media film, capture charge film and Tunnel dielectric film stack gradually from bottom to top, the side wall in channel hole 220, block media
Film, capture charge film and Tunnel dielectric film ecto-entad stack gradually.The material of the block media film and Tunnel dielectric film is
The material of silica, the capture charge film is silicon nitride.The intrinsic gate dielectric film 260 is ONO structure film.
In the present embodiment, in order to enable the block media film of 220 side wall of channel hole, capture charge film and Tunnel dielectric film
Thickness is uniform, and pattern is good, and selection forms block media film, capture charge film and Tunnel dielectric film in boiler tube.In other realities
It applies in example, block media film, capture charge film and Tunnel dielectric film can also be formed using depositing operation, such as atomic layer deposition work
Skill etc..
The effect of the polysilicon protection film 270 includes: in the subsequent intrinsic gate dielectric film for cutting through 220 bottom of channel hole
During 260, the polysilicon protection film 270 protects the intrinsic gate dielectric film 260 of 220 side wall of channel hole not damaged by etching
Wound.
With reference to Fig. 9, it is etched back to the intrinsic gate dielectric film 260 and polysilicon protection film 270, by 220 bottom of channel hole
Intrinsic gate dielectric film 260 and polysilicon protection film 270 cut through and expose the top surface of substrate extended layer 230, make intrinsic grid
Deielectric-coating 260 forms intrinsic gate dielectric layer 261.
In the present embodiment, the intrinsic gate dielectric layer 261 is ONO structure layer.The intrinsic gate dielectric layer 261 includes: resistance
Gear dielectric layer, capture charge layer and tunneling medium layer, the block media layer are formed by block media film, capture charge layer by catching
It obtains charge film to be formed, tunneling medium layer is formed by Tunnel dielectric film.Side wall in channel hole 220, block media layer, capture charge
Layer and tunneling medium layer ecto-entad stack gradually.
Side wall in channel hole 220, channel sacrificial layer 241, high-K gate dielectric layer 251 and intrinsic gate dielectric layer 261 are by extroversion
Inside stack gradually.
In the present embodiment, during being etched back to the intrinsic gate dielectric film 260 and polysilicon protection film 270, also will
The intrinsic gate dielectric film 260 and polysilicon protection film 270 at 210 top of compound medium layer remove.
The polysilicon is removed after being etched back to the intrinsic gate dielectric film 260 and polysilicon protection film 270 with reference to Figure 10
Protective film 270 (refers to Fig. 9).
With reference to Figure 11, after removing polysilicon protection film 270, at the bottom in the side wall of intrinsic gate dielectric layer 261, channel hole 220
Channel film 280 is formed on portion and the top of compound medium layer 210, and it is full described then to form filling on 280 surface of channel film
The channel deielectric-coating 290 in channel hole 220.
The material of the channel film 280 is polysilicon.Channel film 280 is formed in boiler tube.
The material of the channel deielectric-coating 290 is silica.The technique for forming channel deielectric-coating 290 is depositing operation, such as
Plasma activated chemical vapour deposition technique, atom layer deposition process, low-pressure chemical vapor deposition process or sub- normal pressure chemical gas
Phase depositing operation.Alternatively, forming channel deielectric-coating 290 in boiler tube.
With reference to Figure 12, it is etched back to channel deielectric-coating 290, removes the channel deielectric-coating 290 on compound medium layer 210, and go
Except part channel deielectric-coating 290 in channel hole 220, recess 300 is formed, and forms the channel dielectric layer for being located at 300 bottoms of recess
291。
The channel dielectric layer 291 is formed by channel deielectric-coating 290.
With reference to Figure 13, in the recess 300 (referring to Figure 12) and 280 surface of channel film forms polysilicon junctional membrane
310。
With reference to Figure 14, the channel film 280 and polysilicon junctional membrane 310 are planarized until exposing compound medium layer 210
Top surface, make channel film 280 formed channel layer 281, make polysilicon junctional membrane 310 formed polysilicon articulamentum 311.
In the present embodiment, the channel composite layer includes intrinsic gate dielectric layer 261, channel layer 281, channel dielectric layer 291
With polysilicon articulamentum 311.
Then ion implanting is carried out to the top of the polysilicon articulamentum 311 and channel layer 281, to form drain region
(not shown).
In the present embodiment, channel composite layer is not only formd in channel hole 220, also forms ditch in channel hole 220
The space in channel hole 220 is adequately utilized in road sacrificial layer and high-K gate dielectric layer in this way.
With reference to Figure 15, is formed and cover the compound medium layer 210, channel composite layer, channel sacrificial layer 241 and high K grid Jie
The top layer dielectric layer 320 of matter layer 251.
The material of the top layer dielectric layer 320 is silica, silicon oxynitride or silicon oxide carbide.Form the top layer dielectric layer
320 technique is depositing operation, as plasma activated chemical vapour deposition technique, atom layer deposition process, low pressure chemical phase are heavy
Product technique or sub- aumospheric pressure cvd technique.
After forming the drain region, top layer dielectric layer 320 is formed.
With reference to Figure 16, the grid separate slot 330 for running through top layer dielectric layer 320 and compound medium layer 210 is formed.
It is the top view of Figure 16 with reference to Figure 17, Figure 17, Figure 16 is the sectional view of the cutting line M1-N1 along Figure 17.
The width direction of the grid separate slot 330 is parallel to the direction y.
Figure 18 is the schematic diagram of the section structure of the cutting line A-A1 along Figure 16.
In the present embodiment, further includes: before subsequent removal sacrificial layer 212, in partly leading for 330 bottom of grid separate slot
Source line doped layer (not shown) is formed in body substrate 200.
It is schematic diagram on the basis of Figure 16 in conjunction with reference Figure 19 and Figure 20, Figure 19, Figure 20 is showing on the basis of Figure 18
It is intended to, and Figure 20 is the schematic diagram of the section structure of the cutting line A-A1 along Figure 19, after forming the grid separate slot 330, removes sacrificial
Domestic animal layer 212 forms the first opening 340.
The technique for removing sacrificial layer 212 is etching technics, such as dry carving technology or wet-etching technique.
In order to be removed clean the sacrificial layer 212 of different height, the over etching time for removing sacrificial layer 212 is longer.
Although the over etching time for removing sacrificial layer 212 is longer, due to the material and sacrificial layer of channel sacrificial layer 241
212 material is different, and in the technique of removal sacrificial layer 212, to the etch rate of sacrificial layer 212 with to channel sacrificial layer
The ratio of 241 etch rate is greater than 300:1, thus remove the technique of sacrificial layer 212 to the loss of channel sacrificial layer 241 compared with
It is few, correspondingly, the channel sacrificial layer 241 for being in same layer height with insulating layer 211 will not be emptied, it is subsequent to avoid adjacent two layers
It links together between conductive layer.
It is schematic diagram on the basis of Figure 19 in conjunction with reference Figure 21 and Figure 22, Figure 21, Figure 22 is showing on the basis of Figure 20
It is intended to, and Figure 22 is the schematic diagram of the section structure of the cutting line A-A1 along Figure 21, the first opening 340 of etching is (in conjunction with reference Figure 19
And Figure 20) side channel sacrificial layer 241 until expose high-K gate dielectric layer 251, form the second opening 341.
Since the thickness of channel sacrificial layer 241 is smaller with respect to the thickness of sacrificial layer 212,340 sides of the first opening of etching
The over etching time of the channel sacrificial layer 241 in portion is less relative to the over etching time of etching removal sacrificial layer 212, therefore etches
The technique of the channel sacrificial layer 241 of first 340 sides of opening will not will be in the channel sacrifice of same layer height with insulating layer 211
Layer 241 is emptied, subsequent to avoid linking together between adjacent two layers conductive layer.
In the present embodiment, the channel sacrificial layer 241 of 340 sides of the first opening of etching removal makes the first opening 340 form the
Two openings 341, space of second opening 341 on 220 line of adjacent channel hole are expanded.There is no need to increase adjacent channel
The distance between hole 220, without the aperture for reducing channel hole 220, so that it may obtain the second opening 341 of larger space.And
High-K gate dielectric layer 251 is formed in channel hole 220, therefore high-K gate dielectric layer 251 is not necessarily to occupy the space of the second opening 341.
For the second opening 341 between adjacent channel hole 220, the longitudinal size of the second opening 341 and the ratio of lateral dimension can
It is reduced.
It is schematic diagram on the basis of Figure 21 in conjunction with reference Figure 23 and Figure 24, Figure 23, Figure 24 is showing on the basis of Figure 22
It is intended to, and Figure 24 is the schematic diagram of the section structure of the cutting line A-A1 along Figure 23, forms conductive layer 350 in the second opening 341.
The technique for forming the conductive layer 350 is depositing operation.The material of the conductive layer 350 is metal, such as tungsten.It is described
Conductive layer 350 can be used for constituting control gate or selection grid.
During forming conductive layer 350, conductive layer 350 is along 220 side wall of channel hole and the top of the second opening 341
Portion and bottom grown.Since the second opening 341 is grown in the space provided for conductive layer 350, the longitudinal size of the second opening 341
It can be reduced with the ratio of transverse direction (direction of x-axis and the direction of y-axis) size, therefore conductive layer 350 can be made along second
The top and bottom of opening 341 are sufficiently grown in longitudinal direction (z-axis direction), avoid conductive layer 350 when growing in adjacent channel hole 220
Between premature closure, thus be avoided that after conductive layer 350 between adjacent channel hole 220 seals that there are gaps.To sum up, it improves
The performance of 3D-NAND flash memory.
Secondly, the channel sacrificial layer 241 of 340 sides of the first opening of etching removal is until expose high-K gate dielectric layer 251,
Form the second opening 341.It can be situated between during the channel sacrificial layer 241 of 340 sides of the first opening of etching removal with high K grid
Matter layer 251 is stop-layer, so that the technique of the channel sacrificial layer 241 of 340 sides of the first opening of etching removal can obtain
Preferable control.
In the present embodiment, further includes: after forming the conductive layer 350, form source cable architecture in the grid separate slot 330
(not shown).
In the present embodiment, 251 constituting channel structure of the channel composite layer, channel sacrificial layer 241 and high-K gate dielectric layer.
Correspondingly, the present embodiment also provides a kind of 3D-NAND flash memory formed using the above method, Figure 23 and figure are please referred to
24, comprising: semiconductor substrate 200；Stacked structure in the semiconductor substrate 200, the stacked structure include staggeredly
Several layer insulatings 211 and several layers conductive layer 350 of stacking；Through the channel structure of the stacked structure, the channel junction
Structure includes high-K gate dielectric layer 251 and channel sacrificial layer 241, and the high-K gate dielectric layer 251 is perpendicular to semiconductor substrate 200
Continuously distributed on direction, channel sacrificial layer 241 is between the high-K gate dielectric layer 251 and the insulating layer 211, and channel
Sacrificial layer 241 is separated in the direction perpendicular to the semiconductor substrate 200 by the conductive layer 350.
The material of the channel sacrificial layer 241 is different with the material of the high-K gate dielectric layer 251；The channel sacrificial layer
241 material is silica, silicon oxynitride, silicon oxide carbide or high K dielectric material.
The overall thickness of the channel sacrificial layer 241 and the high-K gate dielectric layer 251 is first size；The channel structure
Corresponding diameter is the second size at the position with channel sacrificial layer 241 and high-K gate dielectric layer 251.
In the present embodiment, first size is the 2%~30% of the second size.
Specifically, described second having a size of 50 nanometers~500 nanometers；The channel sacrificial layer 241 with a thickness of 1 nanometer~
50 nanometers, the high-K gate dielectric layer 251 with a thickness of 1 nanometer~50 nanometers.
The channel structure further includes channel composite layer, and the channel composite layer is located at the table of the high-K gate dielectric layer 251
Face, and the high-K gate dielectric layer 251 is between the channel sacrificial layer 241 and the channel composite layer.
The channel composite layer includes positioned at the intrinsic gate dielectric layer 261 on 251 surface of high-K gate dielectric layer and positioned at institute
State the channel layer 281 on intrinsic 261 surface of gate dielectric layer；The intrinsic gate dielectric layer 261 includes block media layer, capture charge layer
And tunneling medium layer, the block media layer, capture charge layer and tunneling medium layer are perpendicular to channel structure side wall and from ditch
Road structure is outer to stacking gradually on the direction in channel structure.
The channel composite layer further includes channel dielectric layer 291 and polysilicon articulamentum 311, the channel dielectric layer 291
Positioned at the surface of channel layer 281, the polysilicon articulamentum 311 is located on the channel layer 281, and the channel dielectric layer
291 are wrapped up by the polysilicon articulamentum 311 and channel layer 281.
Foregoing teachings are please referred to about other contents in the channel composite layer, are no longer described in detail.
The 3D-NAND flash memory further include: the substrate between the channel structure and the semiconductor substrate 200 prolongs
Stretch layer 230.The channel sacrificial layer 241, high-K gate dielectric layer 251 and channel composite layer are respectively positioned on substrate extended layer 230.
The channel sacrificial layer 241 is also located at the part of the surface of the substrate extended layer 230；Substrate extended layer part
The channel sacrificial layer 241 of the channel sacrificial layer 241 on surface and channel structure side bottom connection and L-shaped.
The 3D-NAND flash memory further include: cover the compound medium layer 210, channel composite layer, channel sacrificial layer 241
With the top layer dielectric layer 320 of high-K gate dielectric layer 251.
In the 3D-NAND flash memory that technical solution of the present invention provides, the channel structure includes that channel sacrificial layer and high K grid are situated between
Matter layer.The high-K gate dielectric layer is not necessarily to occupy the space between adjacent insulating layer.The channel sacrificial layer is perpendicular to described half
Separated on the direction of conductor substrate by the conductive layer, i.e., the described conductive layer edge extends between the channel sacrificial layer of adjacent layer.
Therefore, in the case that diameter of the channel structure at the position with channel sacrificial layer and high-K gate dielectric layer is certain, energy
Enough so that conductive layer is larger in the size of transverse direction.Make to sufficiently grow conducive to conductive layer longitudinally in this way, conductive layer is sealing
Gap is less prone at mouthful.To sum up, the performance of 3D-NAND flash memory is improved.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (8)
1. a kind of 3D-NAND flash memory characterized by comprising
Semiconductor substrate；
Stacked structure in the semiconductor substrate, if the stacked structure include intersecting several layer insulatings and
Dried layer conductive layer；
Through the channel structure of the stacked structure, the channel structure includes high-K gate dielectric layer and channel sacrificial layer, the height
K gate dielectric layer is continuously distributed on the direction perpendicular to semiconductor substrate, and channel sacrificial layer is located at the high-K gate dielectric layer and institute
It states between insulating layer, and channel sacrificial layer is separated in the direction perpendicular to the semiconductor substrate by the conductive layer.
2. 3D-NAND flash memory according to claim 1, which is characterized in that the material of the channel sacrificial layer and the high K
The material of gate dielectric layer is different；The material of the channel sacrificial layer is silica, silicon oxynitride, silicon oxide carbide or high K dielectric material
Material.
3. 3D-NAND flash memory according to claim 1, which is characterized in that the channel sacrificial layer and the high-K gate dielectric
The overall thickness of layer is first size；The channel structure is corresponding at the position with channel sacrificial layer and high-K gate dielectric layer
Diameter is the second size, and first size is the 2%~30% of the second size.
4. 3D-NAND flash memory according to claim 3, which is characterized in that described second receives having a size of 50 nanometers~500
Rice；The channel sacrificial layer with a thickness of 1 nanometer~50 nanometers, the high-K gate dielectric layer with a thickness of 1 nanometer~50 nanometers.
5. 3D-NAND flash memory according to claim 1, which is characterized in that the channel structure further includes channel composite layer,
The channel composite layer is located at the surface of the high-K gate dielectric layer, and the high-K gate dielectric layer be located at the channel sacrificial layer and
Between the channel composite layer.
6. 3D-NAND flash memory according to claim 5, which is characterized in that the channel composite layer includes being located at the high K
The intrinsic gate dielectric layer on gate dielectric layer surface and channel layer positioned at the intrinsic gate dielectric layer surface；The intrinsic gate dielectric layer
Including block media layer, capture charge layer and tunneling medium layer, the block media layer, capture charge layer and tunneling medium layer exist
To stacking gradually on the direction in channel structure perpendicular to channel structure side wall and from outside channel structure.
7. 3D-NAND flash memory according to claim 1, which is characterized in that further include: it is located at the channel structure and described
Substrate extended layer between semiconductor substrate.
8. 3D-NAND flash memory according to claim 7, which is characterized in that the channel sacrificial layer is also located at the substrate
The part of the surface of extended layer；The channel sacrificial layer of the substrate extended layer part of the surface and the ditch of channel structure side bottom
Road sacrificial layer connection and it is L-shaped.
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| CN112530975A (en) * | 2020-12-07 | 2021-03-19 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| CN113097216A (en) * | 2020-01-16 | 2021-07-09 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
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