CN105810639B - A kind of 3D NAND flash memory structure and preparation method thereof - Google Patents
A kind of 3D NAND flash memory structure and preparation method thereof Download PDFInfo
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- 230000015654 memory Effects 0.000 title claims abstract description 28
- 238000002360 preparation method Methods 0.000 title description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 62
- 229920005591 polysilicon Polymers 0.000 claims abstract description 59
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 claims abstract description 21
- 238000002955 isolation Methods 0.000 claims abstract description 20
- 238000000034 method Methods 0.000 claims abstract description 20
- 230000004888 barrier function Effects 0.000 claims abstract description 17
- 238000010893 electron trap Methods 0.000 claims abstract description 17
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 12
- 230000003647 oxidation Effects 0.000 claims abstract description 11
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 238000001039 wet etching Methods 0.000 claims abstract description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 10
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 2
- 238000005137 deposition process Methods 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 19
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 19
- 239000004065 semiconductor Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 7
- 229910052760 oxygen Inorganic materials 0.000 description 7
- 239000001301 oxygen Substances 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000003860 storage Methods 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
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Abstract
The present invention relates to technical field of manufacturing semiconductors more particularly to the production methods of a kind of 3D NAND flash memory structure and the 3D NAND flash memory structure.This method comprises: providing substrate, and grid oxic horizon is sequentially formed on substrate, drain selection pipe polysilicon layer, the oxide isolation layer and sacrificial dielectric layer of multiple stackings, drain selecting pipe polysilicon layer, and protection oxide layer；Etching forms the cylindrical channel for exposing substrate；Tunnel oxide, polysilicon and polysilicon spacer medium layer are formed in cylindrical channel；Etching forms the source electrode groove for exposing substrate, and forms public source；Wet etching removes the sacrificial dielectric layer；Electron trapping layer and barrier oxide layer are sequentially formed in the side wall and oxide isolation layer inner wall of source electrode groove；Grid is formed in barrier oxidation layer surface.Selecting pipe made from this method does not include electron trapping layer silicon nitride, avoids the threshold voltage shift and leaky of selecting pipe, improves the quality of memory device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of 3D NAND flash memory structure and the 3D NAND to dodge
The production method for depositing structure.
Background technique
With the fast development of flash memories, three-dimensional (3D) flash memories structure is rapidly developed, 3D NAND
Flash memory has been widely used in semiconductor devices.
In the production method of existing 3D NAND flash memory structure, drain selecting pipe (String Select Line, SSL)
It is consistent with the manufacture craft of storage unit with the manufacture craft of drain selection pipe (Ground Select Line, GSL), that is,
During gate oxidation (Gate Oxide) layer for forming selecting pipe, electron trapping layer is inevitably introduced in selecting pipe
(Charge Trap Layer) silicon nitride SiN.Include electron trapping layer in selecting pipe, cause in the real work of circuit,
SSL selecting pipe and GSL selecting pipe also can inevitably have slight charge storage and release, and cause the threshold voltage of selecting pipe
Vt drift eventually leads to conducting electric current variation and leaky.Especially (Cycling) especially is being read and write in memory device
After repeatedly, which is become apparent, and then the reading of storage unit is caused to be failed.
To sum up, existing selecting pipe includes electron trapping layer, leads to the second-rate of memory device, and being unable to satisfy user needs
It asks.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of 3D NAND flash memory structure and preparation method thereof, it is existing to solve
The problem of selecting pipe includes electron trapping layer in technology.
On the one hand, the embodiment of the invention provides a kind of production methods of 3D NAND flash memory structure, comprising:
Substrate is provided, and sequentially forms grid oxic horizon on substrate, drain selection pipe polysilicon layer, the oxygen of multiple stackings
Change dielectric layer and sacrificial dielectric layer, drain selecting pipe polysilicon layer, and protection oxide layer, wherein the sacrificial dielectric layer shape
At between adjacent oxide isolation layer；
Etching forms the cylindrical channel for exposing substrate；
Tunnel oxide, polysilicon and polysilicon spacer medium layer are sequentially formed in the cylindrical channel；
Etching forms the source electrode groove for exposing substrate, and forms public source；
Wet etching removes the sacrificial dielectric layer；
Electron trapping layer and barrier oxide layer are sequentially formed in the side wall and oxide isolation layer inner wall of the source electrode groove；
Grid is formed in barrier oxidation layer surface.
Further, tunnel oxide, polysilicon and polysilicon spacer medium are sequentially formed in the cylindrical channel
Layer, comprising:
Tunnel oxide is formed in trench sidewalls using atom layer deposition process, and etches away the tunnel oxide of trench bottom
Layer；
Polysilicon is formed on the surface of the tunnel oxide, and forms polysilicon isolation in the inside of the polysilicon and is situated between
Matter layer.
Further, etching forms the source electrode groove for exposing substrate, and forms public source, comprising:
The source electrode groove for exposing substrate is formed using dry etch process；
It is doped using substrate of the ion implantation to exposing, forms public source.
Further, etching removes the sacrificial dielectric layer, comprising: removes the sacrificial dielectric using hot phosphoric acid etching
Layer.
Further, etching is formed before the cylindrical channel for exposing substrate, further includes:
Multiple photoetching and multiple etching, form building trapezoidal groove；
Backfill oxide layer is formed in the building trapezoidal groove, and the backfill oxide layer is carried out at chemical mechanical grinding
Reason.
Further, grid is formed in barrier oxidation layer surface, comprising: sequentially form oxygen in the barrier oxidation layer surface
Change aluminium layer, titanium nitride layer and tungsten layer.
Further, the thickness of the drain selection pipe polysilicon layer and the drain electrode selecting pipe polysilicon layer is
Further, the tunnel oxide with a thickness of
Further, the electron trapping layer with a thickness ofThe barrier oxide layer with a thickness of
On the other hand, the embodiment of the invention also provides a kind of 3D NAND flash memory structure, the 3D NAND flash memory structures
The production method of the 3D NAND flash memory structure provided by any embodiment of that present invention is made.
3D NAND flash memory structure provided in an embodiment of the present invention and preparation method thereof, sequentially forms grid oxygen on substrate
Change layer, drain selection pipe polysilicon layer, the oxide isolation layer and sacrificial dielectric layer of multiple stackings, drain selecting pipe polysilicon layer with
And protection oxide layer, that is, this method replaces the silicon nitride sacrificial layers in selecting pipe using polysilicon layer, so that going to denitrogenate in etching
When SiClx sacrificial dielectric layer, polysilicon layer is retained, thus in the process for forming electron trapping layer, barrier oxide layer and grid
In play a part of barrier layer, therefore, the structure of selecting pipe made from this method includes polysilicon layer and tunnel oxide, without
Including electron trapping layer silicon nitride, the threshold voltage shift and leaky of selecting pipe are avoided, memory device is improved
Quality.
Detailed description of the invention
By reading a detailed description of non-restrictive embodiments in the light of the attached drawings below, of the invention other
Feature, objects and advantages will become more apparent upon:
Fig. 1 a- Fig. 1 e is the schematic diagram of 3D NAND production method in the prior art；
Fig. 2 is the flow diagram of the 3D NAND production method provided in the embodiment of the present invention；
Fig. 3 a- Fig. 3 j is the schematic diagram of the 3D NAND production method provided in the embodiment of the present invention one.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
In description, only some but not all contents related to the present invention are shown in the drawings.
Fig. 1 a- Fig. 1 e is the schematic diagram of 3D nand flash memory production method in the prior art.As shown in Figure 1a, existing
Production method provides substrate 100, and grid oxic horizon 111 is formed on substrate 100, GSL silicon nitride layer 121, multiple stackings
Oxide isolation layer 112 and sacrificial dielectric layer 122, SSL silicon nitride layer 123, and protection oxide layer 113, wherein the sacrificial dielectric
Layer 122 is formed between adjacent oxide isolation layer 112.As shown in Figure 1 b, etching forms the cylindrical type ditch for exposing substrate 100
Road, and tunnel oxide 131, polysilicon 132 and polysilicon spacer medium layer 133 are sequentially formed in the cylindrical channel.
As illustrated in figure 1 c, etching forms the source electrode groove 140 for exposing substrate 100, and forms public source 150；As shown in Figure 1 d, it adopts
Silicon nitride layer is removed with phosphoric acid, that is, removal GSL silicon nitride layer 121, each sacrificial dielectric layer 122 and SSL silicon nitride layer 123.Such as figure
Shown in 1e, electron trapping layer 350, barrier oxide layer 360 and grid are sequentially formed in oxide isolation layer inner wall and source electrode groove
370。
Therefore, in existing 3D NAND flash memory structure, GSL selecting pipe and SSL selecting pipe include silicon nitride electronics prisoner
Layer is obtained, is caused in the real work of circuit, SSL selecting pipe and GSL selecting pipe also can inevitably have slight charge to deposit
It stores up and releases, cause the threshold voltage vt drift of selecting pipe, eventually lead to conducting electric current variation and close continuous leaky.
It is especially being especially after memory device read-write repeatedly, which becomes apparent, and then the reading of storage unit is caused to be failed.
In view of the above-mentioned problems, this method uses polycrystalline the present invention provides a kind of production method of 3D NAND flash memory structure
Silicon layer replaces the silicon nitride sacrificial layers in selecting pipe, so that selecting pipe includes polysilicon layer and tunnel oxide, without including electricity
Muon capture layer silicon nitride avoids the threshold voltage shift phenomenon of selecting pipe, improves the quality of memory device.
Embodiment one
Based on above description, the embodiment of the present invention one provides following solution.
Fig. 2 is the flow diagram of the production method of the 3D NAND flash memory structure provided in the embodiment of the present invention, such as Fig. 2
Shown, this method may comprise steps of:
Step 21 provides substrate, and sequentially forms grid oxic horizon on substrate, GSL polysilicon layer, the oxygen of multiple stackings
Change dielectric layer and sacrificial dielectric layer, SSL polysilicon layer, and protection oxide layer, wherein the sacrificial dielectric layer is formed in adjacent
Oxide isolation layer between；
Step 22, etching form the cylindrical channel for exposing substrate；
Step 23 sequentially forms tunnel oxide, polysilicon and polysilicon spacer medium layer in the cylindrical channel；
Step 24, etching form the source electrode groove for exposing substrate, and form public source；
Step 25, wet etching remove the sacrificial dielectric layer；
Step 26, the source electrode groove side wall and oxide isolation layer inner wall sequentially form electron trapping layer and stop oxygen
Change layer；
Step 27 forms grid in barrier oxidation layer surface.
The present embodiment is sequentially forming grid oxic horizon, GSL polysilicon layer, the oxide isolation layer of multiple stackings on substrate
And sacrificial dielectric layer, SSL polysilicon layer and protection oxide layer, that is, this method replaces the nitridation in selecting pipe using polysilicon
Silicon, avoiding includes electron trapping layer silicon nitride in selecting pipe, so as to avoid the threshold voltage shift phenomenon of selecting pipe, is improved
The quality of memory device.
The production method of the 3D NAND flash memory structure provided in present aspect is provided in detail below.
With reference to shown in Fig. 3 a, substrate 300 is cleaned and provided, is grown about on substrate 300Gate oxidation
Layer 311, grows about on the grid oxic horizon 311GSL polysilicon layer 321, and use chemical gaseous phase
The oxygen of (Chemical Vapor Deposition, the CVD) technology of deposition 321 multiple stackings of generation on the GSL polysilicon layer
Change dielectric layer 312 and sacrificial dielectric layer 322, wherein the sacrificial dielectric layer 322 be formed in adjacent oxide isolation layer 312 it
Between, oxide isolation layer 312 can beSilica, sacrificial dielectric layer 322 can beNitridation
Silicon.
The present invention is not especially limited the number of plies of sacrificial dielectric layer and oxide isolation layer, can hold according to storage unit
Amount needs to be designed to 8,16,32,48 and 64 layers etc..In the present embodiment for 2 layers.
In addition, being grown on uppermost oxide isolation layer 312SSL polysilicon layer 323, and in institute
Stating growth thickness on SSL polysilicon layer 323 isProtection oxide layer 313.
With reference to shown in Fig. 3 b and Fig. 3 c, multiple photoetching and multiple etching, and etching is parked in polysilicon or silicon nitride every time
On, form building trapezoidal groove；Backfill oxide layer 314 is formed also in the building trapezoidal groove, to fill the building trapezoidal groove,
And chemical mechanical grinding (Chemical Mechanical Polishing, CMP) processing is carried out to the backfill oxide layer, make
The backfill oxide layer has flat surface.
With reference to shown in Fig. 3 d, successively to the sacrificial dielectric layer 322 for protecting oxide layer, SSL polysilicon layer 323, multiple stackings
With oxide isolation layer, GSL polysilicon layer 321 and grid oxic horizon are patterned processing, form the cylinder for exposing substrate
Shape channel cylindrical channel (Channel hole) 330.
With reference to shown in Fig. 3 e, using atomic layer deposition (Atomic Layer Deposition, ALD) in trench sidewalls shape
AtTunnel oxide 331, and using side wall etching technics removal trench bottom tunnel oxide 331, expose
The substrate 300.
With reference to shown in Fig. 3 f, polysilicon 332 and polysilicon spacer medium layer are formed on the surface of the tunnel oxide 331
333.Specifically, can be formed on the surface of tunnel oxide 331Polysilicon, subsequently form
Polysilicon spacer medium layer 333, and processing is etched back to polysilicon spacer medium layer 333, the polysilicon is isolated
The height of dielectric layer 333 is lower than the height of the channel, is then formed againPolysilicon, and to the polysilicon
CMP processing is carried out, the polysilicon above channel is removed, keeps polysilicon layer 332 and filling oxide layer 314 contour.Wherein, described more
The material of crystal silicon spacer medium layer 333 can be silica.
With reference to shown in Fig. 3 g, the source electrode groove for exposing substrate 300 is formed using dry etching (Dry etch) technique
(Slit) 340, and N+ is adulterated in the silicon substrate 300 of exposing using ion implantation, form public source (Common
Source Line, CSL) 350.
With reference to shown in Fig. 3 h, the sacrificial dielectric layer 322 is removed using hot phosphoric acid etching.It is noted that since GSL is selected
The material of tube layer 321 and SSL selection tube layer 323 is polysilicon, and the material of sacrificial dielectric layer 322 is silicon nitride, therefore in heat
GSL selects tube layer 321 and SSL selection tube layer 323 not to be corroded during phosphoric acid corrosion sacrificial dielectric layer.
With reference to shown in Fig. 3 i, formed in the side wall of oxide isolation layer inner wall and source electrode groove 340Electron capture
Layer silicon nitride 350, and formed on the surface of the electron trapping layer silicon nitride 350Barrier oxide layer 360, wherein
The material of barrier oxide layer 360 can be silica, therefore, form the ONO (silicon oxide-silicon nitride-oxidation of storage unit
Silicon) dielectric layer.
With reference to shown in Fig. 3 j, grid 370 is formed on the surface of the barrier oxide layer 360.Specifically, in the blocking oxygen
Change successively to grow up on the surface of layer 360 and form alumina layer, titanium nitride layer and tungsten layer, forms tungsten grid 370.
GSL selecting pipe/SSL selection in flash memory structure made from the 3D NAND production method provided in the embodiment of the present invention
Pipe formed structure be polycrystalline silicon/oxidative silicon/polysilicon, and the structure of storage unit be tungsten (grid)/silica/silicon nitride/
Silica/polysilicon, that is, do not include electron trapping layer silicon nitride in GSL selecting pipe and SSL selecting pipe.Therefore, the flash memory knot
Structure avoids threshold voltage shift phenomenon and leaky caused by selecting pipe trapped electron, improves 3D nand flash memory
Quality.
The embodiment of the present invention also provides a kind of 3D NAND flash memory structure, and the 3D NAND flash memory structure can be by the present invention
The production method for the 3D NAND flash memory structure that any embodiment provides is made.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of production method of 3D NAND flash memory structure characterized by comprising
Substrate is provided, and sequentially forms grid oxic horizon on substrate, the oxidation of drain selection pipe polysilicon layer, multiple stackings is situated between
Matter layer and sacrificial dielectric layer, drain selecting pipe polysilicon layer, and protection oxide layer, wherein the sacrificial dielectric layer is formed in
Between adjacent oxide isolation layer；
Etching forms the cylindrical channel for exposing substrate；
Tunnel oxide, polysilicon and polysilicon spacer medium layer are sequentially formed in the cylindrical channel；
Etching forms the source electrode groove for exposing substrate, and forms public source；
Wet etching removes the sacrificial dielectric layer；
Electron trapping layer and barrier oxide layer are sequentially formed in the side wall and oxide isolation layer inner wall of the source electrode groove；
Grid is formed in barrier oxidation layer surface.
2. the method according to claim 1, wherein sequentially forming tunnel oxide in the cylindrical channel
Layer, polysilicon and polysilicon spacer medium layer, comprising:
Tunnel oxide is formed in trench sidewalls using atom layer deposition process, and etches away the tunnel oxide of trench bottom；
Polysilicon is formed on the surface of the tunnel oxide, and forms polysilicon spacer medium in the inside of the polysilicon
Layer.
3. the method according to claim 1, wherein etching forms the source electrode groove for exposing substrate, and being formed
Public source, comprising:
The source electrode groove for exposing substrate is formed using dry etch process；
It is doped using substrate of the ion implantation to exposing, forms public source.
4. the method according to claim 1, wherein etching removes the sacrificial dielectric layer, comprising:
The sacrificial dielectric layer is removed using hot phosphoric acid etching.
5. the method according to claim 1, wherein etching is formed before the cylindrical channel for exposing substrate,
Further include:
Multiple photoetching and multiple etching, form building trapezoidal groove；
Backfill oxide layer is formed in the building trapezoidal groove, and chemical mechanical grinding processing is carried out to the backfill oxide layer.
6. the method according to claim 1, wherein forming grid in barrier oxidation layer surface, comprising:
Alumina layer, titanium nitride layer and tungsten layer are sequentially formed in the barrier oxidation layer surface.
7. the method according to claim 1, wherein the drain selection pipe polysilicon layer and drain electrode selection
The thickness of pipe polysilicon layer is
8. the method according to claim 1, wherein the tunnel oxide with a thickness of
9. the method according to claim 1, wherein the electron trapping layer with a thickness ofThe resistance
Keep off oxide layer with a thickness of
10. a kind of 3D NAND flash memory structure, which is characterized in that be made by the described in any item production methods of claim 1-9.
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| CN107808884A (en) * | 2016-08-24 | 2018-03-16 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of three dimensional NAND flush memory device |
| CN107482017A (en) * | 2017-08-22 | 2017-12-15 | 长江存储科技有限责任公司 | A kind of preparation technology in 3D nand flash memories raceway groove hole |
| WO2021127980A1 (en) * | 2019-12-24 | 2021-07-01 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional nand memory device and method of forming the same |
| CN112038349A (en) * | 2020-09-08 | 2020-12-04 | 长江存储科技有限责任公司 | Method for forming channel hole of three-dimensional memory device and three-dimensional memory device |
| CN112164696B (en) * | 2020-09-24 | 2022-01-25 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN113053904A (en) * | 2021-03-15 | 2021-06-29 | 维沃移动通信有限公司 | Three-dimensional flash memory structure and electronic equipment |
| CN113454781B (en) | 2021-05-28 | 2024-05-28 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of forming the same |
| CN113454780B (en) * | 2021-05-28 | 2023-05-09 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of forming the same |
| CN113871486A (en) * | 2021-09-27 | 2021-12-31 | 北京大学 | Multi-floating-gate laminated type synaptic transistor and preparation method thereof |
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