CN105810639A - 3D NAND flash memory structure and manufacturing method therefor - Google Patents
3D NAND flash memory structure and manufacturing method therefor Download PDFInfo
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- CN105810639A CN105810639A CN201410854359.5A CN201410854359A CN105810639A CN 105810639 A CN105810639 A CN 105810639A CN 201410854359 A CN201410854359 A CN 201410854359A CN 105810639 A CN105810639 A CN 105810639A
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- 230000015654 memory Effects 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 64
- 238000000034 method Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000002955 isolation Methods 0.000 claims abstract description 22
- 238000001039 wet etching Methods 0.000 claims abstract description 4
- 229920005591 polysilicon Polymers 0.000 claims description 56
- 230000004888 barrier function Effects 0.000 claims description 18
- 238000010893 electron trap Methods 0.000 claims description 18
- 125000006850 spacer group Chemical group 0.000 claims description 13
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 10
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 21
- 230000003647 oxidation Effects 0.000 abstract description 8
- 238000007254 oxidation reaction Methods 0.000 abstract description 8
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 238000003860 storage Methods 0.000 abstract description 3
- 230000005264 electron capture Effects 0.000 abstract 2
- 230000000903 blocking effect Effects 0.000 abstract 1
- 230000005641 tunneling Effects 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 230000001351 cycling effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
Abstract
The invention relates to the technical field of semiconductor manufacturing, and especially relates to a 3D NAND flash memory structure and a manufacturing method therefor. The method comprises the steps: providing a substrate, and sequentially forming a grid oxidation layer, a source selectron polycrystalline silicon layer, a plurality of stacked oxidation dielectric layers and sacrificial dielectric layers, a drain selectron polycrystalline silicon layer, and a protection oxidation layer; carrying out etching and forming a cylindrical trench exposing the substrate; forming a tunneling oxidation layer, polycrystalline silicon and a polycrystalline silicon isolation dielectric layer in the cylindrical trench; carrying out etching and forming a source trench exposing the substrate, and forming a public source electrode; carrying out wet etching, and removing the sacrificial dielectric layers; sequentially forming an electron capture layer and a blocking oxidation layer on a side wall of the source trench and an inner wall of the oxidation dielectric layer; and forming a grid electrode on the surface of the oxidation dielectric layer. A selectron prepared through the method does not contain electron capture layer silicon nitride, thereby avoiding the threshold voltage drift and electric leakage of the selectron, and improving the quality of a storage device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the manufacture method of a kind of 3DNAND flash memory structure and this 3DNAND flash memory structure.
Background technology
Along with the fast development of flash memories, three-dimensional (3D) flash memories structure obtains and develops rapidly, and 3DNAND flash memory has been widely used in semiconductor device.
In the manufacture method of existing 3DNAND flash memory structure, drain electrode selects pipe (StringSelectLine, and drain selection pipe (GroundSelectLine SSL), GSL) processing technology is consistent with the processing technology of memory element, namely, in the process forming gate oxidation (GateOxide) layer selecting pipe, in selecting pipe, inevitably introduce electron trapping layer (ChargeTrapLayer) silicon nitride SiN.Pipe is selected to include electron trapping layer, cause in the real work of circuit, SSL selects pipe and GSL to select pipe also can inevitably have slight electric charge storage and release, and causes the threshold voltage vt drift selecting pipe, ultimately results in On current change and leaky.Particularly in particularly after memory device read-write (Cycling) is repeatedly, this phenomenon becomes apparent from, and then causes the reading of memory element to lose efficacy.
To sum up, existing selection pipe includes electron trapping layer, causes the second-rate of memory device, it is impossible to meet user's request.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of 3DNAND flash memory structure and preparation method thereof, with the problem solving to select pipe to include electron trapping layer in prior art.
On the one hand, embodiments provide the manufacture method of a kind of 3DNAND flash memory structure, including:
Substrate is provided, and on substrate, sequentially forms grid oxic horizon, drain selection pipe polysilicon layer; multiple stacking oxide isolation layers and sacrificial dielectric layer, drain electrode selects pipe polysilicon layer and protection oxide layer; wherein, described sacrificial dielectric layer is formed between adjacent oxide isolation layer；
Etching forms the cylindrical channel exposing substrate；
Tunnel oxide, polysilicon and polysilicon spacer medium layer is sequentially formed in described cylindrical channel；
Etching forms the source electrode groove exposing substrate, and forms public source；
Wet etching removes described sacrificial dielectric layer；
Sidewall and oxide isolation layer inwall at described source electrode groove sequentially form electron trapping layer and barrier oxide layer；
Grid is formed on barrier oxide layer surface.
Further, in described cylindrical channel, sequentially form tunnel oxide, polysilicon and polysilicon spacer medium layer, including:
Adopt atom layer deposition process to form tunnel oxide in trench sidewalls, and etch away the tunnel oxide of trench bottom；
Form polysilicon on the surface of described tunnel oxide, and be internally formed polysilicon spacer medium layer at described polysilicon.
Further, etching forms the source electrode groove exposing substrate, and forms public source, including:
Dry etch process is adopted to form the source electrode groove exposing substrate；
Adopt ion implantation that the substrate exposed is adulterated, form public source.
Further, etching removes described sacrificial dielectric layer, including: adopt hot phosphoric acid etching to remove described sacrificial dielectric layer.
Further, etching also includes before forming the cylindrical channel exposing substrate:
Repeatedly photoetching and multiple etching, forms building trapezoidal groove；
In described building trapezoidal groove, form backfill oxide layer, and described backfill oxide layer is carried out cmp process.
Further, form grid on barrier oxide layer surface, including: sequentially form alumina layer, titanium nitride layer and tungsten layer on described barrier oxide layer surface.
Further, described drain selection pipe polysilicon layer and described drain electrode select the thickness of pipe polysilicon layer to be
Further, the thickness of described tunnel oxide is
Further, the thickness of described electron trapping layer isThe thickness of described barrier oxide layer is
On the other hand, the embodiment of the present invention additionally provides a kind of 3DNAND flash memory structure, and the manufacture method of the 3DNAND flash memory structure that described 3DNAND flash memory structure is provided by any embodiment of the present invention prepares.
3DNAND flash memory structure that the embodiment of the present invention provides and preparation method thereof, substrate sequentially forms grid oxic horizon, drain selection pipe polysilicon layer, multiple stacking oxide isolation layers and sacrificial dielectric layer, drain electrode selects pipe polysilicon layer and protection oxide layer, namely, the method adopts polysilicon layer to replace selecting the silicon nitride sacrificial layers in pipe, make when etching removes silicon nitride sacrificial dielectric layer, polysilicon layer is retained, thus forming electron trapping layer, the process of barrier oxide layer and grid plays a part barrier layer, therefore, the structure selecting pipe that the method prepares includes polysilicon layer and tunnel oxide, and do not include electron trapping layer silicon nitride, avoid the threshold voltage shift and leaky that select pipe, improve the quality of memory device.
Accompanying drawing explanation
By reading the detailed description that non-limiting example is made made with reference to the following drawings, the other features, objects and advantages of the present invention will become more apparent upon:
Fig. 1 a-Fig. 1 e is the schematic diagram of 3DNAND manufacture method of the prior art；
The schematic flow sheet of the Fig. 2 3DNAND manufacture method for providing in the embodiment of the present invention；
Fig. 3 a-Fig. 3 j is the schematic diagram of the 3DNAND manufacture method provided in the embodiment of the present invention one.
Detailed description of the invention
Below in conjunction with drawings and Examples, the present invention is described in further detail.It is understood that specific embodiment described herein is used only for explaining the present invention, but not limitation of the invention.It also should be noted that, for the ease of describing, accompanying drawing illustrate only part related to the present invention but not full content.
Fig. 1 a-Fig. 1 e is the schematic diagram of 3DNAND preparation method for flash memory of the prior art.As shown in Figure 1a; existing manufacture method; substrate 100 is provided; and form grid oxic horizon 111 on the substrate 100; GSL silicon nitride layer 121, multiple stacking oxide isolation layers 112 and sacrificial dielectric layer 122, SSL silicon nitride layer 123; and protection oxide layer 113, wherein said sacrificial dielectric layer 122 is formed between adjacent oxide isolation layer 112.As shown in Figure 1 b, etching forms the cylindrical channel exposing substrate 100, and sequentially forms tunnel oxide 131, polysilicon 132 and polysilicon spacer medium layer 133 in described cylindrical channel.As illustrated in figure 1 c, etching forms the source electrode groove 140 exposing substrate 100, and forms public source 150；As shown in Figure 1 d, phosphoric acid is adopted to remove silicon nitride layer, i.e. to remove GSL silicon nitride layer 121, each sacrificial dielectric layer 122 and SSL silicon nitride layer 123.As shown in fig. le, oxide isolation layer inwall and source electrode groove sequentially form electron trapping layer 350, barrier oxide layer 360 and grid 370.
Therefore, in existing 3DNAND flash memory structure, GSL selects pipe and SSL to select Guan Jun to include silicon nitride electron trapping layer, cause in the real work of circuit, SSL selects pipe and GSL to select pipe also can inevitably have slight electric charge storage and release, cause the threshold voltage vt drift selecting pipe, ultimately result in On current change and close continuous leaky.Particularly in particularly after memory device read-write repeatedly, this phenomenon becomes apparent from, and then causes the reading of memory element to lose efficacy.
For the problems referred to above, the invention provides the manufacture method of a kind of 3DNAND flash memory structure, the method adopts polysilicon layer to replace selecting the silicon nitride sacrificial layers in pipe, make to select pipe to include polysilicon layer and tunnel oxide, and do not include electron trapping layer silicon nitride, avoid the threshold voltage shift phenomenon selecting pipe, improve the quality of memory device.
Embodiment one
Based on above description, the embodiment of the present invention one provides following solution.
Fig. 2 is the schematic flow sheet of the manufacture method of the 3DNAND flash memory structure of offer in the embodiment of the present invention, as in figure 2 it is shown, the method may comprise steps of:
Step 21, offer substrate, and on substrate, sequentially form grid oxic horizon, GSL polysilicon layer; multiple stacking oxide isolation layers and sacrificial dielectric layer, SSL polysilicon layer, and protection oxide layer; wherein, described sacrificial dielectric layer is formed between adjacent oxide isolation layer；
Step 22, etching form the cylindrical channel exposing substrate；
Step 23, in described cylindrical channel, sequentially form tunnel oxide, polysilicon and polysilicon spacer medium layer；
Step 24, etching form the source electrode groove exposing substrate, and form public source；
Step 25, wet etching remove described sacrificial dielectric layer；
Step 26, sequentially form electron trapping layer and barrier oxide layer at sidewall and the oxide isolation layer inwall of described source electrode groove；
Step 27, barrier oxide layer surface formed grid.
The present embodiment is sequentially forming grid oxic horizon on substrate; GSL polysilicon layer; multiple stacking oxide isolation layers and sacrificial dielectric layer; SSL polysilicon layer and protection oxide layer; that is, the method adopts polysilicon to replace selecting the silicon nitride in pipe, it is to avoid selection pipe includes electron trapping layer silicon nitride; thus avoiding the threshold voltage shift phenomenon selecting pipe, improve the quality of memory device.
The manufacture method of the 3DNAND flash memory structure provided in present aspect is provided in detail below.
With reference to shown in Fig. 3 a, cleaning and provide substrate 300, on substrate 300, growth is aboutGrid oxic horizon 311, on described grid oxic horizon 311, growth is aboutGSL polysilicon layer 321, and adopt chemical vapour deposition (CVD) (ChemicalVaporDeposition, CVD) the technology 321 multiple stacking oxide isolation layers 312 of generation and sacrificial dielectric layer 322 on described GSL polysilicon layer, wherein, described sacrificial dielectric layer 322 is formed between adjacent oxide isolation layer 312, and oxide isolation layer 312 can beSilicon oxide, sacrificial dielectric layer 322 can beSilicon nitride.
The number of plies of sacrificial dielectric layer and oxide isolation layer is not especially limited by the present invention, it is possible to according to needing to be designed to 8,16,32,48 and 64 layers etc. to memory element capacity.In the present embodiment, 2 layers is example.
It addition, grow on uppermost oxide isolation layer 312SSL polysilicon layer 323, and growth thickness is on described SSL polysilicon layer 323Protection oxide layer 313.
Shown in reference Fig. 3 b and Fig. 3 c, repeatedly photoetching and multiple etching, and etching is all parked on polysilicon or silicon nitride every time, forms building trapezoidal groove；In described building trapezoidal groove, also form backfill oxide layer 314, to fill described building trapezoidal groove, and described backfill oxide layer is carried out cmp (ChemicalMechanicalPolishing, CMP) process, make described backfill oxide layer have smooth surface.
With reference to shown in Fig. 3 d; successively to protection oxide layer, SSL polysilicon layer 323, multiple stacking sacrificial dielectric layer 322 and oxide isolation layer; GSL polysilicon layer 321; and grid oxic horizon is patterned process, form the cylindrical channel cylindrical channel (Channelhole) 330 exposing substrate.
With reference to, shown in Fig. 3 e, adopting ald (AtomicLayerDeposition, ALD) to be formed in trench sidewallsTunnel oxide 331, and adopt sidewall etching technics remove trench bottom tunnel oxide 331, expose described substrate 300.
With reference to, shown in Fig. 3 f, forming polysilicon 332 and polysilicon spacer medium layer 333 on the surface of described tunnel oxide 331.Concrete, it is possible to formed on the surface of tunnel oxide 331Polysilicon, subsequently formPolysilicon spacer medium layer 333, and polysilicon spacer medium layer 333 is etched back to process, make the height of described polysilicon spacer medium layer 333 lower than the height of described raceway groove, again formed subsequentlyPolysilicon, and this polysilicon is carried out CMP process, removes the polysilicon above raceway groove, make polysilicon layer 332 and filling oxide layer 314 contour.Wherein, the material of described polysilicon spacer medium layer 333 can be silicon oxide.
With reference to shown in Fig. 3 g, dry etching (Dryetch) technique is adopted to form the source electrode groove (Slit) 340 exposing substrate 300, and adopt ion implantation to adulterate in the silicon substrate 300 exposed N+, form public source (CommonSourceLine, CSL) 350.
With reference to, shown in Fig. 3 h, adopting hot phosphoric acid etching to remove described sacrificial dielectric layer 322.It is to be noted that, owing to GSL selects the material of tube layer 321 and SSL selection tube layer 323 to be polysilicon, and the material of sacrificial dielectric layer 322 is silicon nitride, therefore in hot phosphoric acid corrosion sacrificial dielectric layer process, GSL selects tube layer 321 and SSL to select tube layer 323 not all to be corroded.
With reference to shown in Fig. 3 i, the sidewall at oxide isolation layer inwall and source electrode groove 340 is formedElectron trapping layer silicon nitride 350, and the surface of described electron trapping layer silicon nitride 350 formedBarrier oxide layer 360, wherein the material of barrier oxide layer 360 can be silicon oxide, therefore, defines ONO (oxide-nitride-oxide) dielectric layer of memory element.
With reference to, shown in Fig. 3 j, forming grid 370 on the surface of described barrier oxide layer 360.Concrete, grow up successively in the surface of described barrier oxide layer 360 and form alumina layer, titanium nitride layer and tungsten layer, form tungsten grid 370.
In the flash memory structure that the 3DNAND manufacture method provided in the embodiment of the present invention prepares, GSL selects pipe/SSL to select the structure that pipe is formed to be polycrystalline silicon/oxidative silicon/polysilicon, and the structure of memory element is tungsten (grid)/silicon oxide/silicon nitride/silicon oxide/polysilicon, that is, GSL selects pipe and SSL to select Guan Zhongjun not include electron trapping layer silicon nitride.Therefore, this flash memory structure avoids and selects pipe trapped electron and the threshold voltage shift phenomenon that causes and leaky, improves the quality of 3DNAND flash memory.
The embodiment of the present invention also provides for a kind of 3DNAND flash memory structure, and the manufacture method of the 3DNAND flash memory structure that described 3DNAND flash memory structure can be provided by any embodiment of the present invention prepares.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute without departing from protection scope of the present invention.Therefore, although the present invention being described in further detail by above example, but the present invention is not limited only to above example, when without departing from present inventive concept, other Equivalent embodiments more can also be included, and the scope of the present invention is determined by appended right.
Claims (10)
1. the manufacture method of a 3DNAND flash memory structure, it is characterised in that including:
Substrate is provided, and on substrate, sequentially forms grid oxic horizon, drain selection pipe polysilicon layer; multiple stacking oxide isolation layers and sacrificial dielectric layer, drain electrode selects pipe polysilicon layer and protection oxide layer; wherein, described sacrificial dielectric layer is formed between adjacent oxide isolation layer；
Etching forms the cylindrical channel exposing substrate；
Tunnel oxide, polysilicon and polysilicon spacer medium layer is sequentially formed in described cylindrical channel；
Etching forms the source electrode groove exposing substrate, and forms public source；
Wet etching removes described sacrificial dielectric layer；
Sidewall and oxide isolation layer inwall at described source electrode groove sequentially form electron trapping layer and barrier oxide layer；
Grid is formed on barrier oxide layer surface.
2. method according to claim 1, it is characterised in that sequentially form tunnel oxide, polysilicon and polysilicon spacer medium layer in described cylindrical channel, including:
Adopt atom layer deposition process to form tunnel oxide in trench sidewalls, and etch away the tunnel oxide of trench bottom；
Form polysilicon on the surface of described tunnel oxide, and be internally formed polysilicon spacer medium layer at described polysilicon.
3. method according to claim 1, it is characterised in that etching forms the source electrode groove exposing substrate, and forms public source, including:
Dry etch process is adopted to form the source electrode groove exposing substrate；
Adopt ion implantation that the substrate exposed is adulterated, form public source.
4. method according to claim 1, it is characterised in that etching removes described sacrificial dielectric layer, including:
Hot phosphoric acid etching is adopted to remove described sacrificial dielectric layer.
5. method according to claim 1, it is characterised in that etching also includes before forming the cylindrical channel exposing substrate:
Repeatedly photoetching and multiple etching, forms building trapezoidal groove；
In described building trapezoidal groove, form backfill oxide layer, and described backfill oxide layer is carried out cmp process.
6. method according to claim 1, it is characterised in that form grid on barrier oxide layer surface, including:
Alumina layer, titanium nitride layer and tungsten layer is sequentially formed on described barrier oxide layer surface.
7. method according to claim 1, it is characterised in that described drain selection pipe polysilicon layer and described drain electrode select the thickness of pipe polysilicon layer to be
8. method according to claim 1, it is characterised in that the thickness of described tunnel oxide is
9. method according to claim 1, it is characterised in that the thickness of described electron trapping layer isThe thickness of described barrier oxide layer is
10. a 3DNAND flash memory structure, it is characterised in that the manufacture method described in any one of claim 1-9 prepares.
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107482017A (en) * | 2017-08-22 | 2017-12-15 | 长江存储科技有限责任公司 | A kind of preparation technology in 3D nand flash memories raceway groove hole |
| CN107808884A (en) * | 2016-08-24 | 2018-03-16 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of three dimensional NAND flush memory device |
| CN112038349A (en) * | 2020-09-08 | 2020-12-04 | 长江存储科技有限责任公司 | Method for forming channel hole of three-dimensional memory device and three-dimensional memory device |
| CN112164696A (en) * | 2020-09-24 | 2021-01-01 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN113053904A (en) * | 2021-03-15 | 2021-06-29 | 维沃移动通信有限公司 | Three-dimensional flash memory structure and electronic equipment |
| WO2021127980A1 (en) * | 2019-12-24 | 2021-07-01 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional nand memory device and method of forming the same |
| CN113454780A (en) * | 2021-05-28 | 2021-09-28 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of forming the same |
| CN113871486A (en) * | 2021-09-27 | 2021-12-31 | 北京大学 | Multi-floating-gate laminated type synaptic transistor and preparation method thereof |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100213538A1 (en) * | 2009-02-25 | 2010-08-26 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing the same |
| KR20120041314A (en) * | 2010-10-21 | 2012-05-02 | 삼성전자주식회사 | Vertical memory devices and methods of manufacturing the same |
| US20120276696A1 (en) * | 2011-04-29 | 2012-11-01 | Yang Jun-Kyu | Vertical structure non-volatile memory device and method of manufacturing the same |
| CN102867830A (en) * | 2011-07-06 | 2013-01-09 | 爱思开海力士有限公司 | Non-volatile memory device and method of manufacturing the same |
| KR20130027154A (en) * | 2011-09-07 | 2013-03-15 | 삼성전자주식회사 | Three dimensional semiconductor device and method of fabricating the same |
| CN103066076A (en) * | 2011-10-24 | 2013-04-24 | 爱思开海力士有限公司 | 3-D nonvolatile memory device and method of manufacturing same, and memory system |
| CN103117293A (en) * | 2011-10-26 | 2013-05-22 | 爱思开海力士有限公司 | 3-D nonvolatile memory devices and methods of manufacturing the same |
| CN103680611A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | 3D (three-dimensional) NAND memory and manufacturing method thereof |
-
2014
- 2014-12-31 CN CN201410854359.5A patent/CN105810639B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100213538A1 (en) * | 2009-02-25 | 2010-08-26 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device and method of manufacturing the same |
| KR20120041314A (en) * | 2010-10-21 | 2012-05-02 | 삼성전자주식회사 | Vertical memory devices and methods of manufacturing the same |
| US20120276696A1 (en) * | 2011-04-29 | 2012-11-01 | Yang Jun-Kyu | Vertical structure non-volatile memory device and method of manufacturing the same |
| CN102867830A (en) * | 2011-07-06 | 2013-01-09 | 爱思开海力士有限公司 | Non-volatile memory device and method of manufacturing the same |
| KR20130027154A (en) * | 2011-09-07 | 2013-03-15 | 삼성전자주식회사 | Three dimensional semiconductor device and method of fabricating the same |
| CN103066076A (en) * | 2011-10-24 | 2013-04-24 | 爱思开海力士有限公司 | 3-D nonvolatile memory device and method of manufacturing same, and memory system |
| CN103117293A (en) * | 2011-10-26 | 2013-05-22 | 爱思开海力士有限公司 | 3-D nonvolatile memory devices and methods of manufacturing the same |
| CN103680611A (en) * | 2012-09-18 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | 3D (three-dimensional) NAND memory and manufacturing method thereof |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107808884A (en) * | 2016-08-24 | 2018-03-16 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of three dimensional NAND flush memory device |
| CN107482017A (en) * | 2017-08-22 | 2017-12-15 | 长江存储科技有限责任公司 | A kind of preparation technology in 3D nand flash memories raceway groove hole |
| WO2021127980A1 (en) * | 2019-12-24 | 2021-07-01 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional nand memory device and method of forming the same |
| US11587945B2 (en) | 2019-12-24 | 2023-02-21 | Yangtze Memory Technologies Co., Ltd. | Three-dimensional NAND memory device with reduced RC delay |
| CN112038349A (en) * | 2020-09-08 | 2020-12-04 | 长江存储科技有限责任公司 | Method for forming channel hole of three-dimensional memory device and three-dimensional memory device |
| CN112164696A (en) * | 2020-09-24 | 2021-01-01 | 长江存储科技有限责任公司 | Three-dimensional memory and manufacturing method thereof |
| CN113053904A (en) * | 2021-03-15 | 2021-06-29 | 维沃移动通信有限公司 | Three-dimensional flash memory structure and electronic equipment |
| CN113454780A (en) * | 2021-05-28 | 2021-09-28 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of forming the same |
| CN113871486A (en) * | 2021-09-27 | 2021-12-31 | 北京大学 | Multi-floating-gate laminated type synaptic transistor and preparation method thereof |
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