CN105810683A - 3D NAND flash memory structure and manufacturing method therefor - Google Patents
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- 230000015654 memory Effects 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 61
- 238000000034 method Methods 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000005468 ion implantation Methods 0.000 claims abstract description 18
- 238000002955 isolation Methods 0.000 claims description 45
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 25
- 229920005591 polysilicon Polymers 0.000 claims description 25
- 230000004888 barrier function Effects 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 11
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 6
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 3
- 238000010893 electron trap Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract 4
- 238000007254 oxidation reaction Methods 0.000 abstract 4
- 238000005516 engineering process Methods 0.000 description 16
- 238000000605 extraction Methods 0.000 description 9
- 239000002699 waste material Substances 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 239000010937 tungsten Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- OKZIUSOJQLYFSE-UHFFFAOYSA-N difluoroboron Chemical compound F[B]F OKZIUSOJQLYFSE-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000001259 photo etching Methods 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 210000004744 fore-foot Anatomy 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- -1 grid is formed Chemical compound 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Abstract
The invention discloses a 3D NAND flash memory structure and a manufacturing method therefor. The method comprises the steps: providing a substrate, and forming a plurality of array string units on the surface of the substrate, wherein a source trench which enables the substrate to be exposed is disposed between the array string units, and each array string unit comprises a plurality of stacked oxidation dielectric layers and sacrificial dielectric layers; carrying out the ion implantation of the exposed substrate in the source trench, and forming a public source electrode; carrying out the etching removal of the sacrificial dielectric layers, forming grid electrodes on inner walls of the oxidation dielectric layers, and forming a second oxidation dielectric layer in the source trench; carrying out the etching of the second oxidation dielectric layer at the bottom of the source trench, the public source electrode and the substrate, and forming a P-well connection trench; carrying out the ion implantation of the substrate exposed in the P-well connection trench, and forming P+; and forming trench leads in the P-well connection trench and the source trench. The method employs self-aligning ion implantation method to form P+ and N+ in all source trenches, saves the production cost, and improves the stability and reliability of a circuit.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to the manufacture method of a kind of 3DNAND flash memory structure and this 3DNAND flash memory structure.
Background technology
Along with the fast development of flash memories, three-dimensional (3D) flash memories structure obtains and develops rapidly, and 3DNAND flash memory has been widely used in semiconductor device.
In existing 3DNAND flash memory structure, in order to the P type heavy doping of p-well (well) substrate is drawn, it is necessary to perform twice ion implantation technology after etching forms source electrode groove.Concrete, first adopt self-registered technology to carry out N-type (phosphorus P or arsenic As) ion implanting and form public source (CommonSourceLine, CSL)；Then, P type heavy doping is formed needing to carry out P type photoetching and P type (boron or boron difluoride BF2) ion implanting in by P+ another region drawn.
In above-mentioned manufacture method, P type photoetching process is by the minimum lithographic scope in ion implantation technologyAnd the restriction of alignment precision, and in order to meet the needs of circumferential channel layout, cause adopting self-registered technology to carry out P type ion implanting, what is more important, two, the left and right adjacent with this P type groove raceway groove has lacked side common source, therefore these two raceway grooves can not effectively be drawn, thus two, the left and right raceway groove adjacent with p-well groove need to be sacrificed into sky raceway groove (dummystrip).Therefore, in highdensity 3DNAND storage chip, waste considerable area, considerably increase cost of manufacture.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of 3DNAND flash memory structure and preparation method thereof, to reduce the production cost of 3DNAND storage chip, and improves stability and the reliability of circuit work.
On the one hand, embodiments provide the manufacture method of a kind of 3DNAND flash memory structure, including:
Substrate is provided, described substrate surface is formed with multiple array strings unit, the source electrode groove exposing described substrate it is provided with between described array strings unit, described array strings unit includes polysilicon, polysilicon spacer medium layer and multiple the first stacking oxide isolation layer and sacrificial dielectric layer, described polysilicon spacer medium layer is formed at the inside of described polysilicon, described sacrificial dielectric layer is formed between the first adjacent oxide isolation layer, and the plurality of the first oxide isolation layer being staggeredly stacked and sacrificial dielectric layer are positioned at the both sides of described polysilicon；
The substrate exposed in source electrode groove is carried out ion implanting, forms public source；
Etching removes described sacrificial dielectric layer, and forms grid at oxide isolation layer inwall, and forms the second oxide isolation layer in source electrode groove；
Second oxide isolation layer of etching source channel bottom, public source and substrate, form p-well and connect groove；
Described p-well is connected the substrate exposed in groove and carries out ion implanting, form P type heavy doping；
Connect in described p-well and in groove and described source electrode groove, form groove lead-in wire.
Further, the degree of depth of described p-well connection groove is
Further, described p-well is connected the substrate exposed in groove and carries out ion implanting, form P type heavy doping, including:
Adopt autoregistration ion implantation, described p-well is connected the substrate exposed in groove and carries out P type ion implanting, form P type heavy doping.
Further, the second oxide isolation layer of etching source channel bottom, public source and substrate, form p-well and connect groove, including:
Adopt dry etch process that the second oxide isolation layer of source electrode channel bottom, public source and substrate are performed etching, form described p-well and connect groove.
Further, connect in described p-well and in groove and described source electrode groove, form groove lead-in wire, including:
Connect in described p-well and in groove and described source electrode groove, sequentially form adhesion layer and groove lead-in wire.
Further, etching removes described sacrificial dielectric layer, and forms grid at the first oxide isolation layer inwall, including:
Hot phosphoric acid etching is adopted to remove described sacrificial dielectric layer；
Electron trapping layer and barrier oxide layer is sequentially formed at the first oxide isolation layer inwall；
Grid is formed on barrier oxide layer surface.
Further, form grid on barrier oxide layer surface, including: sequentially form gate blocks layer, adhesion layer and grid layer on described barrier oxide layer surface.
Further, the thickness of described second oxide isolation layer is
On the other hand, the embodiment of the present invention additionally provides a kind of 3DNAND flash memory structure, and the manufacture method of the 3DNAND flash memory structure that described 3DNAND flash memory structure is provided by any embodiment of the present invention prepares.
3DNAND flash memory structure that the embodiment of the present invention provides and preparation method thereof, after etching forms source electrode groove, adopts the autoregistration ion implantation substrate to exposing in source electrode groove to carry out N-type ion implanting, forms public source (N+)；In follow-up removal sacrificial dielectric layer, form grid and after forming the second oxide isolation layer in source electrode groove, the same area is carried out P type ion implanting and forms P type heavy doping (P+)；And growth groove lead-in wire in groove and source electrode groove is connected in p-well, N+ and P+ is drawn.In the method, it is possible to adopt autoregistration ion implantation to form P+, not by the restriction of the minimum lithographic scope in ion implantation technology and alignment precision, therefore need not sacrifice extra groove, also just be absent from the waste of any area, be greatly saved production cost；Additionally, owing to each groove has the P+ of p-well substrate to draw, the P+ of a p-well substrate is just had to draw every thousands of grooves of hundreds of in compared to existing technology, improve intensive and the uniformity of the P+ extraction of p-well substrate, thus improve extraction effect, and then improve stability and the reliability of circuit work.
Accompanying drawing explanation
By reading the detailed description that non-limiting example is made made with reference to the following drawings, the other features, objects and advantages of the present invention will become more apparent upon:
Fig. 1 a-Fig. 1 d is the schematic diagram of 3DNAND flash memory structure manufacture method of the prior art；
The schematic flow sheet of the Fig. 2 3DNAND flash memory structure manufacture method for providing in the embodiment of the present invention；
Fig. 3 a-Fig. 3 f is the schematic diagram of the 3DNAND flash memory structure manufacture method provided in the embodiment of the present invention one.
Detailed description of the invention
Below in conjunction with drawings and Examples, the present invention is described in further detail.It is understood that specific embodiment described herein is used only for explaining the present invention, but not limitation of the invention.It also should be noted that, for the ease of describing, accompanying drawing illustrate only part related to the present invention but not full content.
Fig. 1 a-Fig. 1 d is the schematic diagram of 3DNAND flash memory structure manufacture method of the prior art.As shown in Figure 1a, existing manufacture method, substrate 100 is provided, described substrate 100 surface is formed with multiple array strings unit, the source electrode groove 140 exposing described substrate 100 it is provided with between described array strings unit, wherein, described array strings unit includes polysilicon 130, polysilicon spacer medium layer 131 and multiple the first stacking oxide isolation layer 110 and sacrificial dielectric layer 120, described polysilicon spacer medium layer 131 is formed at the inside of described polysilicon 130, described sacrificial dielectric layer 120 is formed between the first adjacent oxide isolation layer 110, the plurality of the first oxide isolation layer 110 being staggeredly stacked and sacrificial dielectric layer 120 are positioned at the both sides of described polysilicon 130.
As shown in Figure 1 b, adopt the substrate 100 that autoregistration ion implantation technology is exposed bottom part source electrode groove 140 to carry out N-type ion implanting, form public source 150.It should be noted that source electrode groove top in another area has photoresist 191 to block phosphorus or arsenic ion, the source electrode groove being now blocked will not form public source.
As illustrated in figure 1 c, carry out P type photoetching, retain the photoresist 192 above source electrode groove in this forefoot area, expose the source electrode groove 140 in another region, and the substrate 100 exposed bottom this source electrode groove 140 carries out P type ion implanting, forms P type heavy doping 170.It should be noted that in ion implantation technology, minimum lithographic ranges forTherefore two adjacent with this source electrode groove raceway grooves are not photo-etched glue 192 and block completely, make to be also injected into part P type ion in two raceway grooves adjacent with this source electrode groove, what is more important, two, the left and right adjacent with this source electrode groove raceway groove has lacked side common source, therefore these two raceway grooves can not effectively be drawn, and causes that the two raceway groove becomes sky groove.
In conjunction with Fig. 1 c and Fig. 1 d, etching removes described sacrifice layer 120, and forms tungsten grid 160, also forms the second oxide isolation layer 111 at source electrode trenched side-wall, and forms groove lead-in wire 161 in remaining source electrode groove, with by groove lead-in wire 161 extraction N+ or P+.
Therefore, in the manufacture method of existing 3DNAND flash memory structure, by the restriction of minimum lithographic scope and alignment precision in ion implantation technology, self-registered technology can not be adopted when P type ion implanting, and two adjacent empty grooves need to be sacrificed, and causing substantial amounts of waste, cost of manufacture is higher.It addition, prior art just has the P+ of a p-well substrate to draw every thousands of grooves of hundreds of, reducing intensive and the uniformity of the P+ extraction of p-well substrate, thus reducing extraction effect, and then have impact on stability and the reliability of circuit work.
For the problems referred to above, the invention provides the manufacture method of a kind of 3DNAND flash memory structure, the method is after forming public source, form p-well in substrate interior and connect groove, and the same area is carried out the formation P type heavy doping of P type ion implanting, and growth groove lead-in wire in groove and source electrode groove is connected in p-well, N+ and P+ is drawn.The method adopts autoregistration ion implantation form P type heavy doping, it is to avoid the waste of raceway groove, be greatly saved production cost；It addition, the groove lead-in wire in each source electrode groove can draw N+ and P+, improve intensive and the uniformity of the P+ extraction of p-well substrate, thus improve extraction effect, and then improve stability and the reliability of circuit work.
Embodiment one
Based on above description, the embodiment of the present invention one provides following solution.
Fig. 2 is the schematic flow sheet of the manufacture method of the 3DNAND flash memory structure of offer in the embodiment of the present invention, as in figure 2 it is shown, the method may comprise steps of:
Step 21, offer substrate, described substrate surface is formed with multiple array strings unit, the source electrode groove exposing described substrate it is provided with between described array strings unit, described array strings unit includes polysilicon, polysilicon spacer medium layer and multiple the first stacking oxide isolation layer and sacrificial dielectric layer, described polysilicon spacer medium layer is formed at the inside of described polysilicon, described sacrificial dielectric layer is formed between the first adjacent oxide isolation layer, and the plurality of the first oxide isolation layer being staggeredly stacked and sacrificial dielectric layer are positioned at the both sides of described polysilicon；
Step 22, ion implanting that the substrate exposed in source electrode groove is carried out, form public source；
Step 23, etching remove described sacrificial dielectric layer, and form grid at oxide isolation layer inwall, and form the second oxide isolation layer in source electrode groove；
Step 24, the second oxide isolation layer of etching source channel bottom, public source and substrate, form p-well and connect groove；
Step 25, described p-well is connected in groove the substrate exposed carry out ion implanting, form P type heavy doping；
Step 26, connect in described p-well and in groove and described source electrode groove, form groove lead-in wire.
The present embodiment is after adopting ion implantation to form public source, form grid and p-well connect groove, and the substrate exposed in described p-well connection groove is carried out ion implanting, form P type heavy doping, and connect formation groove lead-in wire in groove and described source electrode groove in described p-well.Owing to being each formed with public electrode and P type heavy doping in each source electrode groove, it is possible to adopt autoregistration ion implantation technology to form P type heavy doping, it is to avoid the waste of source electrode groove, reduce cost of manufacture；It addition, improve intensive and the uniformity of groove lead-in wire, and then improve stability and the reliability of circuit work.
The manufacture method of the 3DNAND flash memory provided in the present invention is provided in detail below.
With reference to shown in Fig. 3 a, clean and substrate 300 is provided, multiple array strings unit is formed at described substrate surface, the source electrode groove 340 exposing described substrate 300 it is provided with between described array strings unit, described array strings unit includes polysilicon 330, polysilicon spacer medium layer 331 and multiple the first stacking oxide isolation layer 310 and sacrificial dielectric layer 320, described polysilicon spacer medium layer 331 is formed at the inside of described polysilicon 330, described sacrificial dielectric layer 320 is formed between the first adjacent oxide isolation layer 310, the plurality of the first oxide isolation layer 310 being staggeredly stacked and sacrificial dielectric layer 320 are positioned at the both sides of described polysilicon 330.
Wherein, described array strings unit also includes the grid oxic horizon 311 being positioned at bottom and the protection oxide layer 312 being positioned at top layer.
With reference to, shown in Fig. 3 b, adopting autoregistration ion implantation that the substrate 300 exposed in source electrode groove 340 carries out ion implanting, form public source 350, the ion wherein injected can be phosphorus or arsenic.It should be noted that the substrate 300 of now each source electrode groove 340 bottom-exposed is each formed with public electrode 350.
In conjunction with Fig. 3 b and Fig. 3 c, etching removes described sacrificial dielectric layer 320, and forms grid 360 at the first oxide isolation layer 311 inwall, and forms the second oxide isolation layer 311 in source electrode groove 340.Concrete, hot phosphoric acid etching can be adopted to remove described sacrificial dielectric layer silicon nitride 320, sequentially form electron trapping layer silicon nitride (not shown) and barrier oxide layer (not shown) at the first oxide isolation layer 311 inwall, and form grid 360 on described barrier oxide layer surface.Wherein, when forming grid on barrier oxide layer surface, specifically may include that and sequentially form gate blocks layer ALO, adhesion layer TiN and tungsten gate layer on described barrier oxide layer surface.
Subsequently, also it is etched back to tungsten grid process, removes the tungsten in source electrode groove 340, expose source electrode groove 340.Forming the second oxide isolation layer 311 in sidewall and the bottom of described source electrode groove 340, the thickness of described second oxide isolation layer 311 is
Shown in reference Fig. 3 d, the second oxide isolation layer 311 of etching source channel bottom, public source 350 and substrate 300, remove the second oxide isolation layer 311 of source electrode channel bottom, and form p-well connection groove 341.Concrete, the second oxide isolation layer 311 of sidewall (Spacer) silicon dioxide dry etch process etching source channel bottom, public source 350 and substrate 300 can be adopted, remove the second oxide isolation layer 311 of source electrode channel bottom, and form p-well connection groove 341.Wherein, the degree of depth of described p-well connection groove 341 isNamely the substrate 300 being etched away is approximately
With reference to, shown in Fig. 3 e, each source electrode groove 340 being carried out P type photoetching, and the substrate exposed in described p-well connection groove is carried out P type ion implanting, form P type heavy doping 370, wherein, the ion of injection can be (boron or boron difluoride BF2), forms P type heavy doping.It should be noted that the substrate 300 of now each source electrode groove 340 bottom-exposed is each formed with P type heavy doping 370.
It should be noted that public source 350 and P type heavy doping 370 are respectively positioned on substrate 300 inside.
Shown in reference Fig. 3 e, adopt chemical vapour deposition (CVD) (ChemicalVaporDeposition, CVD) technology to connect in described p-well in groove and described source electrode groove and form groove lead-in wire 361, with by groove lead-in wire 361 extraction N+350 and P+370.Concrete, connect in described p-well and in groove and described source electrode groove, sequentially form adhesion layer TiN and tungsten groove lead-in wire.
To sum up, in the 3DNAND manufacture method provided in the embodiment of the present invention, after etching forms source electrode groove, namely carry out the autoregistration ion implanting of normal CSLN type, form public source.Remove in subsequent silicon nitride, grid is formed, tungsten returns quarter, sidewall silicon dioxide growth and adopts sidewall etching technics to form the autoregistration ion implanting carrying out secondary p-well substrate P+ after p-well connects groove again at the same area, the last lead-in wire of CVD growth groove again, is drawn CSLN+ and P+ by groove lead-in wire simultaneously.The method can adopt autoregistration ion implantation technology form P+, not by the restriction of photolithographic minimum dimension and alignment precision, it is not necessary to waste extra empty groove, be also just absent from the waste of any area, be greatly saved cost.
Additionally, owing to there being the P+ of p-well substrate to draw in each source electrode groove, the P+ of a p-well substrate is just had to draw every thousands of source electrode grooves of hundreds of compared to existing technology, the extraction of the obvious present invention is more dense, uniform, better draw effect it is thus possible to have, improve stability and the reliability of circuit work.
The embodiment of the present invention also provides for a kind of 3DNAND flash memory, and the manufacture method of the 3DNAND flash memory structure that described 3DNAND flash memory can be provided by any embodiment of the present invention prepares.
Note, above are only presently preferred embodiments of the present invention and institute's application technology principle.It will be appreciated by those skilled in the art that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute without departing from protection scope of the present invention.Therefore, although the present invention being described in further detail by above example, but the present invention is not limited only to above example, when without departing from present inventive concept, other Equivalent embodiments more can also be included, and the scope of the present invention is determined by appended right.
Claims (9)
1. the manufacture method of a 3DNAND flash memory structure, it is characterised in that including:
Substrate is provided, described substrate surface is formed with multiple array strings unit, the source electrode groove exposing described substrate it is provided with between described array strings unit, described array strings unit includes polysilicon, polysilicon spacer medium layer and multiple the first stacking oxide isolation layer and sacrificial dielectric layer, described polysilicon spacer medium layer is formed at the inside of described polysilicon, described sacrificial dielectric layer is formed between the first adjacent oxide isolation layer, and the plurality of the first oxide isolation layer being staggeredly stacked and sacrificial dielectric layer are positioned at the both sides of described polysilicon；
The substrate exposed in source electrode groove is carried out ion implanting, forms public source；
Etching removes described sacrificial dielectric layer, and forms grid at oxide isolation layer inwall, and forms the second oxide isolation layer in source electrode groove；
Second oxide isolation layer of etching source channel bottom, public source and substrate, form p-well and connect groove；
Described p-well is connected the substrate exposed in groove and carries out ion implanting, form P type heavy doping；
Connect in described p-well and in groove and described source electrode groove, form groove lead-in wire.
2. method according to claim 1, it is characterised in that described p-well connects the degree of depth of groove and is
3. method according to claim 1, it is characterised in that described p-well is connected the substrate exposed in groove and carries out ion implanting, form P type heavy doping, including:
Adopt autoregistration ion implantation, described p-well is connected the substrate exposed in groove and carries out P type ion implanting, form P type heavy doping.
4. method according to claim 1, it is characterised in that the second oxide isolation layer of etching source channel bottom, public source and substrate, forms p-well and connects groove, including:
Adopt dry etch process that the second oxide isolation layer of source electrode channel bottom, public source and substrate are performed etching, form described p-well and connect groove.
5. method according to claim 1, it is characterised in that connect in described p-well and form groove lead-in wire in groove and described source electrode groove, including:
Connect in described p-well and in groove and described source electrode groove, sequentially form adhesion layer and groove lead-in wire.
6. method according to claim 1, it is characterised in that etching removes described sacrificial dielectric layer, and forms grid at the first oxide isolation layer inwall, including:
Hot phosphoric acid etching is adopted to remove described sacrificial dielectric layer；
Electron trapping layer and barrier oxide layer is sequentially formed at the first oxide isolation layer inwall；
Grid is formed on barrier oxide layer surface.
7. method according to claim 1, it is characterised in that form grid on barrier oxide layer surface, including:
Gate blocks layer, adhesion layer and grid layer is sequentially formed on described barrier oxide layer surface.
8. method according to claim 1, it is characterised in that the thickness of described second oxide isolation layer is
9. a 3DNAND flash memory structure, it is characterised in that the manufacture method described in any one of claim 1-8 prepares.
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| CN105810683B (en) | 2019-05-28 |
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Address after: 502 / 15, building 1, 498 GuoShouJing Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee after: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 502 / 15, building 1, 498 GuoShouJing Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee before: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |