CN105810683B - A kind of 3D NAND flash memory structure and preparation method thereof - Google Patents
A kind of 3D NAND flash memory structure and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a kind of 3D NAND flash memory structures and preparation method thereof.This method comprises: providing substrate, substrate surface is formed with multiple array string locations, is equipped with the source electrode groove for exposing substrate between the array string location, array string location includes the first oxide isolation layer and sacrificial dielectric layer of multiple stackings；Ion implanting is carried out to the substrate exposed in source electrode groove, forms public source；Etching removal sacrificial dielectric layer, and grid is formed in oxide isolation layer inner wall, and the second oxide isolation layer is formed in source electrode groove；The second oxide isolation layer, public source and the substrate of etching source channel bottom form p-well and connect groove；Ion implanting is carried out to the substrate exposed in p-well connection groove, forms P+；It is connected in p-well and forms groove lead in groove and source electrode groove.P+ and N+ are respectively formed in each source electrode groove using autoregistration ion implantation, production cost has not only been saved, has also improved the stability and reliability of circuit.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of 3D NAND flash memory structure and the 3D NAND to dodge
The production method for depositing structure.
Background technique
With the fast development of flash memories, three-dimensional (3D) flash memories structure is rapidly developed, 3D NAND
Flash memory has been widely used in semiconductor devices.
In existing 3D NAND flash memory structure, in order to draw the p-type heavy doping of p-well (well) substrate, need etching
Ion implantation technology twice is executed after forming source electrode groove.Specifically, first carrying out N-type (phosphorus P or arsenic As) using self-registered technology
Ion implanting forms public source (Common Source Line, CSL)；Then, in another region for needing to draw P+
Interior progress p-type photoetching and p-type (boron or boron difluoride BF2) ion implanting form p-type heavy doping.
In above-mentioned production method, p-type photoetching process is by the minimum lithographic range in ion implantation technologyAnd alignment
The limitation of precision, and in order to meet the needs of circumferential channel layout, lead to that P-type ion note cannot be carried out using self-registered technology
Enter, it is even more important that left and right two channel adjacent with the p-type groove has lacked side common source, therefore two channels
It cannot effectively draw, thus need to be by the left and right two channel sacrifice adjacent with p-well groove at empty channel (dummy strip).Cause
This, wastes considerable area in highdensity 3D NAND storage chip, considerably increases cost of manufacture.
Summary of the invention
In view of this, the embodiment of the present invention provides a kind of 3D NAND flash memory structure and preparation method thereof, to reduce 3D
The production cost of NAND storage chip, and improve the stability and reliability of circuit work.
On the one hand, the embodiment of the invention provides a kind of production methods of 3D NAND flash memory structure, comprising:
Substrate is provided, the substrate surface is formed with multiple array string locations, is equipped with exposure between the array string location
The source electrode groove of the substrate out, the array string location include the of polysilicon, polysilicon spacer medium layer and multiple stackings
One oxide isolation layer and sacrificial dielectric layer, the polysilicon spacer medium layer are formed in the inside of the polysilicon, the sacrifice
Dielectric layer is formed between the first adjacent oxide isolation layer, and the multiple the first oxide isolation layer being staggeredly stacked and sacrifice are situated between
Matter layer is located at the two sides of the polysilicon；
Ion implanting is carried out to the substrate exposed in source electrode groove, forms public source；
Etching removes the sacrificial dielectric layer, and forms grid in oxide isolation layer inner wall, and formed in source electrode groove
Second oxide isolation layer；
The second oxide isolation layer, public source and the substrate of etching source channel bottom form p-well and connect groove；
Ion implanting is carried out to the substrate exposed in p-well connection groove, forms p-type heavy doping；
It is connected in the p-well and forms groove lead in groove and the source electrode groove.
Further, the depth of the p-well connection groove is
Further, ion implanting is carried out to the substrate exposed in p-well connection groove, forms p-type heavy doping, packet
It includes:
Using autoregistration ion implantation, P-type ion injection is carried out to the substrate exposed in p-well connection groove,
Form p-type heavy doping.
Further, the second oxide isolation layer, public source and the substrate of etching source channel bottom forms p-well connection
Groove, comprising:
It is carved using second oxide isolation layer, public source and substrate of the dry etch process to source electrode channel bottom
Erosion forms the p-well connection groove.
Further, it is connected in the p-well and forms groove lead in groove and the source electrode groove, comprising:
It is connected in groove and the source electrode groove in the p-well and sequentially forms adhesion layer and groove lead.
Further, etching removes the sacrificial dielectric layer, and forms grid in the first oxide isolation layer inner wall, comprising:
The sacrificial dielectric layer is removed using hot phosphoric acid etching；
Electron trapping layer and barrier oxide layer are sequentially formed in the first oxide isolation layer inner wall；
Grid is formed in barrier oxidation layer surface.
Further, grid is formed in barrier oxidation layer surface, comprising: sequentially form grid in the barrier oxidation layer surface
Pole barrier layer, adhesion layer and grid layer.
Further, the second oxide isolation layer with a thickness of
On the other hand, the embodiment of the invention also provides a kind of 3D NAND flash memory structure, the 3D NAND flash memory structures
The production method of the 3D NAND flash memory structure provided by any embodiment of that present invention is made.
3D NAND flash memory structure provided in an embodiment of the present invention and preparation method thereof, after etching forms source electrode groove,
N-type ion injection is carried out to the substrate exposed in source electrode groove using autoregistration ion implantation, is formed public source (N+)；
In subsequent removal sacrificial dielectric layer, form grid and in source electrode groove form the second oxide isolation layer after, to the same area
P-type ion is carried out to inject to form p-type heavy doping (P+)；And connected in p-well and grow groove lead in groove and source electrode groove, by N+
It is drawn with P+.In this method, P+ can be formed using autoregistration ion implantation, not by the minimum lithographic in ion implantation technology
The limitation of range and alignment precision, therefore do not need to sacrifice additional groove, the waste of any area is also just not present, significantly
Production cost is saved；In addition, since each groove has the P+ of p-well substrate to draw, compared to the prior art on several hundred
Thousand grooves just have the P+ of a p-well substrate to draw, and intensive and uniformity that the P+ of p-well substrate is drawn are improved, to mention
High extraction effect, and then improve the stability and reliability of circuit work.
Detailed description of the invention
By reading a detailed description of non-restrictive embodiments in the light of the attached drawings below, of the invention other
Feature, objects and advantages will become more apparent upon:
Fig. 1 a- Fig. 1 d is the schematic diagram of 3D NAND flash memory structure production method in the prior art；
Fig. 2 is the flow diagram of the 3D NAND flash memory structure production method provided in the embodiment of the present invention；
Fig. 3 a- Fig. 3 f is the schematic diagram of the 3D NAND flash memory structure production method provided in the embodiment of the present invention one.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
In description, only some but not all contents related to the present invention are shown in the drawings.
Fig. 1 a- Fig. 1 d is the schematic diagram of 3D NAND flash memory structure production method in the prior art.As shown in Figure 1a, existing
Some production methods, provide substrate 100, and 100 surface of substrate is formed with multiple array string locations, the array string location it
Between be equipped with and expose the source electrode groove 140 of the substrate 100, wherein the array string location includes polysilicon 130, polysilicon
The the first oxide isolation layer 110 and sacrificial dielectric layer 120 of spacer medium layer 131 and multiple stackings, the polysilicon spacer medium
Layer 131 is formed in the inside of the polysilicon 130, and the sacrificial dielectric layer 120 is formed in the first adjacent oxide isolation layer 110
Between, the multiple the first oxide isolation layer 110 being staggeredly stacked and sacrificial dielectric layer 120 are located at the two of the polysilicon 130
Side.
As shown in Figure 1 b, the substrate 100 exposed using autoregistration ion implantation technology in 140 bottom of part source electrode groove into
The injection of row N-type ion, forms public source 150.It should be noted that source electrode the top of the groove in another area has photoresist
191 block phosphorus or arsenic ion, not will form public source in the source electrode groove being blocked at this time.
As illustrated in figure 1 c, p-type photoetching is carried out, the photoresist 192 in this forefoot area above source electrode groove is retained, is exposed another
The source electrode groove 140 in region, and the substrate 100 exposed in 140 bottom of source electrode groove carries out P-type ion injection, forms p-type weight
Doping 170.It should be noted that minimum lithographic range is in ion implantation technologyTherefore adjacent with the source electrode groove
Two channels are not photo-etched glue 192 and block completely so that be also injected into two channels adjacent with the source electrode groove part p-type from
Son, it is even more important that left and right two channel adjacent with the source electrode groove has lacked side common source, therefore two channels
It cannot effectively draw, the two channels is caused to become empty groove.
In conjunction with Fig. 1 c and Fig. 1 d, etching removes the sacrificial layer 120, and forms tungsten grid 160, also in source electrode trenched side-wall shape
At the second oxide isolation layer 111, and groove lead 161 is formed in remaining source electrode groove, to draw by groove lead 161
N+ or P+.
Therefore, in the production method of existing 3D NAND flash memory structure, by minimum lithographic range in ion implantation technology with
And the limitation of alignment precision, self-registered technology cannot be used in P-type ion injection, and two adjacent empty grooves need to be sacrificed,
A large amount of waste is caused, cost of manufacture is higher.In addition, just having a p-well lining every several hundred thousands of a grooves in the prior art
The P+ at bottom is drawn, and is reduced intensive and uniformity that the P+ of p-well substrate is drawn, to reduce extraction effect, and then is influenced
The stability and reliability of circuit work.
In view of the above-mentioned problems, this method is forming public affairs the present invention provides a kind of production method of 3D NAND flash memory structure
After common source, p-well is formed in substrate interior and connects groove, and P-type ion is carried out to the same area and injects that form p-type heavily doped
It is miscellaneous, and connected in p-well and grow groove lead in groove and source electrode groove, N+ and P+ is drawn.In this method using autoregistration from
Sub- injection method forms p-type heavy doping, avoids the waste of channel, production cost is greatly saved；In addition, in each source electrode groove
Groove lead can draw N+ and P+, improve p-well substrate P+ draw intensive and uniformity, to improve extraction
Effect, and then improve the stability and reliability of circuit work.
Embodiment one
Based on above description, the embodiment of the present invention one provides following solution.
Fig. 2 is the flow diagram of the production method of the 3D NAND flash memory structure provided in the embodiment of the present invention, such as Fig. 2
Shown, this method may comprise steps of:
Step 21 provides substrate, and the substrate surface is formed with multiple array string locations, sets between the array string location
There is the source electrode groove for exposing the substrate, the array string location includes polysilicon, polysilicon spacer medium layer and multiple heaps
The first folded oxide isolation layer and sacrificial dielectric layer, the polysilicon spacer medium layer are formed in the inside of the polysilicon, institute
Sacrificial dielectric layer is stated to be formed between the first adjacent oxide isolation layer, the multiple the first oxide isolation layer being staggeredly stacked and
Sacrificial dielectric layer is located at the two sides of the polysilicon；
Step 22 carries out ion implanting to the substrate exposed in source electrode groove, forms public source；
Step 23, etching remove the sacrificial dielectric layer, and form grid in oxide isolation layer inner wall, and in source electrode groove
The second oxide isolation layer of interior formation；
The second oxide isolation layer, public source and the substrate of step 24, etching source channel bottom form p-well connection ditch
Slot；
Step 25 carries out ion implanting to the substrate exposed in p-well connection groove, forms p-type heavy doping；
Step 26 connects formation groove lead in groove and the source electrode groove in the p-well.
The present embodiment is after forming public source using ion implantation, and form grid connects groove with p-well, and to institute
It states the substrate exposed in p-well connection groove and carries out ion implanting, form p-type heavy doping, and connect groove and institute in the p-well
It states and forms groove lead in source electrode groove.Due to being each formed with public electrode and p-type heavy doping in each source electrode groove, can adopt
P-type heavy doping is formed with autoregistration ion implantation technology, the waste of source electrode groove is avoided, reduces the production cost；In addition, mentioning
The high intensive and uniformity of groove lead, and then improve the stability and reliability of circuit work.
The production method of 3D nand flash memory provided in the present invention is introduced in detail below.
With reference to shown in Fig. 3 a, substrate 300 is cleaned and provided, forms multiple array string locations in the substrate surface, it is described
Be equipped between array string location and expose the source electrode groove 340 of the substrate 300, the array string location include polysilicon 330,
The the first oxide isolation layer 310 and sacrificial dielectric layer 320 of polysilicon spacer medium layer 331 and multiple stackings, the polysilicon every
From the inside that dielectric layer 331 is formed in the polysilicon 330, the sacrificial dielectric layer 320 is formed in the first adjacent oxidation and is situated between
Between matter layer 310, the multiple the first oxide isolation layer 310 being staggeredly stacked and sacrificial dielectric layer 320 are located at the polysilicon
330 two sides.
Wherein, the array string location further includes that the grid oxic horizon 311 positioned at bottom and the protection positioned at top layer aoxidize
Layer 312.
With reference to shown in Fig. 3 b, using autoregistration ion implantation to the substrate 300 exposed in source electrode groove 340 carry out from
Son injection, forms public source 350, wherein the ion injected can be phosphorus or arsenic.It should be noted that each source electrode ditch at this time
The substrate 300 of 340 bottom-exposed of slot is each formed with public electrode 350.
In conjunction with Fig. 3 b and Fig. 3 c, etching removes the sacrificial dielectric layer 320, and in 311 inner wall shape of the first oxide isolation layer
At grid 360, and the second oxide isolation layer 311 is formed in source electrode groove 340.Specifically, can be gone using hot phosphoric acid etching
Except the sacrificial dielectric layer silicon nitride 320, electron trapping layer silicon nitride is sequentially formed (not in 311 inner wall of the first oxide isolation layer
Show) and barrier oxide layer (not shown), and grid 360 is formed in the barrier oxidation layer surface.Wherein, in barrier oxide layer
When surface forms grid, it can specifically include: sequentially forming gate blocks layer ALO, adhesion layer in the barrier oxidation layer surface
TiN and tungsten grid layer.
Then, processing also is etched back to tungsten grid, removes the tungsten in source electrode groove 340, expose source electrode groove 340.?
Second oxide isolation layer 311, the thickness of the second oxide isolation layer 311 are formed on the side wall of the source electrode groove 340 and bottom
For
With reference to shown in Fig. 3 d, the second oxide isolation layer 311, public source 350 and the substrate of etching source channel bottom
300, the second oxide isolation layer 311 of source electrode channel bottom is removed, and form p-well connection groove 341.Specifically, can use
The second oxide isolation layer 311, the public source of side wall (Spacer) silica dry etch process etching source channel bottom
350 and substrate 300, the second oxide isolation layer 311 of source electrode channel bottom is removed, and form p-well connection groove 341.Wherein, institute
State p-well connection groove 341 depth beThe substrate 300 being etched away is about
With reference to shown in Fig. 3 e, p-type photoetching is carried out to each source electrode groove 340, and connect in groove and expose to the p-well
Substrate carry out P-type ion injection, formed p-type heavy doping 370, wherein the ion of injection can be (boron or boron difluoride
BF2), p-type heavy doping is formed.It should be noted that the substrate 300 of each 340 bottom-exposed of source electrode groove is each formed with P at this time
Type heavy doping 370.
It should be noted that public source 350 and p-type heavy doping 370 are respectively positioned on inside substrate 300.
With reference to shown in Fig. 3 f, using chemical vapor deposition (Chemical Vapor Deposition, CVD) technology in institute
It states in p-well connection groove and the source electrode groove and forms groove lead 361, to draw N+350 and P+ by groove lead 361
370.Adhesion layer TiN and tungsten groove lead are sequentially formed specifically, connecting in groove and the source electrode groove in the p-well.
To sum up, it in the 3D NAND production method provided in the embodiment of the present invention, is carried out after etching forms source electrode groove
The autoregistration ion implanting of normal CSL N-type, forms public source.It is returned in subsequent silicon nitride removal, grid formation, tungsten
Quarter, side wall silicon dioxide growth are simultaneously formed after p-well connection groove using side wall etching technics again in the same area progress second
The autoregistration ion implanting of secondary p-well substrate P+, last CVD growth groove lead again, by groove lead by CSL N+ and P+
It draws simultaneously.P+ can be formed using autoregistration ion implantation technology in this method, not by photolithographic minimum dimension and alignment essence
The limitation of degree does not need the additional empty groove of waste, the waste of any area is also just not present, cost is greatly saved.
In addition, due to there is the P+ of p-well substrate extraction in each source electrode groove, compared with prior art every several hundred thousands of
Source electrode groove just has the P+ of a p-well substrate to draw, it is clear that extraction of the invention is more dense, uniform, preferably draws so as to have
Effect out improves the stability and reliability of circuit work.
The embodiment of the present invention also provides a kind of 3D nand flash memory, and the 3D nand flash memory can be by any implementation of the invention
The production method for the 3D NAND flash memory structure that example provides is made.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (9)
1. a kind of production method of 3D NAND flash memory structure characterized by comprising
P-well substrate is provided, the p-well substrate surface is formed with multiple array string locations, is equipped between the array string location sudden and violent
Expose the source electrode groove of the p-well substrate, the array string location include polysilicon, polysilicon spacer medium layer and it is multiple staggeredly
The the first oxide isolation layer and sacrificial dielectric layer, the polysilicon spacer medium layer stacked is formed in the inside of the polysilicon,
The sacrificial dielectric layer is formed between the first adjacent oxide isolation layer, the multiple the first oxide isolation layer being staggeredly stacked
It is located at the two sides of the polysilicon with sacrificial dielectric layer；
N-type ion injection is carried out to the p-well substrate exposed in source electrode groove, forms public source；
Etching removes the sacrificial dielectric layer, and forms grid in oxide isolation layer inner wall, and form second in source electrode groove
Oxide isolation layer；
The second oxide isolation layer, public source and the p-well substrate of etching source channel bottom form p-well and connect groove；
Ion implanting is carried out to the p-well substrate exposed in p-well connection groove, forms p-type heavy doping；
It is connected in the p-well and forms groove lead in groove and the source electrode groove.
2. the method according to claim 1, wherein the depth of p-well connection groove is
3. the method according to claim 1, wherein to the p-well substrate that exposes in p-well connection groove into
Row ion implanting forms p-type heavy doping, comprising:
Using autoregistration ion implantation, P-type ion injection, shape are carried out to the p-well substrate exposed in p-well connection groove
At p-type heavy doping.
4. the method according to claim 1, wherein the second oxide isolation layer of etching source channel bottom, public affairs
Common source and p-well substrate form p-well and connect groove, comprising:
It is performed etching using second oxide isolation layer, public source and p-well substrate of the dry etch process to source electrode channel bottom,
Form the p-well connection groove.
5. the method according to claim 1, wherein connecting shape in groove and the source electrode groove in the p-well
At groove lead, comprising:
It is connected in groove and the source electrode groove in the p-well and sequentially forms adhesion layer and groove lead.
6. the method according to claim 1, wherein etching removes the sacrificial dielectric layer, and in the first oxidation
Dielectric layer inner wall forms grid, comprising:
The sacrificial dielectric layer is removed using hot phosphoric acid etching；
Electron trapping layer and barrier oxide layer are sequentially formed in the first oxide isolation layer inner wall；
Grid is formed in barrier oxidation layer surface.
7. the method according to claim 1, wherein forming grid in barrier oxidation layer surface, comprising:
Gate blocks layer, adhesion layer and grid layer are sequentially formed in the barrier oxidation layer surface.
8. the method according to claim 1, wherein the second oxide isolation layer with a thickness of
9. a kind of 3D NAND flash memory structure, which is characterized in that be made by the described in any item production methods of claim 1-8.
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| CN107863305B (en) * | 2017-11-21 | 2020-03-27 | 长江存储科技有限责任公司 | Detection method of SONO etching process |
| CN110767656B (en) * | 2019-09-17 | 2023-06-16 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
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| CN103794619A (en) * | 2012-10-30 | 2014-05-14 | 爱思开海力士有限公司 | Variable resistance memory device |
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| KR101543331B1 (en) * | 2009-07-06 | 2015-08-10 | 삼성전자주식회사 | Method of fabricating vertical structure Non-volatile memory device having metal source line |
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| CN103794619A (en) * | 2012-10-30 | 2014-05-14 | 爱思开海力士有限公司 | Variable resistance memory device |
| CN104201176A (en) * | 2014-09-23 | 2014-12-10 | 武汉新芯集成电路制造有限公司 | 3D NAND flash structure and production method thereof |
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Address after: 502 / 15, building 1, 498 GuoShouJing Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee after: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee after: Zhaoyi Innovation Technology Group Co.,Ltd. Address before: 502 / 15, building 1, 498 GuoShouJing Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203 Patentee before: SHANGHAI GEYI ELECTRONIC Co.,Ltd. Patentee before: GIGADEVICE SEMICONDUCTOR(BEIJING) Inc. |