CN105448703A

CN105448703A - Etching method

Info

Publication number: CN105448703A
Application number: CN201410427703.2A
Authority: CN
Inventors: 杨芸
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2014-08-27
Filing date: 2014-08-27
Publication date: 2016-03-30
Anticipated expiration: 2034-08-27
Also published as: CN105448703B

Abstract

The invention discloses an etching method. With the method, the sidewall of a floating gate can be protected, and a good active region corner can be formed. The method comprises the steps of sequentially forming an action region, a tunnel oxide layer, a polycrystalline silicon layer and a mask layer on a substrate, forming grooves in the tunnel oxide layer, the polycrystalline silicon layer and the mask layer, forming a protective film on the sidewalls of the grooves, etching the active region, and removing the protective film.

Description

A kind of lithographic method

Technical field

The present invention relates to field of semiconductor manufacture, particularly relate to and can protect floating grid sidewall and the lithographic method forming angle, good active area and the product manufactured by the method.

Background technology

ETOX flash memory is the Erasable Programmable Read Only Memory EPROM (EPROM) of a type, wherein comprises thin tunnel oxide structure, is therefore called as " ETOX " (ElectronTunnelOxideDevice) flash memory.

In ETOX flash memory, floating grid (FG) for store electrons to realize " 1 " or " 0 ".Floating grid is formed by polysilicon usually.Along with the size of flash memory constantly reduces, floating grid length and active area (AA) width also constantly reduce.Therefore the size and dimension of floating grid and active area has a significant impact for the characteristic tool of flash memory.

Autoregistration shallow-trench isolation (STI) technology is a kind of method forming floating grid in floating grid-type flash memory.But, in actual manufacture process, find in the process of sti trench groove silicon etching, usually can cause damage to the sidewall of floating grid.

Figure 1A to Fig. 1 E shows the flow chart carrying out STI etching to polysilicon and active area in prior art.

After Figure 1A illustrates and is formed with source region 101 on a semiconductor substrate, form tunnel oxide 102, polysilicon layer 103 and silicon nitride layer 104, hard mask layer 105 successively on the active area.Then, hard mask 105 applies photoresist 106, carries out photoetching to form figure.Then, with photoresist 106 for mask, etch to form opening to hard mask layer 105, again to be with the hard mask layer 105 of opening for mask, etch nitride silicon layer 104, polysilicon layer 103 and tunnel oxide 102, with expose portion active area 101, finally remove hard mask layer 105, obtain semiconductor structure as shown in Figure 1B.

Then, as shown in Figure 1 C, active area 101 is etched, to form groove.

Then, as shown in figure ip, the flute surfaces exposed forms oxide liner 107.Such as, this oxide liner 107 is formed by boiler tube heated oxide.Finally, fill oxide in the trench, and carry out chemico-mechanical polishing to make wafer surface smooth.

But, under present technological conditions, in the process of sti trench groove silicon etching as shown in Figure 1 C, exposed polysilicon layer 103 is often consumed, this polysilicon layer 103 is typically used as floating grid in Subsequent semiconductor device manufacturing processes, therefore, the sidewall of process to floating grid of the sti trench groove silicon etching shown in Fig. 1 C causes damage.Make often there is very large error between the actual size of formed polysilicon layer 103 and design size, have a strong impact on the performance of flash memory.

Therefore, need a kind ofly can protect floating grid sidewall and form the process at angle, good active area in the manufacture process of semiconductor.

Summary of the invention

The object of this invention is to provide a kind of lithographic method, this lithographic method can be protected floating grid sidewall and form angle, good active area.

According to an aspect of the present invention, provide a kind of manufacturing method of semiconductor device, comprising: a) provide Semiconductor substrate, described Semiconductor substrate has active area and form tunnel oxide, polysilicon layer, mask layer successively on described active area; B) etching mask layer, polysilicon layer and tunnel oxide successively, forms groove; C) on described trenched side-wall, diaphragm is formed; D) continue the described active area of etching, form isolated groove; And e) remove described diaphragm.

According to an aspect of the present invention, in preceding method, step b) in using plasma etching technics, step c) described in diaphragm be execution step b) polymer of etch by-product that formed in process.

According to an aspect of the present invention, in preceding method, repeating said steps c) and steps d), until reach predetermined etching depth.

According to an aspect of the present invention, in preceding method, described step c) be included in etching chamber and increase a certain amount of etch byproduct polymers.

According to an aspect of the present invention, in preceding method, remove described byproduct polymers by ashing.

According to an aspect of the present invention, in preceding method, remove described byproduct polymers by cleaning.

According to an aspect of the present invention, preceding method also comprises: form liner oxide at described isolated groove inwall; Fill described isolated groove.

According to an aspect of the present invention, in preceding method, form described liner oxide by boiler tube heated oxide.

According to an aspect of the present invention, in preceding method, strengthen chemical vapour deposition (CVD) (PECVD) by gas ions, spin-on deposition, rapid vapor deposition, the film that can flow be deposited in described isolated groove and fill silica.

Compared with prior art, advantage of the present invention comprises:

According to lithographic method of the present invention; before active area is etched; the sidewall of polysilicon trench forms diaphragm, thus protection polysilicon is not damaged during the silicon etching of active area, the angle, active area simultaneously formed exposes more and this angle, active area is round.

Accompanying drawing explanation

In order to illustrate above and other advantage and the feature of various embodiments of the present invention further, present the description more specifically of various embodiments of the present invention with reference to accompanying drawing.Be appreciated that exemplary embodiments of the present invention only described by these accompanying drawings, therefore will not be considered to restriction on its scope.In the accompanying drawings, in order to cheer and bright, be exaggerated the thickness in layer and region.Identical or corresponding parts will represent with same or similar mark.

Figure 1A to Fig. 1 D shows the generalized section of carrying out the process of STI etching to polysilicon and active area in prior art.

Fig. 2 A to Fig. 2 F illustrates the generalized section of carrying out the process of STI etching to polysilicon and active area according to an embodiment of the invention.

Fig. 3 illustrates the flow chart carrying out the process of STI etching to polysilicon and active area according to an embodiment of the invention.

Embodiment

In the following description, with reference to each embodiment, present invention is described.But, person of skill in the art will appreciate that and can replace when neither one or multiple specific detail or with other and/or implement each embodiment together with addition method, material or assembly.In other situation, not shown or do not describe known structure, material or operation in detail in order to avoid make the aspects of various embodiments of the present invention obscure.Similarly, in order to the object explained, specific quantity, material and configuration are set forth, to provide the complete understanding to embodiments of the invention.But the present invention can implement when not having specific detail.In addition, each embodiment shown in accompanying drawing should be understood be illustrative expression and not necessarily draw in proportion.

Fig. 2 A-2F illustrates the generalized section of carrying out the process of STI etching to polysilicon and active area according to an embodiment of the invention.

As shown in Figure 2 A, first, source region 201 is formed with on a semiconductor substrate by doping process.Doping impurity is introduced wittingly semiconductor to change the process of its electrical properties.Selected particular dopant can depend at least in part the characteristic of the special properties expected in final switch module, the semi-conducting material that will adulterate, the other factors do not discussed herein, or more combination.Exemplary alloy can include but not limited to race III and race's V element.That in all embodiment of race IV material (such as, silicon, germanium and carborundum), race III or race's V element can be used as alloy at semi-conducting material.Concrete exemplary alloy can include but not limited to: boron (B), arsenic (As), phosphorus (P) and gallium (Ga).

Then, active area 201 forms tunnel oxide 202, polysilicon layer 203, mask layer 204 and hard mask layer 205 successively by suitable depositing operation.Depositing operation can comprise chemical vapour deposition (CVD) (CVD) technique, physical vapour deposition (PVD) (PVD) technique or ald (ALD) technique etc.In one embodiment, mask layer 204 can be silicon nitride layer.

Then, as shown in Figure 2 B, by suitable photoetching and etching technics, tunnel oxide 202, polysilicon layer 203, mask layer 204 and hard mask layer 205 are etched, to form groove.Optional etching technics comprises wet etching and dry etching, and wherein dry etching comprises again ion beam milling etching, plasma etching and reactive ion etching etc.After having etched, remove hard mask layer.

Then, as shown in Figure 2 C, the structure shown in Fig. 2 B forms layer protecting film 206, to protect the sidewall of polysilicon layer 203 when etching the silicon in active area 201.

First, set forth the action principle of diaphragm: in plasma etch process, plasma active base and the material generation chemical reaction be etched, form multiple polymers.Utilize this polymer to form anti-corrosion film on the sidewall of etched features, can lateral etching be prevented, thus realize anisotropic etching.

Inventor envisions and etch byproduct polymers can be utilized on the sidewall of etched features to form anti-corrosion film accordingly, continuous etching process is divided into some discontinuous etch stages, certain interval of time between each etch stages, and a certain amount of etch byproduct polymers is increased to etching chamber in interval time, thus increase the concentration of this etch byproduct polymers, fully can seal the multiple holes on ultra low k dielectric sidewall, the sidewall of etched features forms anti-corrosion film, thus prevents lateral etching.

Therefore, in one embodiment, by introduce diaphragm, be divided into two steps by the etching of active area 201: the first step, increase a certain amount of etch byproduct polymers at etching chamber, thus on etched features conformal deposited diaphragm 206; Second step, passes into etching gas to etching chamber, etches the silicon in active area 201.Can according to the etching requirement of reality, repeatedly repeat the first step and second step, and arrange the time of the first step and second step, while guaranteeing to etch active area 201, diaphragm 206 can adequately protect the sidewall of polysilicon layer 203.In addition, adopt etch byproduct polymers to form diaphragm 206 and also help this diaphragm 206 of removal after the etching of active area.This diaphragm 206 can be removed by cleaning step after ashing, annealing or simple etching, not increase processing step, be conducive to reducing manufacturing cost.

In another embodiment of the present invention, diaphragm 206 can be other polymer film can protecting polysilicon layer during the etching of active area.

In yet another embodiment of the present invention, diaphragm 206 can be silicon nitride film.Such as, by carrying out n 2 annealing to the structure shown in Fig. 2 B, thus silicon nitride film is formed on the sidewall of polysilicon layer 203.Then, the silicon in active area 201 is etched.

After the etching completing active area 201, remove diaphragm 206, form structure as shown in Figure 2 E.Due to during the etching of active area, protect trenched side-wall, therefore compared with existing scheme, the sidewall aspects formed is neat, and the angle, active area 207 formed exposes more and round.

Finally, as described in Fig. 2 F, the flute surfaces exposed forms oxide liner 208 and filling groove, and chemico-mechanical polishing is carried out to it.In one embodiment, this oxide liner 208 is formed by boiler tube heated oxide.In one embodiment, in sti trench groove, fill silica by high surface ratio (HARP) depositing operation, high surface ratio (HARP) depositing operation can comprise plasma enhanced chemical vapor deposition (PECVD), spin-on deposition, rapid vapor deposition, can flow film deposition etc.

First, in step 301, be formed with source region, tunnel oxide, polysilicon layer, mask layer and hard mask layer on a semiconductor substrate.

Then, in step 302, by suitable photoetching and etching technics, in tunnel oxide, polysilicon layer, mask layer, form groove, and remove hard mask layer.

In step 303, trenched side-wall forms diaphragm.。Various execution mode described by composition graphs 2C and equivalent way thereof can be taked above to form diaphragm.

In step 304, active area is etched.

In step 305, after active area has etched, carry out cleaning to remove diaphragm.

In step 306, in etching groove, form liner oxide, filling groove, and carry out chemico-mechanical polishing.

The foregoing describe some embodiments of the present invention.But the present invention can be embodied as other concrete form and not deviate from its spirit or substantive characteristics.Described embodiment all should be considered to be only illustrative and nonrestrictive in all respects.Therefore, scope of the present invention by appended claims but not aforementioned description limit.Fall in the implication of the equivalents of claims and scope to change contain by the scope of claims.

Claims

1. a manufacturing method of semiconductor device, comprising:

A) provide Semiconductor substrate, described Semiconductor substrate has active area and form tunnel oxide, polysilicon layer, mask layer successively on described active area;

B) etching mask layer, polysilicon layer and tunnel oxide successively, forms groove;

C) on described trenched side-wall, diaphragm is formed;

D) continue the described active area of etching, form isolated groove; And

E) described diaphragm is removed.

2. the method for claim 1, is characterized in that, step b) in using plasma etching technics, step c) described in diaphragm be execution step b) polymer of etch by-product that formed in process.

3. the method for claim 1, is characterized in that, repeating said steps c) and steps d), until reach predetermined etching depth.

4. method as claimed in claim 3, is characterized in that, described step c) be included in etching chamber and increase a certain amount of etch byproduct polymers.

5. the method for claim 1, is characterized in that, removes described byproduct polymers by ashing.

6. the method for claim 1, is characterized in that, removes described byproduct polymers by cleaning.

7. the method for claim 1, is characterized in that, also comprises:

Liner oxide is formed at described isolated groove inwall;

Fill described isolated groove.

8. method as claimed in claim 7, is characterized in that, form described liner oxide by boiler tube heated oxide.

9. method as claimed in claim 7, is characterized in that, strengthens chemical vapour deposition (CVD) (PECVD), spin-on deposition, rapid vapor deposition, the film that can flow be deposited in described isolated groove and fill silica by gas ions.

10. a semiconductor device, comprises the semiconductor structure manufactured by method described in any one in claim 1 to 9.