CN103367261A - Forming method of semiconductor structure - Google Patents
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- CN103367261A CN103367261A CN201310315010XA CN201310315010A CN103367261A CN 103367261 A CN103367261 A CN 103367261A CN 201310315010X A CN201310315010X A CN 201310315010XA CN 201310315010 A CN201310315010 A CN 201310315010A CN 103367261 A CN103367261 A CN 103367261A
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Abstract
The invention discloses a forming method of a semiconductor structure. The forming method comprises the following steps of: providing a semiconductor substrate, wherein the substrate is provided with a first region and a second region; forming a first dielectric layer and a floating barrier layer on the surface of the semiconductor substrate; forming a second dielectric layer with a plurality of openings, forming first side wall material layers on the second dielectric layer and the surfaces of the inner walls of the openings, wherein the thickness of the first side wall material layer arranged on the first region is larger than the thickness of the first side wall material layer arranged on the second region; carrying out chemical mechanical polishing treatment on the first side wall material layers so that the top surface of the first side wall material layer arranged on the first region is lower than or equal to the top surface of the first side wall material layer arranged on the second region; and etching the first side wall material layers and forming a first side wall on the surface of the side wall of the second dielectric layer, wherein the thickness of the first side wall arranged on the first region is same as the thickness of the first side wall arranged on the second region. The forming method of the semiconductor structure provided by the invention can improve the property of the final flash memory.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of formation method of semiconductor structure.
Background technology
Flash memory (Flash Memory) is the memory of a kind of long-life non-volatile (still can keep under powering-off state store data message), its main feature is in the situation that do not power up and can keep for a long time canned data, have that integrated level is high, access speed and the multiple advantages such as be easy to wipe faster, thereby be widely used in multinomial fields such as microcomputer, automation controls.
Existing flash cell, substantially be divided into two types: folded gate device and minute gate device, folded gate device has floating boom and control gate, wherein, control gate is positioned at the floating boom top, the method of making folded gate device is simpler than making minute gate device, yet there was the problem of wiping in folded gate device, and had increased the complexity of circuit design.Grid dividing structure can effectively be avoided erasure effect, and circuit design is relatively simple.And, compare stacked gate structure, grid dividing structure has higher programming efficiency, thereby is widely used in each electronic product.
Please refer to Fig. 1 to Fig. 6, the generalized section of the manufacture method of the autoregistration flash cell that forms for prior art.
Please refer to Fig. 1, Semiconductor substrate 10 is provided, form successively oxide layer 11, floating gate layer 12 on the described substrate 10; Form discrete dielectric layer 13 at described floating gate layer 12.
Please refer to Fig. 2, form the first side wall 14 in described dielectric layer 13 sidewall surfaces, take the first side wall 14 as mask, the described floating gate layer 12 of etching, oxide layer 11 form groove 15 to Semiconductor substrate 10.
Please refer to Fig. 3, please refer to Fig. 2 at described groove 15() floating gate layer 12, oxide layer 11 sidewall surfaces of inwall form the second side wall 16, form source line 17 in described groove and between the first side wall.
Please refer to Fig. 4, form source line 17 after, the floating gate layer 12, the oxide layer 11(that remove dielectric layer 13 and be positioned at dielectric layer 13 belows please refer to Fig. 3), expose the part surface of Semiconductor substrate 10, form floating boom 19 and floating gate oxide layers 18.
Please refer to Fig. 5, form tunnel oxide 20, described tunnel oxide 20 covers sidewall, the first side wall 14, the source line 17 of described Semiconductor substrate 10, floating boom 19 and floating gate oxide layers 18.
With reference to figure 6, form the word line 21 relative with source line 17 positions at tunnel oxide 20.
The performance of the flash memory that prior art forms also needs further raising.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of semiconductor structure, improves the performance of flash memory.
For addressing the above problem, the invention provides a kind of formation method of semiconductor structure, comprising: Semiconductor substrate is provided, and described substrate has first area and second area, described first area is positioned at the marginal position of Semiconductor substrate, and second area is positioned at the center of Semiconductor substrate; Form first medium layer and the floating gate layer that is positioned at described first medium layer surface at described semiconductor substrate surface; Form the second medium layer with some openings on described floating gate layer surface, described opening exposes the surface of part floating gate layer; Inner wall surface at described second medium layer and opening forms the first spacer material layer, and the thickness of the first spacer material layer on the first area is greater than the thickness of the first spacer material layer on the second area; Described the first spacer material layer is carried out cmp to be processed, make the top surface of the first spacer material layer on the described first area be less than or equal to the top surface of the first spacer material layer on the second area, when improving subsequent etching the first spacer material layer, the lateral etching amount of the first spacer material layer in the upper shed of first area; Described the first spacer material layer of etching forms the first side wall in the sidewall surfaces of described second medium layer, and the thickness that is positioned at the first side wall on the first side wall thicknesses and the second area on the first area is identical.
Optionally, the thickness of described the first spacer material layer is
Optionally, the thickness of described the first spacer material layer is greater than the thickness of the first side wall to be formed.
Optionally, the material of described the first spacer material layer is silica or silicon oxynitride.
Optionally, the time of described cmp is 5s～5min.
Optionally, adopt chemical mechanical milling tech, make the thickness of the first spacer material layer of removing on the first area be
Make the thickness of the first spacer material layer of removing on the second area be
Optionally, carry out after cmp processes, the top surface of the first spacer material layer is lower than the thickness of the top surface of the first spacer material layer on the second area and is on the first area
Optionally, described the first spacer material layer carries out the thickness that thickness after cmp is processed is equal to or greater than the first side wall to be formed.
Optionally, the material of described first medium layer is silica, and thickness range is
Optionally, also comprise: after forming described the first side wall, take described the first side wall and second medium layer as mask, the described floating gate layer of etching and first medium layer are to semiconductor substrate surface, and remove the second medium layer and be positioned at floating gate layer, first medium layer under the described second medium layer, form the floating boom that is positioned at the first side wall below and be positioned at the floating gate dielectric layer of described floating boom below.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the technical scheme of the present invention, because the thickness of the first spacer material layer that forms on the first area is greater than the thickness of the first spacer material layer on the second area, so that the top surface of the first spacer material layer is higher than the top surface of the first spacer material layer on the second area on the first area, thereby so that in the follow-up process of carrying out milled processed, grinding rate on the first area is greater than the grinding rate on the second area, so that the top surface of the first spacer material layer on the first area is less than or equal to the top surface of the first spacer material layer on the second area, be that the thickness of the first spacer material layer of the second medium layer top surface on the described first area is less than the thickness of the first spacer material layer of the second medium layer top surface on the second area, thereby so that the first area upper shed in the first spacer material layer by the amount of lateral etching greater than the first spacer material layer in the second area opening by the amount of lateral etching, thereby so that the thickness of the first side wall on the thickness of the first side wall on the first area that forms and the second area is identical, the length of the floating gate structure on the length that makes the floating gate structure on the first area of follow-up formation and the second area is identical, improved the performance of flash memory, improving the Semiconductor substrate central area is the quality of flash cell on the second area, has reduced the failure rate of flash cell on the second area.
Description of drawings
Fig. 1 to Fig. 6 is the structural representation that prior art of the present invention forms flash cell;
Fig. 7 to Figure 16 is the schematic diagram that the semiconductor structure of embodiments of the invention forms process.
Embodiment
As described in the background art, the flash memory performance of prior art formation remains further to be improved.
Research is found, in the flush memory device that same chip forms, is positioned at the flash memory performance in chip center zone and the poor performance in chip edge zone, thereby affects the performance of whole flash memory.
Because in the flash cell that prior art forms, as shown in Figure 4, the length of the floating gate structure of described flash cell (comprising floating boom 19 and floating gate oxide layers 18) is identical with the thickness of the first side wall 14, and the length of described floating gate structure is by the thickness decision of first side wall 14 on its surface.Prior art is when forming described the first side wall 14, at first please refer to Fig. 1 at floating gate layer 12 and dielectric layer 13() surface formation the first spacer material layer, then take described dielectric layer 13 as etching stop layer, described the first spacer material layer of etching, form described the first side wall 14, the thickness of described the first side wall 14 is identical with the thickness of the first spacer material layer.But form in the process of described the first spacer material layer at the existing depositing operation that adopts, because the speed of silicon chip edge zone gas flow and exchange is faster, and reacting gas generally touches first the fringe region on the silicon chip, so the thickness of the first spacer material layer that the thickness of actual the first spacer material layer that forms in the silicon chip edge zone forms greater than the silicon chip central area.The floating boom length of the flash cell that the floating boom length that will cause like this being positioned at the flash cell that the silicon chip central area forms forms less than the silicon chip edge zone, the flash memory performance that causes the silicon chip central area to form is relatively poor, thereby affects the performance of whole flash memory.
Technical scheme of the present invention is carried out planarization after forming described the first spacer material layer, make the floating boom length of flash cell of formation consistent, thereby improves the performance of flash memory.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing specific embodiments of the invention are described in detail.
Please refer to Fig. 7, Semiconductor substrate 100 is provided, form successively first medium layer 201 and the floating gate layer 202 that is positioned at described first medium layer 201 surface at described semiconductor substrate surface.
The material of described Semiconductor substrate 100 comprises the semi-conducting materials such as silicon, germanium, SiGe, GaAs, and described Semiconductor substrate 100 can be that the body material also can be composite construction such as silicon-on-insulator.Those skilled in the art can select according to the semiconductor device that forms on the Semiconductor substrate 100 type of described Semiconductor substrate 100, and therefore the type of described Semiconductor substrate should not limit protection scope of the present invention.In the present embodiment, described Semiconductor substrate 100 is silicon chip.
Described Semiconductor substrate 100 comprises first area I and second area II, and described first area is positioned at the silicon chip edge position, and described second area II is positioned at the center.In the present embodiment, the position of described first area I and second area II is non-conterminous, and in other embodiments of the invention, the position of described first area I and second area II also can be adjacent.
The material of described first medium layer 201 is silica, and thickness range is
Described first medium layer 201 is used to form follow-up floating gate dielectric layer, as the tunnel oxide between floating boom and the substrate.The formation method of described first medium layer 301 is thermal oxidation or chemical vapour deposition (CVD).
The material of described floating gate layer 202 can be polysilicon, and thickness range is
Described floating gate layer 202 is used to form follow-up floating boom, and described floating gate layer 202 formation methods are chemical vapour deposition (CVD).
The described floating gate layer 202 of subsequent etching and first medium layer 201 form floating gate structure.
Please refer to Fig. 8, form the second medium layer 301 with some openings 302 on described floating gate layer 202 surfaces, described opening 302 exposes the surface of part floating gate layer 202.
The material of described second medium layer 301 can be silica or silicon nitride, and in the present embodiment, the material of described second medium layer 301 is silicon nitride.
Forming described method with second medium layer 301 of some openings 302 comprises: form the second medium material layer on described floating gate layer 202 surfaces, the thickness range of described second medium material layer is
Form patterned mask layer at described second medium material layer, take described patterned mask layer as mask, the described second medium material layer of etching forms opening 302 to floating gate layer 202.Described opening 302 lays respectively at first area I and the second area II top of Semiconductor substrate.
Please refer to Fig. 9, second medium layer 301 on described first area I and the inner wall surface of opening 302 form the first spacer material layer 400a, and the second medium layer 301 on described second area II and the inner wall surface of opening 302 form the first spacer material layer 400b simultaneously.
The material of described the first spacer material layer 400a and the first spacer material layer 400b is silica, silicon nitride or silicon oxynitride, the material of described the first spacer material layer 400a and the first spacer material layer 400b is not identical with the material of second medium layer 301, in the present embodiment, the material of described the first spacer material layer 400a and the first spacer material layer 400b is silica.The thickness of described the first spacer material layer 400a and the first spacer material layer 400b is
Described the first spacer material layer 400a and the first spacer material layer 400b can adopt chemical vapor deposition method to form.The thickness of described the first spacer material layer 400a and the first spacer material layer 400b is slightly larger than the follow-up length that needs the floating gate structure of formation, and the thickness of described the first spacer material layer 400a and the first spacer material layer 400b is greater than the length of floating gate structure
In one embodiment of the invention, the average thickness of described the first spacer material layer 400a and the first spacer material layer 400b is
Because described first area I is positioned at the marginal position of silicon chip, when adopting chemical vapor deposition method to form in the process of described the first spacer material layer, reacting gas enters in the reaction chamber from the marginal position of silicon chip, and because the exchange rate between silicon chip edge position reacting gas and the accessory substance is very fast, described first area I at first contacts with reacting gas, II compares with second area, the growth rate of the first spacer material layer on the I of first area is greater than the growth rate of upper the first spacer material layer of second area II, so the thickness of the first spacer material layer 400a that forms at first area I is greater than the thickness of the second spacer material layer 400b on the second area II.If described the first spacer material layer 400a of direct etching and the first spacer material layer 400b, form the first side wall, because the thickness of described the first spacer material layer 400b is less than the thickness of 400a, can cause the thickness of upper the first side wall that forms of second area II less than the thickness of upper the first side wall of first area I, thereby so that the floating boom length of the upper internal storage location that forms of second area II is less than the floating boom length of the upper internal storage location that forms of first area I, so the upper internal storage location performance that forms of second area II can be lower than the performance of first area I internal storage location, the problem that lost efficacy occurs.
Please refer to Figure 10, described the first spacer material layer 400a and the first spacer material layer 400b(be please refer to Fig. 9) carry out cmp (CMP) and process, the first spacer material layer 400c on the formation first area I and the first spacer material layer 400d on the second area II, the top surface of described the first spacer material layer 400c is lower than the top surface of the first spacer material layer 400d.
Adopt chemical mechanical milling tech that the first spacer material layer 400b(on the first spacer material layer 400a on the described first area I and the second area II be please refer to Fig. 9) carry out planarization, form the first spacer material layer 400c on the I of first area and the first spacer material layer 400d on the second area II.Because the surface of the first spacer material layer 400a on the I of first area is higher than the surface of the first spacer material layer 400b, so, in chemical mechanical planarization process, the first spacer material layer 400a grinding rate on the I of first area is greater than the grinding rate of upper the first spacer material layer 400b of second area II.Because the thickness of the first spacer material layer 400a is greater than the thickness of the first spacer material layer 400b, the grinding rate of the first spacer material layer 400a is greater than the grinding rate of the first spacer material layer 400b, thereby after grinding a period of time, can be so that finally the surface of the first spacer material layer 400c of formation be a little less than the surface of the first spacer material layer 400d.
In the present embodiment, the time of described cmp is 5s～5min, so that the thickness of upper the first spacer material layer removed of first area I is
Form the first spacer material layer 400c; So that the thickness of upper the first spacer material layer removed of second area II is
Form the first spacer material layer 400d; And the surface of described the first spacer material layer 400c is lower than the surface of the first spacer material layer 400d.The surface of described the first spacer material layer 400c is lower than the surface of the first spacer material layer 400d
In other embodiments of the invention, also can be by the time of reducing cmp or the speed that reduces cmp, so that the surface of final the first spacer material layer 400c that forms and the flush of the first spacer material layer 400d.
Because the thickness of initial the first spacer material layer 400a that forms and the first spacer material layer 400b is greater than the width of the floating gate structure of needs formation, after the employing cmp carries out planarization, so that the thickness of the first spacer material layer 400d on dielectric layer 301 top surfaces on the second area II equals or be slightly larger than the width of the floating gate structure that needs formation.
Described cmp does not exert an influence to the first spacer material layer 400c in the opening 302 and the thickness of the first spacer material layer 400d, the thickness of the first spacer material layer 400c in the described opening 302 still but can change the first spacer material layer at described second medium layer 301 top and the pattern of interior the first spacer material layer junction of opening greater than the thickness of the first spacer material layer 400d.Because the thickness that the first spacer material layer on the second area II is removed is lower, so, in described the first spacer material layer 400d and the opening 302 pattern of the first spacer material layer junction be flattened before compare, change little.And because the thickness that the first spacer material layer on the I of first area is removed is larger, so, in described the first spacer material layer 400c and the opening 302 pattern of the first spacer material layer junction be flattened before compare, change larger, the first spacer material layer 400c top of opening 302 sidewall surfaces of first area I has a horizontal surface, thereby so that during follow-up spacer material layer 400c on the described first area I of etching, the first spacer material layer in the described opening 302 by the amount of lateral etching greater than the first spacer material layer in the second area II upper shed 302 by the amount of lateral etching.
Please refer to Figure 11, described the first spacer material layer 400c of etching and the first spacer material layer 400d form the first side wall 401a that is positioned on the I of first area and the first side wall 401b that is positioned on the second area II.
Employing forms described the first side wall 401a and the first side wall 401b without mask etching.In concrete the present embodiment, adopt dry etch process, the etching gas that described dry etch process adopts is CF
4, buffer gas is He, pressure is 20mTorr～200mTorr, wherein CF
4Flow velocity be 50sccm～1000sccm, the flow velocity of He is 50sccm～1000sccm.In other embodiments of the invention, described etching gas can also be CF
4, CHF
3Or C
2F
6In one or more combination.
Because in the process of planarization, the first spacer material layer 400b(to second medium layer 301 top on the second area II please refer to Fig. 9) thickness removed is lower, the first spacer material layer 400d(at the second medium layer top that forms after the planarization please refer to Figure 10) the thickness disparity of interior the second spacer material layer of thickness and opening 302 little.And because the second spacer material layer 400a(at second medium layer 301 top on the I of first area please refer to Fig. 9) thickness that goes out is larger, the thickness of the first spacer material layer 400c at the second medium layer top that forms after the planarization is less than the thickness of the second spacer material layer in the opening 302, and both gaps are larger.
Described the first spacer material layer 400c of etching and the first spacer material layer 400d, form the first side wall 401a and the first side wall 401b, take described floating boom material layer 202 as etching stop layer, after all being etched to floating boom material layer 202 on first area I and the second area II, stop described etching technics.In the first spacer material layer 400c on the described first area I of etching, because the first spacer material layer 400c on second medium layer 301 surface on the described first area I compares with planarization before, be removed certain thickness, and be lower than the thickness of the first spacer material layer 400d at second medium layer 301 top on the second area II, so, in the process of etching, the first spacer material that described second medium layer 301 top need to etch away is relatively less, thereby so that more to the time of the first spacer material layer etching in the first area I upper shed 302, more to the amount of the lateral etching of the first spacer material layer of described opening 302 sidewall surfaces.But because the thickness of the first spacer material layer 400c in the opening 302 of described first area I is greater than the thickness of the first spacer material layer 400d in the opening 302 of second area II, so final the first side wall 401a that forms is identical with the thickness of the first side wall 401b.Thereby so that follow-up again first area I is identical with the length of the upper floating gate structure that forms of second area II, namely so that the length of the floating gate structure of the flash cell that forms on silicon chip edge zone and the central area is identical, reduce the failure rate of the flash cell of silicon chip central area, improved the flash memory quality of silicon chip central area.
Please refer to Figure 12, take described second medium layer 301 and the first side wall 401a, the first side wall 401b as mask, the described floating gate layer 202 of etching and first medium layer 201 form groove 501 to Semiconductor substrate 100.
Concrete, the etching technics of employing is dry etch process.
Please refer to Figure 13, please refer to Figure 12 at described groove 501() sidewall surfaces forms the second side wall 502, and forming source electrode line 503 between described groove 501, the first side wall 401a, between the first side wall 401b.
The material of described the second side wall 502 is silica or silicon nitride, and the formation method of the second side wall 502 is known technology for those skilled in the art, does not repeat them here.Acting as of the second side wall 502 is in the isolation and protection structure of subsequent technique as floating gate layer 202 and first medium layer 201.
After forming the second side wall 502, take the first side wall 401a, the first side wall 401b and the second side wall 502 as mask Semiconductor substrate is carried out Implantation, form the source region (not shown).
At surface, described source region and second medium layer 301 surface deposition source electrode line material, in the present embodiment, described source electrode line material is polysilicon, and the method that forms described source electrode line material is chemical vapour deposition (CVD).After forming described source electrode line material, adopt chemical mechanical milling tech that described source electrode line material is carried out planarization, take described second medium layer 301 as stop-layer, form source electrode line 503.In other embodiments of the invention, also can adopt etching technics, remove the source electrode line material on the described second medium layer 301.
Follow-uply can also adopt thermal oxidation or depositing operation, form the oxide protective layer (not shown)s on described source electrode line 503 surfaces.
Please refer to Figure 14, remove described second medium layer 301(and please refer to Figure 13) and floating gate layer 202 and the first medium layer 201(of described second medium layer 301 below please refer to Figure 13).
Concrete, form the mask layer (not shown) on described source electrode line 503 surfaces, take described mask layer as mask, adopt dry etch process, take described first medium layer 201 as stop-layer, 301(please refer to Figure 13 to the second medium layer) and following floating gate layer 202 carry out etching, form floating boom 203.
Then, adopt wet corrosion technique to remove second medium layer 301(and please refer to Figure 13) the first medium layer 201(of below please refer to Figure 13), form the floating gate dielectric layer 204 that is positioned at floating boom 203 belows.
Please refer to Figure 15, form the 3rd dielectric layer 504 in the sidewall surfaces of described Semiconductor substrate 100 surfaces, floating boom 203 sidewall surfaces, floating gate dielectric layer 204 and the first side wall 401a, the first side wall 402b.
The material of described the 3rd dielectric layer 504 is silica, and thickness is
In the present embodiment, adopt chemical vapor deposition method to form described the 3rd dielectric layer 504.Described the 3rd dielectric layer 504 is as tunnel oxide.
Please refer to Figure 16, form word line 505 on described the 3rd dielectric layer 504 surfaces.
The material of described word line 505 is polysilicon, and the technique that forms described word line 505 is known the field for those skilled in the art, does not repeat them here.
In the present embodiment, adopt said method to form in the process of flash memory structure, after forming the first spacer material layer, adopt the chemical machinery masking process that described the first spacer material layer is ground, be the thickness of the first spacer material layer of the second medium layer top surface on the second area II less than the silicon chip central area so that the silicon chip edge zone is the thickness of the first spacer material layer of the second medium layer top surface on the I of first area, thereby so that first area I upper shed in the first spacer material layer by the amount of lateral etching greater than the first spacer material layer in the second area II upper shed by the amount of lateral etching, thereby so that the thickness of the first side wall on the thickness of the first side wall on the first area I that forms and the second area II is identical, thereby the length of the floating gate structure on the length that makes the floating gate structure on the first area I of final formation and the second area II is identical, improve the performance of flash memory, reduced the probability that the upper flash cell of second area II lost efficacy.
Although the present invention discloses as above, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can make various changes or modifications, so protection scope of the present invention should be as the criterion with the claim limited range.
Claims (10)
1. the formation method of a semiconductor structure is characterized in that, comprising:
Semiconductor substrate is provided, and described substrate has first area and second area, and described first area is positioned at the marginal position of Semiconductor substrate, and second area is positioned at the center of Semiconductor substrate;
Form first medium layer and the floating gate layer that is positioned at described first medium layer surface at described semiconductor substrate surface;
Form the second medium layer with some openings on described floating gate layer surface, described opening exposes the surface of part floating gate layer;
Inner wall surface at described second medium layer and opening forms the first spacer material layer, and the thickness of the first spacer material layer on the first area is greater than the thickness of the first spacer material layer on the second area;
Described the first spacer material layer is carried out cmp to be processed, make the top surface of the first spacer material layer on the described first area be less than or equal to the top surface of the first spacer material layer on the second area, when improving subsequent etching the first spacer material layer, the lateral etching amount of the first spacer material layer in the upper shed of first area;
Described the first spacer material layer of etching forms the first side wall in the sidewall surfaces of described second medium layer, makes the thickness of the first side wall on the first side wall thicknesses of being positioned on the first area and the second area identical.
2. the formation method of semiconductor structure according to claim 1 is characterized in that, the thickness of described the first spacer material layer is
3. the formation method of semiconductor structure according to claim 1 is characterized in that, the thickness of described the first spacer material layer is greater than the thickness of the first side wall to be formed.
4. the formation method of semiconductor structure according to claim 1 is characterized in that, the material of described the first spacer material layer is silica.
5. the formation method of semiconductor structure according to claim 1 is characterized in that, the time of described cmp is 5s～5min.
6. the formation method of semiconductor structure according to claim 1 is characterized in that, adopts chemical mechanical milling tech, makes the thickness of the first spacer material layer of removing on the first area be
Make the thickness of the first spacer material layer of removing on the second area be
7. the formation method of semiconductor structure according to claim 1 is characterized in that, carries out after cmp processes, and the top surface of the first spacer material layer is lower than the thickness of the top surface of the first spacer material layer on the second area and is on the first area
8. the formation method of semiconductor structure according to claim 1 is characterized in that, described the first spacer material layer carries out the thickness that thickness after cmp is processed is equal to or greater than the first side wall to be formed.
9. the formation method of semiconductor structure according to claim 1 is characterized in that, the material of described first medium layer is silica, and thickness range is
10. the formation method of semiconductor structure according to claim 1, it is characterized in that, also comprise: after forming described the first side wall, take described the first side wall and second medium layer as mask, the described floating gate layer of etching and first medium layer are to semiconductor substrate surface, and remove the second medium layer and be positioned at floating gate layer, first medium layer under the described second medium layer, form the floating boom that is positioned at the first side wall below and be positioned at the floating gate dielectric layer of described floating boom below.
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| CN105977207A (en) * | 2016-05-11 | 2016-09-28 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of flash memory |
| CN108735760A (en) * | 2017-04-25 | 2018-11-02 | 三星电子株式会社 | three-dimensional semiconductor memory device |
| CN108735760B (en) * | 2017-04-25 | 2023-10-13 | 三星电子株式会社 | Three-dimensional semiconductor memory device |
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