CN105514046A - Manufacturing method of split-gate flash memory - Google Patents
Manufacturing method of split-gate flash memory Download PDFInfo
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- CN105514046A CN105514046A CN201610016144.5A CN201610016144A CN105514046A CN 105514046 A CN105514046 A CN 105514046A CN 201610016144 A CN201610016144 A CN 201610016144A CN 105514046 A CN105514046 A CN 105514046A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
Abstract
A manufacturing method of a split-gate flash memory comprises the steps of providing a substrate, wherein the substrate is provided with a first surface and a second surface; forming a plurality of discrete pseudo grid structures on the first surface of the substrate; forming first source electrode material layers between the adjacent pseudo grid structures and above places between the adjacent pseudo grid structures, and meanwhile forming a second source electrode material layer on the second surface of the substrate; planarizing the first source electrode material layers to form source wires; after the source wires are formed, removing the second source electrode material layer; forming word lines. According to the manufacturing method disclosed by the embodiment of the invention, after the first source electrode material layers and the second source electrode material layer are formed, under the condition that the substrate is not obviously warped, firstly the first source electrode material layers are planarized, then the second source electrode material layer is removed by etching, thus avoiding the problem that a planarizing process lowers the height of the word lines to cause programming crosstalk failure of the split-gate flash memory.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of manufacture method of Split-gate flash memory.
Background technology
In current semiconductor industry, memory device account for sizable ratio in integrated circuit (IC) products, and the development of the flash memory in memory is particularly rapid.Its main feature is the information that can keep for a long time when not powering up storing, and has that integrated level is high, access speed and be easy to the multiple advantages such as erasing faster, is thus widely used in the multinomial field such as microcomputer, Automated condtrol.
Flash memory is divided into two types: folded grid (stackgate) device and point grid (splitgate) device.Folded gate device has floating boom and control gate, and wherein, control gate is positioned at above floating boom, and the method manufacturing folded gate device is simpler than manufacture point gate device, but folded gate device existed erasing problem.With folded gate device unlike, point gate device forms the wordline as erasing grid in the side of floating boom, wordline as control gate, on wiping/writing performance, point gate device efficiently avoid folded gate device erasure effect, circuit design is relatively simple.And grid dividing structure utilizes source hot electron to inject and programmes, and has higher programming efficiency, is thus widely used in the electronic products such as all kinds of such as smart card, SIM card, microcontroller, mobile phone.
But there is the problem of programming interference inefficacy (columnpunchthrough, PTC) in existing Split-gate flash memory.The reason of this problem is caused to be: when carrying out ion implantation to source-drain electrode, because the height of wordline is lower, ion implantation can be made to penetrate wordline, cause programming interference to lose efficacy.
Summary of the invention
The technical problem that the present invention solves is to provide a kind of manufacture method of Split-gate flash memory, to solve the lower and problem of Split-gate flash memory programming interference inefficacy that causes of height because of wordline.
For solving the problems of the technologies described above, the embodiment of the present invention provides a kind of manufacture method of Split-gate flash memory, comprising: provide substrate, and described substrate has first surface and second surface; Multiple discrete dummy gate structure is formed at the first surface of described substrate; Between adjacent dummy gate structure and on form the first source electrode material layer, simultaneously form the second source electrode material layer at the second surface of described substrate; Planarization is carried out to the first source electrode material layer, forms source electrode line; After forming source electrode line, remove described second source electrode material layer; Form wordline.
Alternatively, the material forming described first source electrode material layer and the second source electrode material layer comprises polysilicon.
Alternatively, the technique forming described first source electrode material layer and the second source electrode material layer is low-pressure chemical vapor deposition process, and it is 400 degrees Celsius to 700 degrees Celsius that technological parameter comprises temperature, and pressure is that 0.2 holder to 0.6 is held in the palm, and reacting gas is SiH
4and PH
3, SiH
4flow be 1 standard liter/min to 3 standard liter/min, PH
3flow be 1 standard milliliters/minute to 20 standard milliliters/minute.
Alternatively, the thickness forming described first source electrode material layer is 1600 dust to 2300 dusts.
Alternatively, described flatening process comprises cmp.
Alternatively, the method forming described discrete dummy gate structure comprises: form the first oxide layer, floating gate layer and pseudo-gate layer successively at the first surface of substrate; Etch described pseudo-gate layer, floating gate layer is formed discrete dummy grid, the region at dummy grid place is wordline district, and the region between adjacent dummy grid forms the first groove, and the first channel bottom exposes part floating gate layer; The first side wall is formed at the sidewall of described first groove; With the first side wall for mask, etch described floating gate layer and the first oxide layer to the first surface of substrate, form discrete dummy gate structure, described dummy gate structure comprises the first oxide layer, floating gate layer, dummy grid and the first side wall.
Alternatively, after forming discrete dummy gate structure, before forming the first source electrode material layer, also comprise: form the second side wall at the sidewall of dummy gate structure, described second side wall covers the sidewall of the first oxide layer and floating gate layer and the partial sidewall of the first side wall; With the first side wall and the second side wall for mask, ion implantation is carried out to the substrate between adjacent dummy gate structure, form source region.
Alternatively, described after forming discrete dummy grid, before formation first side wall, also comprise and adopt the method for isotropic etching to etch the first channel bottom, to remove the floating gate layer of part, described floating gate layer forms curved surfaces.
Alternatively, the method forming wordline comprises: remove the floating gate layer below dummy grid and dummy grid and the first oxide layer, forms floating boom and coupling oxide layer; Form the second oxide layer, cover sidewall and the source electrode line surface of the substrate surface in wordline district, floating boom, coupling oxide layer and the first side wall; Second oxide layer in wordline district forms wordline.
Compared with prior art, the technical scheme of the embodiment of the present invention has following beneficial effect:
In the manufacture method of the embodiment of the present invention, after formation first source electrode material layer and the second source electrode material layer, when not yet there is obvious warpage in substrate, first planarization is carried out to the first source electrode material layer, etching removes the second source electrode material layer being positioned at the second surface of substrate again, makes the wordline height of formation not by the impact of flatening process; Avoid and formerly remove the second source electrode material layer, carry out in the technique of planarization to the first source electrode material layer again, obvious warpage is there is in substrate under the effect of stress of the first source electrode material layer, make the wordline district being positioned at substrate edge by exceedingly planarization, reduce the height forming wordline, cause the problem that Split-gate flash memory programming interference lost efficacy.
Accompanying drawing explanation
Fig. 1 is the schematic flow sheet of the manufacture method of the Split-gate flash memory of one embodiment of the invention.
Fig. 2 to Figure 13 is the generalized section of the intermediate structure of the manufacture method of the Split-gate flash memory of one embodiment of the invention.
Embodiment
There is the problem of programming interference inefficacy in the Split-gate flash memory of prior art, through inventor to the analysis that the position that programming interference lost efficacy occurs, find that programming interference lost efficacy and mainly occur in the edge of semiconductor crystal wafer, the height of the wordline of the subnormal flash cell of height of the wordline of programming interference disabling unit occurs.
When substrate (wafer) surface deposition forms the polysilicon layer of source electrode line, the upper surface of substrate and lower surface all can form polysilicon layer.But polysilicon layer inside has very high compression stress usually, is approximately 114N/cm
2, so large stress can change the warpage degree of substrate significantly.Under normal circumstances, the polysilicon layer of substrate upper surface and lower surface is stressed reaches balance, can not make substrate that obvious warpage occurs.And in the process forming Split-gate flash memory, for ensureing the accurate of technological operation, usually need the polysilicon layer removing substrate lower surface.
Prior art is after eliminating the polysilicon layer being positioned at substrate lower surface, and the stress that substrate upper surface and lower surface are subject to is unbalance, makes substrate that obvious warpage occur; Then, cmp (CMP) is carried out to form source electrode line to polysilicon layer, warped portion now near substrate edge can exceedingly be ground, reduce the height being positioned at the wordline district of substrate edge, cause the height reduction of follow-up formation wordline, cause the leakage current of wordline raceway groove to increase, cause the problem that programming interference lost efficacy.
In order to solve the problem, the invention provides a kind of manufacture method of Split-gate flash memory, below in conjunction with accompanying drawing detailed description in addition.
Fig. 1 is the schematic flow sheet of the manufacture method of the Split-gate flash memory of one embodiment of the invention.
Fig. 2 to Figure 13 is the generalized section of the intermediate structure of the manufacture method of the Split-gate flash memory of one embodiment of the invention.
With reference to figure 2, perform the step S11 in Fig. 1, provide substrate 100, described substrate 100 has first surface 100a and second surface 100b.
Described substrate 100 can be silicon substrate, germanium silicon substrate, iii-v element compound substrate, silicon carbide substrates or its laminated construction, or silicon on insulated substrate etc.In one embodiment, described substrate 100 is silicon substrate.
With reference to figure 3 to Fig. 7, perform the step S13 in Fig. 1, form multiple discrete dummy gate structure at the first surface 100a (as shown in Figure 2) of described substrate 100.Concrete formation method is:
With reference to figure 3, form the first oxide layer 111, floating gate layer 112 and pseudo-gate layer 113 successively at described first surface 100a.
In one embodiment, the material of described first oxide layer 111 is silica, and the technique forming described first oxide layer 111 is thermal oxidation technology.The thickness range forming described first oxide layer 111 is 85 dust to 100 dusts; The material of described floating gate layer 112 is polysilicon, and the technique forming described floating gate layer 112 is low-pressure chemical vapor deposition process, and the thickness range forming described floating gate layer 112 is 200 dust to 1000 dusts; The material of described pseudo-gate layer 113 is silicon nitride, and the technique forming described pseudo-gate layer 113 is low-pressure chemical vapor deposition process, and the thickness range forming described pseudo-gate layer 113 is 2500 dust to 5000 dusts.
With reference to figure 4, etch described pseudo-gate layer 113 (as shown in Figure 3), floating gate layer 112 is formed discrete dummy grid 113a, the region at dummy grid 113a place is wordline district 201, region between adjacent dummy grid 113a forms the first groove 114, and described first groove 114 bottom-exposed goes out the surface of part floating gate layer 112.
The formation method of described dummy grid 113a is: in pseudo-gate layer 113, form patterned mask layer, with described patterned mask layer for mask, adopt described pseudo-gate layer 113 to the floating gate layer 112 of method etching of dry etching, floating gate layer 112 is formed discrete dummy grid 113a, and the region at dummy grid 113a place is wordline district 201.
With reference to figure 5, the method for employing isotropic etching etches the floating gate layer 112 between adjacent dummy grid 113a, described floating gate layer 112 forms umbilicate curved surfaces, for the top apex of the floating boom of follow-up formation is ready.
With reference to figure 6, the sidewall of dummy grid 113a forms the first side wall 115.
In one embodiment, the material of described first side wall 115 is silica.The method forming described first side wall 115 is: adopt the technique of low-pressure chemical vapor deposition at the curved surfaces of floating gate layer 112, the surface of dummy grid 113a and side wall deposition first spacer material layer (not shown), then return and carve described first spacer material layer, form the first side wall 115 covering dummy grid 113a sidewall.
With reference to figure 7, with described first side wall 115 for mask, etching floating gate layer 112 and the first oxide layer 111 to substrate 100, form discrete dummy gate structure 110 at the first surface 100a of described substrate 100.Described dummy gate structure 110 comprises the first oxide layer 111, floating gate layer 112, dummy grid 113a and the first side wall 115.Wherein, the technique etching floating gate layer 112 and the first oxide layer 111 to substrate 100 is dry etching.
With reference to figure 8, perform the step S15 in Fig. 1, ion implantation is carried out to the substrate between adjacent dummy gate structure 110, form source region.
The method forming source region comprises: in the partial sidewall of adjacent dummy gate structure 110, form the second side wall 116, described second side wall 116 covers the sidewall of the first oxide layer 111 and floating gate layer 112 and the partial sidewall of the first side wall 115; With the first side wall 115 and the second side wall 116 for mask, ion implantation is carried out to the substrate 100 between adjacent dummy gate structure 110, form source region (not shown).
In one embodiment, the material of described second side wall 116 is silica or silicon nitride, and the formation method of the second side wall 116 knows technology for those skilled in the art, does not repeat them here.Acting as of second side wall 116: follow-up ion implantation is carried out to the substrate between adjacent dummy gate structure 110 time, protection first medium layer 111 and floating gate layer 112 injury-free, play the effect of isolation floating gate layer 112 and surrounding medium.
With reference to figure 9, perform the step S17 in Fig. 1, between adjacent dummy gate structure 110 and on form the first source electrode material layer 121, simultaneously at the upper formation second source electrode material layer 122 of the second surface 100b (as shown in Figure 1) of described substrate 100.
The material of described first source electrode material layer 121 and the second source electrode material layer 122 is polysilicon; The method forming described first source electrode material layer 121 and the second source electrode material layer 122 is low-pressure chemical vapor deposition (LowPressureChemicalVaporDeposition, LPCVD) technique, it is 400 degrees Celsius to 700 degrees Celsius that technological parameter comprises temperature, pressure is that 0.2 holder to 0.6 is held in the palm (1 holder approximates 133.322 handkerchiefs), and reacting gas is SiH
4and PH
3, SiH
4flow be 1 standard liter/min to 3 standard liter/min, PH
3flow be 1 standard milliliters/minute to 20 standard milliliters/minute; The thickness forming described first source electrode material layer 121 is 1600 dust to 2300 dusts.
In one embodiment, the technological temperature forming the low-pressure chemical vapor deposition process of described first source electrode material layer 121 and the second source electrode material layer 122 is 500 degrees Celsius, and pressure is 0.4 holder, reacting gas SiH
4flow be 1.5 standard liter/min, PH
3flow be 11.2 standard milliliters/minute; The thickness forming described first source electrode material layer 121 is 1900 dusts.
In another embodiment, the technological temperature forming the low-pressure chemical vapor deposition process of described first source electrode material layer 121 and the second source electrode material layer 122 is 600 degrees Celsius, and pressure is 0.5 holder, reacting gas SiH
4flow be 2 standard liter/min, PH
3flow be 14 standard milliliters/minute; The thickness forming described first source electrode material layer 121 is 2100 dusts.
It should be noted that, because the first surface 100a (as shown in Figure 2) of described substrate 100 and second surface 100b (as shown in Figure 2) is formed with source electrode material layer, stress between described first source electrode material layer 121 and the second source electrode material layer 122 reaches balance, and therefore obvious warpage can not occur whole substrate (wafer) (comprising substrate 100 and dummy gate structure 110).
In one embodiment, after the described first source electrode material layer 121 of formation and the second source electrode material layer 122, the radius of curvature of described substrate is 40.036; In another embodiment, after the described first source electrode material layer 121 of formation and the second source electrode material layer 122, then remove described second source electrode material layer 122, the radius of curvature of described substrate is 34.341.This shows, after the described second source electrode material layer 122 of removal, can there is obvious warpage in substrate under the effect of stress of the first source electrode material layer.
In order to prevent when substrate warpage, flatening process is removed too much to substrate edge, reduce the height in wordline district 201, the embodiment of the present invention is after the described first source electrode material layer 121 of formation and the second source electrode material layer 122, when not removing described second source electrode material layer 122, first planarization is carried out to described first source electrode material layer 121, then remove described second source electrode material layer 122.
With reference to Figure 10, perform the step S19 in Fig. 1, planarization is carried out to the first source electrode material layer 121 (as shown in Figure 9), until expose the surface of dummy grid 113a, form source electrode line 121a.The method of carrying out planarization to described first source electrode material layer 121 is cmp.
With reference to Figure 11, perform the step S21 in Fig. 1, after forming source electrode line 121a, etching removes described second source electrode material layer 122 (as shown in Figure 10).
In conjunction with reference to Figure 12 and Figure 13, perform the step S23 in Fig. 1, form wordline.The method forming wordline comprises:
With reference to Figure 12, remove the floating gate layer 112 below dummy grid 113a and dummy grid 113a and the first oxide layer 111, form floating boom 112a and coupling oxide layer 111a, described floating boom 112a has top apex; Substrate 100 surface in wordline district 201, coupling oxide layer 111a, floating boom 112a and the sidewall of the first side wall 115 and the surface of source electrode line 121a form the second oxide layer 130.
With reference to Figure 13, the upper deposition of the second oxide layer 130 (as shown in figure 12) in wordline district 201 wordline material floor, etches described wordline material layer by self-registered technology until expose source electrode line 121a surface, forms wordline 140 and tunnel oxide 130a.Described coupling oxide layer 111a, floating boom 112a, the first side wall 115, tunnel oxide 130a and wordline 140 form grid structure 110a jointly.
In one embodiment, the material of described second oxide layer 130 is silica, and described wordline material layer is polysilicon, and the technique forming wordline 140 and tunnel oxide 130a belongs to those skilled in the art and knows field, does not repeat them here.
It should be noted that, the invention is not restricted to the Split-gate flash memory of above embodiment, the Split-gate flash memory of other types is applicable to the present invention too.
In sum, the manufacture method of the embodiment of the present invention, after formation first source electrode material layer and the second source electrode material layer, when not yet there is obvious warpage in substrate, first planarization is carried out to the first source electrode material layer, etching removes the second source electrode material layer being positioned at the second surface of substrate again, makes the wordline height of formation not by the impact of flatening process; Avoid and formerly remove the second source electrode material layer, carry out in the technique of planarization to the first source electrode material layer again, obvious warpage is there is in substrate under the effect of stress of the first source electrode material layer, make the wordline district being positioned at substrate edge by exceedingly planarization, reduce the height forming wordline, cause the problem that Split-gate flash memory programming interference lost efficacy.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (9)
1. a manufacture method for Split-gate flash memory, is characterized in that, comprising:
There is provided substrate, described substrate has first surface and second surface;
Multiple discrete dummy gate structure is formed at the first surface of described substrate;
Between adjacent dummy gate structure and on form the first source electrode material layer, simultaneously form the second source electrode material layer at the second surface of described substrate;
Planarization is carried out to the first source electrode material layer, forms source electrode line;
After forming source electrode line, remove described second source electrode material layer;
Form wordline.
2. manufacture method as claimed in claim 1, it is characterized in that, the material forming described first source electrode material layer and the second source electrode material layer comprises polysilicon.
3. manufacture method as claimed in claim 2, it is characterized in that, the technique forming described first source electrode material layer and the second source electrode material layer is low-pressure chemical vapor deposition process, and it is 400 degrees Celsius to 700 degrees Celsius that technological parameter comprises temperature, pressure is that 0.2 holder to 0.6 is held in the palm, and reacting gas is SiH
4and PH
3, SiH
4flow be 1 standard liter/min to 3 standard liter/min, PH
3flow be 1 standard milliliters/minute to 20 standard milliliters/minute.
4. manufacture method as claimed in claim 3, it is characterized in that, the thickness forming described first source electrode material layer is 1600 dust to 2300 dusts.
5. manufacture method as claimed in claim 1, it is characterized in that, described flatening process comprises cmp.
6. manufacture method as claimed in claim 1, it is characterized in that, the method forming described discrete dummy gate structure comprises:
The first oxide layer, floating gate layer and pseudo-gate layer is formed successively at the first surface of substrate;
Etch described pseudo-gate layer, floating gate layer is formed discrete dummy grid, the region at dummy grid place is wordline district, and the region between adjacent dummy grid forms the first groove, and the first channel bottom exposes part floating gate layer;
The first side wall is formed at the sidewall of described first groove;
With the first side wall for mask, etch described floating gate layer and the first oxide layer to the first surface of substrate, form discrete dummy gate structure, described dummy gate structure comprises the first oxide layer, floating gate layer, dummy grid and the first side wall.
7. manufacture method as claimed in claim 6, is characterized in that, after forming discrete dummy gate structure, before forming the first source electrode material layer, also comprises:
Form the second side wall at the sidewall of dummy gate structure, described second side wall covers the sidewall of the first oxide layer and floating gate layer and the partial sidewall of the first side wall;
With the first side wall and the second side wall for mask, ion implantation is carried out to the substrate between adjacent dummy gate structure, form source region.
8. manufacture method as claimed in claim 6, is characterized in that, described after forming discrete dummy grid, before formation first side wall, also comprise and adopt the method for isotropic etching to etch the first channel bottom, to remove the floating gate layer of part, described floating gate layer forms curved surfaces.
9. manufacture method as claimed in claim 6, is characterized in that, the method forming wordline comprises:
Remove the floating gate layer below dummy grid and dummy grid and the first oxide layer, form floating boom and coupling oxide layer;
Form the second oxide layer, cover sidewall and the source electrode line surface of the substrate surface in wordline district, floating boom, coupling oxide layer and the first side wall;
Second oxide layer in wordline district forms wordline.
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| CN106206451A (en) * | 2016-07-27 | 2016-12-07 | 上海华虹宏力半导体制造有限公司 | Gate-division type flash memory device making method |
| CN111613619A (en) * | 2020-06-11 | 2020-09-01 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of split-gate flash memory |
| CN111613618A (en) * | 2020-05-26 | 2020-09-01 | 上海华虹宏力半导体制造有限公司 | Semiconductor device and method for manufacturing the same |
| CN111739892A (en) * | 2020-07-30 | 2020-10-02 | 上海华虹宏力半导体制造有限公司 | Flash memory and manufacturing method thereof |
| CN111799163A (en) * | 2020-07-17 | 2020-10-20 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing semiconductor device |
| CN112750790A (en) * | 2021-01-22 | 2021-05-04 | 上海华虹宏力半导体制造有限公司 | Flash memory and manufacturing method thereof |
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