CN103441075A

CN103441075A - Method for manufacturing floating gate MOS transistor

Info

Publication number: CN103441075A
Application number: CN2013103369437A
Authority: CN
Inventors: 秦伟; 高慧慧; 杨渝书; 黄海辉
Original assignee: Shanghai Huali Microelectronics Corp
Current assignee: Shanghai Huali Microelectronics Corp
Priority date: 2013-08-02
Filing date: 2013-08-02
Publication date: 2013-12-11

Abstract

The invention discloses a method for manufacturing a floating gate MOS transistor. The method includes the following steps that a medium layer, a polycrystalline silicon layer and a nitride layer are sequentially deposited on the surface of a silicon substrate; the nitride layer, the polycrystalline silicon layer and the medium layer are sequentially etched into the silicon substrate, and STI trenches are formed; an oxidation layer is deposited, the STI trenches are filled with the oxidation layer, and the oxidation layer covers the surface of the remaining nitride layer; a flattening technology is performed on the silicon oxide layer, and the remaining silicon oxide layer located on the surface of the remaining nitride layer is removed; after part of the silicon oxide layer located in the STI trenches is etched, the remaining nitride layer is removed. According to the method, the deposition steps are firstly performed, then the scheme of synchronous etching is adopted, and FG and STI technologies are finished at the same time. In comparison with a traditional technology, the technological processes are simplified, production efficiency is further improved, production time of finished products is shortened, and economic benefits are improved.

Description

The transistorized manufacture method of floating-gate MOS

Technical field

This area relates to field of semiconductor manufacture, is specifically related to the transistorized manufacture method of a kind of floating boom.

Background technology

Development along with integrated circuit technique, traditional silicon integrated circuit based on the one-transistor function, problem a lot of difficulties, anxious to be resolved has appearred, and floating-gate MOS transistor (Floating Gate MOS), as the cell transistor of novel high integration, for increasing the problem of bringing, transistor size and interconnection line in the solution integrated circuit provide a kind of effective approach.

In the floating-gate MOS transistor, due to the FG(floating grid) be positioned at the STI(fleet plough groove isolation structure) top, and the position opposite of complete and STI, so the technological process of traditional formation FG is first to carry out STI Etch(fleet plough groove isolation structure etching), then in fleet plough groove isolation structure, cvd silicon oxide process CMP (cmp) and silicon nitride are removed technique, and last deposition and the polysilicon grinding that passes through again polysilicon forms floating gate structure.

Fig. 1-4, for prior art prepares the schematic flow sheet of floating grid, comprise the following steps:

1, provide semiconductor device, this device comprises silicon substrate 1, dielectric layer 2 and silicon nitride layer 3 from bottom to top successively, as shown in Figure 1.

2, adopt photoetching process and dry etch process to form fleet plough groove isolation structure in device, form shown in Fig. 2.

3, silicon oxide layer deposited 4 fill up fleet plough groove isolation structure and remove remaining nitride silicon layer 3 ', as shown in Figure 3;

4, deposit spathic silicon layer 5 covers remaining media layers 2 ' and the upper surface of silicon nitride layer 4, as shown in Figure 4.

5, carry out chemical mechanical milling tech and remove the silicon nitride layer 4 that certain thickness polysilicon layer 5 exposes its lower surface covering, then eat-back silicon nitride layer 4, as shown in Figure 5.

As can be seen here, the technical scheme of available technology adopting is that first etching forms fleet plough groove isolation structure, after then being filled after silicon oxide layer polishing and removing silicon nitride, then after the deposit spathic silicon layer, then carry out cmp and eat-back silicon oxide layer.As can be seen here, the preparation method of prior art is more loaded down with trivial details, and the production cycle is longer.

Documents (application number: 200710094466.2) disclose a kind of method that forms fleet plough groove isolation structure and formed the lithographic method of shallow trench, having comprised the following steps: the Semiconductor substrate with pad oxide and corrosion barrier layer is provided successively; Form grinding layer on corrosion barrier layer, be formed with the opening corresponding with the shallow trench position on described grinding layer; Take grinding layer as the cover curtain, along opening etching corrosion barrier layer to exposing pad oxide; Take grinding layer and corrosion barrier layer as the cover curtain, and etching pad oxide and Semiconductor substrate, form shallow trench; After removing grinding layer, Side deposition lining oxide layer in shallow trench, and insulating oxide is filled to full shallow trench; Remove corrosion barrier layer and pad oxide, form fleet plough groove isolation structure.

This invention forms the grinding layer of protection corrosion barrier layer in etching process on corrosion barrier layer, and etching gas can not exerted an influence to corrosion barrier layer, and the thickness of corrosion barrier layer does not change yet, thereby the isolation effect of fleet plough groove isolation structure is improved.

Summary of the invention

The present invention is according to the deficiencies in the prior art, a kind of manufacture method of floating grid is provided, first carry out all deposition steps, then etching forms shallow trench and fills silica, finally carries out cmp and removes the partial oxygen SiClx, forms the transistorized floating grid of floating boom and fleet plough groove isolation structure, the present invention adopts the method for synchronous etching, effectively simplification of flowsheet, enhance productivity, and then shorten and ETCD estimated time of commencing discharging.

The technical solution used in the present invention is:

The transistorized manufacture method of a kind of floating-gate MOS wherein, comprises the following steps:

Metallization medium layer, polysilicon layer and nitride layer successively in the surface of a silicon substrate;

The described nitride layer of etching, polysilicon layer and described dielectric layer, to described silicon substrate, form the sti trench groove successively;

Deposit the surface that an oxide layer is full of described sti trench groove and covers residual nitrogen compound layer;

Described silicon oxide layer is carried out to flatening process, remove the lip-deep silicon oxide layer that is positioned at described residual nitrogen compound layer;

Eat-back the part be arranged in sti trench groove silicon oxide layer after, remove described residual nitrogen compound layer;

Carry out the transistorized manufacturing process of follow-up floating boom.

Above-mentioned method, wherein, described nitride layer is silicon nitride layer.

Above-mentioned method, wherein, adopt photoetching and dry etch process to form described sti trench groove.

Above-mentioned method, wherein, the thickness that deposits described polysilicon layer is the 600-700 dust.

Above-mentioned method, wherein, adopt wet-etching technology to eat-back the partial oxidation silicon layer of filling in described sti trench groove.

Above-mentioned method, wherein, after carrying out described wet-etching technology, the residue oxide layer upper surface of filling in described sti trench groove is between remaining media layer upper surface and residue the first polysilicon layer upper surface.

Above-mentioned method, wherein, described oxide layer is silica.

Because the present invention has adopted above technical scheme, before the silicon nitride deposition, first deposit a polysilicon layer, and then carry out trench fill, and form floating grid and the shallow trench of MOS transistor by etching, without form the sti trench groove in etching and fill after at deposit spathic silicon and then ground and etching, simplified processing step, improved production efficiency.

The accompanying drawing explanation

By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that the present invention and feature thereof, profile and advantage will become.In whole accompanying drawings, identical mark is indicated identical part.Deliberately proportionally do not draw accompanying drawing, focus on illustrating purport of the present invention.

Fig. 1-5 prepare the flow chart of floating grid for prior art;

The flow chart that Fig. 6-9 are a kind of floating-gate MOS transistor fabrication process provided by the invention.

Embodiment

Below in conjunction with accompanying drawing, the specific embodiment of the present invention is further described:

The invention provides a kind of floating-gate MOS transistor preparation method, can be applicable to the Flash(memory) and the technology platform of eFlash on, comprise the following steps:

Step 1, provide a silicon substrate 1, after silicon substrate upper surface deposition one deck dielectric layer 2, then deposit successively a polysilicon layer 6 and nitride layer 7 from bottom to top in the surface of dielectric layer 2.Preferably, the thickness of deposit spathic silicon layer 6 is 600-700 dust (as 600 dusts, 630 dusts, 650 dusts, 680 dusts, 700 dusts), and nitride layer 7 is silicon nitride, as shown in Figure 6.

The upper surface of step 2, coating one deck photoresist cover nitride layer 7, carry out exposure imaging technique rear window that forms in photoresist, then utilize this window successively etch nitride layer 7, polysilicon layer 6 and dielectric layer 2 to described silicon substrate 1, form the sti trench groove, and remove the residue photoresist, as shown in Figure 7.

Step 3, deposition one silica layer be full of fleet plough groove isolation structure and cover residual nitrogen compound layer 7 ' upper surface, then carry out chemical mechanical milling tech and remove the lip-deep silicon oxide layer be positioned at residual nitrogen compound layer 7, as shown in Figure 8.

Step 4, employing wet-etching technology eat-back removes the partial oxidation silicon layer 8 of filling in shallow trench, make residual silicon oxide layer 8 ' end face remaining media layer 2 ' upper surface and remain the first polysilicon layer 3 ' upper surface between, then remove remaining silicon nitride layer 7 '.And then make remaining silicon oxide layer 7 in the STI groove ' transistorized floating grid of formation floating boom, form shallow trench simultaneously above floating grid.Structure as shown in Figure 9.

Step 5, the transistorized preparatory technology flow process of follow-up floating boom of carrying out, follow-up processing step adopts habitual technical scheme in prior art, therefore it will not go into details in the present invention.

The STI Etch(shallow-trench isolation etching of the present invention to extensive use) and the process program of Poly CMP (polysilicon grinding) improve, to originally needing etching, deposition, grind, the technique that deposition is ground is again integrated and is optimized, first carry out all deposition steps, then adopt the scheme of synchronous etching, complete the transistorized floating grid of floating boom and shallow trench simultaneously, the conventional art of comparing has been simplified technological process, and then enhance productivity, shorten and ETCD estimated time of commencing discharging, improved economic benefit.

Above preferred embodiment of the present invention is described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and the equipment of wherein not describing in detail to the greatest extent and structure are construed as with the common mode in this area to be implemented; Any those of ordinary skill in the art, do not breaking away from technical solution of the present invention scope situation, all can utilize method and the technology contents of above-mentioned announcement to make many possible changes and modification to technical solution of the present invention, or being revised as the equivalent embodiment of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content that does not break away from technical solution of the present invention,, all still belong in the scope of technical solution of the present invention protection any simple modification made for any of the above embodiments, equivalent variations and modification according to technical spirit of the present invention.

Claims

1. the transistorized manufacture method of floating-gate MOS, is characterized in that, comprises the following steps:

Carry out the transistorized manufacturing process of follow-up floating boom.

2. the method for claim 1, is characterized in that, described nitride layer is silicon nitride layer.

3. the method for claim 1, is characterized in that, adopts photoetching and dry etch process to form described sti trench groove.

4. the method for claim 1, is characterized in that, the thickness that deposits described polysilicon layer is the 600-700 dust.

5. the method for claim 1, is characterized in that, adopts wet-etching technology to eat-back the partial oxidation silicon layer of filling in described sti trench groove.

6. method as claimed in claim 5, is characterized in that, after carrying out described wet-etching technology, the residue oxide layer upper surface of filling in described sti trench groove is between remaining media layer upper surface and residue the first polysilicon layer upper surface.

7. the method for claim 1, is characterized in that, described oxide layer is silica.