CN103633031B - The formation method of semiconductor device - Google Patents
The formation method of semiconductor device Download PDFInfo
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- CN103633031B CN103633031B CN201210306872.1A CN201210306872A CN103633031B CN 103633031 B CN103633031 B CN 103633031B CN 201210306872 A CN201210306872 A CN 201210306872A CN 103633031 B CN103633031 B CN 103633031B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
Abstract
One embodiment of the invention provides a kind of formation method of semiconductor device, comprising: provide a substrate, sequentially forms a gate dielectric, a gate material layers, a barrier oxide layer and a curtain layer of hard hood on the substrate; Sequentially etch curtain layer of hard hood, barrier oxide layer, gate material layers, gate dielectric and substrate, to form a groove in a substrate; Insert monoxide layer in the trench; This oxide skin(coating) in etchback groove, to reduce the height of oxide skin(coating); Remove curtain layer of hard hood, and removing in step with its lower gate material layers of barrier protect oxide layer; And remove barrier oxide layer, and expose gate material layers.
Description
Technical field
Present invention is directed to the formation method of semiconductor structure, and relate to a kind of barrier oxide skin(coating) that utilizes especially as the formation method of the semiconductor structure of protective layer.
Background technology
Flash memory device (FlashMemory) is a kind of nonvolatile memory device not needing power consumption just can preserve data, and it can repeatedly be deleted in operation or write.In addition, compared to other storage arrangements, flash memory has significant speed advantage when having lower reading delay, preferably dynamic shock resistance and write great mass of data, therefore be often applied to general data storage, and between computer and other numerical digit products, exchange data transmission, as memory card and Portable disk.
In addition, another advantage of flash memory is then for the cost manufactured is lower, such as, therefore flash memory has become the most important technology also the most widely adopted of non-volatile solid-state storage at present, can be applicable in the Related products such as notebook computer, numerical digit walkman, digital still camera, mobile phone, game host.
For not b gate flash memory (NANDfashmemory), primary focus is the charge storage capacity of floating grid.In addition, in the manufacturing process of semiconductor, along with the reduction of memory-size, the usefulness of floating grid also comes into one's own more.In the manufacturing process of general floating grid, hard cover screen remove the infringement that can cause grid polycrystalline silicon, and cause the reduction of gate performance.On the other hand, the pointed shape of grid rectangle then may have the problem of point discharge.
Therefore, need a kind of semiconductor fabrication process of novelty at present badly, the usefulness of floating grid can be promoted.
Summary of the invention
One embodiment of the invention provides a kind of formation method of semiconductor device, comprising: provide a substrate, sequentially forms a gate dielectric, a gate material layers, a barrier oxide layer and a curtain layer of hard hood on the substrate; Sequentially etch this curtain layer of hard hood, this barrier oxide layer, this gate material layers, this gate dielectric and this substrate, to form a groove in this substrate; Insert monoxide layer in the groove; This oxide skin(coating) in this groove of etchback, to reduce the height of this oxide skin(coating); Remove this curtain layer of hard hood, and remove in step with its this lower gate material layers of this barrier protect oxide layer at this; And remove this barrier oxide layer, and expose this gate material layers.
For the above and other object of the present invention, feature and advantage can be become apparent, cited below particularly go out preferred embodiment, and coordinate institute's accompanying drawings, be described in detail below:
Accompanying drawing explanation
Fig. 1 is presented at the flow chart of the formation method of the semiconductor device of one embodiment of the invention.
The semiconductor device that Fig. 2 to Figure 13 display is formed according to the method for Fig. 1 is in one embodiment at the profile of each fabrication stage.
Main element symbol description:
102,104,106,108,110,112 ~ step;
200 ~ substrate;
202 ~ gate dielectric;
204 ~ gate material layers;
206 ~ barrier oxide layer;
208 ~ curtain layer of hard hood;
210 ~ patterning photoresist layer;
212 ~ groove;
214 ~ oxide skin(coating);
The residual fraction of 216 ~ oxide skin(coating);
220 ~ control gate layer.
Embodiment
Different characteristic below according to the present invention enumerates several different embodiment.In the present invention, specific element and arrangement have been simplification, but the present invention is not limited with these embodiments.For example, the description forming the first element on the second element can comprise the embodiment that the first element directly contacts with the second element, also comprises the embodiment having extra element and be formed between the first element with the second element, the first element is not directly contacted with the second element.In addition, for simplicity's sake, the present invention with the component symbol repeated and/or letter representation, but does not represent between described each embodiment and/or structure and has specific relation in different example.
Fig. 1 display in an embodiment of the present invention, forms the method flow diagram of semiconductor device.In a step 102, provide substrate, and on substrate, sequentially form gate dielectric, gate material layers, barrier oxide layer and curtain layer of hard hood.At step 104, sequentially etch curtain layer of hard hood, barrier oxide layer, gate material layers, gate dielectric and substrate, to form a groove in a substrate.In step 106, oxide skin(coating) is inserted in the trench.In step 108, the oxide skin(coating) in etchback groove, to reduce the height of this oxide skin(coating).In step 110, remove curtain layer of hard hood, and removing in step with its lower gate material layers of barrier protect oxide layer.In step 112, remove barrier oxide layer, and expose gate material layers.
Fig. 2 to Figure 11 then shows the semiconductor device that formed according to the method for Fig. 1 in one embodiment profile in each fabrication stage.Understand concept of the present invention in order to clearer, easy, Fig. 2 to Figure 11 is through simplifying.In certain embodiments, can increase extra element in semiconductor devices, in other embodiments, some elements in following semiconductor device then can be substituted or remove.
With reference to Fig. 2, substrate 200 is provided, and forms gate dielectric 202 on substrate 200.In one embodiment, substrate 200 comprises silicon substrate, sige substrate or semiconductor on insulator (semiconductor-on-insulator) substrate.Gate dielectric 202 can comprise dielectric material as silica, high-k dielectric materials, other dielectric material be applicable to or aforementioned combinations.In one embodiment, gate dielectric 202 can be the tunnel oxide layer (tunneloxidelayer) utilizing thermal oxidation manufacturing process to be formed.In another embodiment, the additive method such as chemical vapour deposition (CVD) (CVD), ald (ALD) also can be utilized to form gate dielectric 202.
With reference to Fig. 3, gate dielectric 202 forms gate material layers 204.In one embodiment, gate material layers 204 comprises polysilicon layer.The formation of gate material layers 204 can utilize deposition process, such as chemical vapour deposition (CVD) (CVD).
With reference to Fig. 4, gate material layers 204 forms barrier oxide layer 206.Barrier oxide layer 206 can comprise silica, silicon oxynitride, aluminium oxide, lanthana, hafnium oxide, zirconia, nitrogen hafnium oxide or aforementioned combination.Barrier oxide layer 206 can utilize any applicable manufacturing process to be formed, such as thermal oxidation method, chemical vapour deposition (CVD), spin coating etc.In one embodiment, the formation of barrier oxide layer 206 can be silicon oxide dielectric layer (siliconoxidedielectric) of growing up in gate material layers 204.
With reference to Fig. 5, barrier oxide layer 206 forms curtain layer of hard hood 208.Curtain layer of hard hood 208 can comprise silicon nitride layer or other hard mask material be applicable to.The formation of curtain layer of hard hood 208 can utilize deposition process, such as chemical vapour deposition (CVD) (CVD).
With reference to Fig. 6, curtain layer of hard hood 208 forms patterning photoresist layer 210.The formation of patterning photoresist layer 210 can utilize photoresist and the method for any known or future development.With reference to Fig. 7, utilize patterning photoresist layer 210 to be cover curtain, sequentially etch curtain layer of hard hood 208, barrier oxide layer 206, gate material layers 204, gate dielectric 202 and substrate 200, to form groove 212 in substrate 200.Above-mentioned etching manufacturing process can comprise dry etching, as electricity slurry etching or reactive ion etching.
With reference to Fig. 8, after formation groove 212, clean after ashing is carried out to the structure of Fig. 7, and remove patterning photoresist layer 210.With reference to Fig. 9, in groove 212, insert oxide skin(coating) 214, make oxide skin(coating) 214 on the whole fill up groove 212.Oxide skin(coating) 214 is such as silicon dioxide.The formation of oxide skin(coating) 214 can utilize thermal oxidation method, such as, react 14 seconds to 22 seconds under 900 ° of C to 1050 ° of C.It should be noted, in the process forming oxide skin(coating) 214, the corner of gate material layers 204 can be oxidized in the lump, and form the corner of circular arc.
With reference to Figure 10, the oxide skin(coating) 214 in etchback groove 212, to reduce the height of oxide skin(coating) 214.In one embodiment, the upper surface of oxide skin(coating) 214 can on the whole between the upper and lower surface of gate material layers 204.With reference to Figure 11, remove curtain layer of hard hood 208, and utilize barrier oxide layer 206 to protect gate material layers 204 below it.In one embodiment, wet etching can be utilized to lose manufacturing process and to remove curtain layer of hard hood 208, such as, utilize hot phosphoric acid to etch.Then, then remove barrier oxide layer 206, and expose gate material layers 204, as shown in figure 12.In traditional manufacturing process, when removing curtain layer of hard hood with hot phosphoric acid etching, directly can expose gate material layers, now hot phosphoric acid can infiltrate in gate material layers along the lattice of gate material layers (as polysilicon layer), and formed element efficiency is suffered damage.But, in this embodiment, be utilize extra barrier oxide layer 206 to protect gate material layers 204 not to be subject to the infringement of hot phosphoric acid, then remove barrier oxide layer 206 with the manufacturing process that can not damage gate material layers 204 again.The method removing barrier oxide layer 206 such as comprises buffered oxide etch (bufferedoxideetch; BHF).
It should be noted, when carrying out etchback step to the oxide skin(coating) 214 that Fig. 9 was formed, a part 216 for oxide skin(coating) 214 still can remain on the sidewall of groove 212, as shown in Figure 10.Therefore, after removing curtain layer of hard hood 208, another etching manufacturing process generally need be utilized to remove the residual fraction 216 of oxide skin(coating).In this embodiment, single etching manufacturing process can be utilized, remove the residual fraction 216 of barrier oxide layer 206 and oxide skin(coating) simultaneously.That is barrier oxide layer 206 not only can protect gate material layers 204 in the etching manufacturing process removing curtain layer of hard hood 208, and can remove in the lump in the etch step of residual fraction 216 removing oxide skin(coating), and not need extra manufacturing technology steps.In a preferred embodiment, on the whole the thickness that oxide skin(coating) 214 remains in the part 216 of sidewall equal the thickness of barrier oxide layer 206.Such as, the thickness of barrier oxide layer 206 can between 5nm to 10nm.
With reference to Figure 12, the gate material layers 204 exposed after removing barrier oxide layer 206 has the corner of circular arc.The ill effect of element point electric discharge (pointdischarge) formed in subsequent manufacturing procedures can be avoided in the corner of this circular arc.In one embodiment, gate material layers 204 can be used as the floating grid in flash memory device.
In one embodiment, can be applied on above-mentioned semiconductor structure in the manufacturing process of not b gate flash memory (NANDflashmemory).Such as, after removing barrier oxide layer 206, in gate material layers 204, further sequentially form oxygen-nitrogen-oxygen (ONO) layer 218 and control gate layer 220, as shown in figure 13, O-N-O layer 218 is conformably formed on gate material layers 204 and oxide skin(coating) 214.Control gate layer 220 is such as polysilicon, and it is cover on O-N-O layer 218 and have a smooth plane.In various embodiments of the invention, the method for any known or future development and material can be utilized to form O-N-O layer 218 and control gate layer 220.In this embodiment, the corner of gate material layers 204 circular arc is conducive to the formation of O-N-O layer 218, can avoid the generation of space (voids).
In various embodiments of the invention; a kind of undamaged floating gate structure can be provided; barrier oxide layer can be utilized as the protective layer of gate material layers, affect element efficiency to avoid gate material layers to suffer damage in the etching manufacturing process removing curtain layer of hard hood.In addition, formed in the trench in the step of oxide skin(coating), gate material layers can be made to form circular arc corner, the problem of discharging to avoid element point.In addition, the etch step removing the oxide skin(coating) that trenched side-wall remains can be utilized, remove above-mentioned barrier oxide layer in the lump, therefore not need to carry out extra manufacturing technology steps again and removed.
Although the present invention discloses as above with several preferred embodiment; so itself and be not used to limit the present invention; have in any art and usually know the knowledgeable; without departing from the spirit and scope of the invention; when doing any change and retouching, the protection range of therefore the present invention is when being as the criterion with the claims in the present invention scope person of defining.
Claims (9)
1. a formation method for semiconductor device, is characterized in that, described formation method comprises:
One substrate is provided, described substrate is sequentially formed a gate dielectric, a gate material layers, a barrier oxide layer and a curtain layer of hard hood;
Sequentially etch described curtain layer of hard hood, described barrier oxide layer, described gate material layers, described gate dielectric and described substrate, to form a groove in described substrate;
Monoxide layer is inserted in described groove;
Described oxide skin(coating) in groove described in etchback, to reduce the height of described oxide skin(coating);
Remove described curtain layer of hard hood, and remove in step with its lower described gate material layers of described barrier protect oxide layer described; And
Remove described barrier oxide layer, and expose described gate material layers, the gate material layers described in exposing after removing described barrier oxide layer has the corner of circular arc.
2. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, described oxide series of strata are formed with thermal oxidation method, and described gate material layers forms the corner of circular arc in described step of thermal oxidation.
3. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, described gate dielectric comprises tunnel oxide layer.
4. the formation method of semiconductor device as claimed in claim 1, is characterized in that, removing of described curtain layer of hard hood is utilize wet etching to lose manufacturing process, and removing of described barrier oxide layer is utilize dry etching manufacturing process.
5. the formation method of semiconductor device as claimed in claim 4, it is characterized in that, removing of described curtain layer of hard hood is utilize hot phosphoric acid to etch, and removing of described barrier oxide layer is utilize buffered oxide etch.
6. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, after oxide skin(coating) described in the groove described in etchback, a part for described oxide skin(coating) still remains on the sidewall of described groove, and removes residual part in the lump when removing described barrier oxide layer.
7. the formation method of semiconductor device as claimed in claim 6, is characterized in that, on the whole the thickness that described oxide skin(coating) remains in the described part of sidewall equal the thickness of described barrier oxide layer.
8. the formation method of semiconductor device as claimed in claim 1, is characterized in that, after removing described barrier oxide layer, be more included in described gate material layers and form an O-N-O layer.
9. the formation method of semiconductor device as claimed in claim 8, it is characterized in that, described method is more included on described O-N-O layer and forms a control gate.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101017799A (en) * | 2006-02-07 | 2007-08-15 | 海力士半导体有限公司 | Method of manufacturing a flash memory device |
| TWI334633B (en) * | 2005-03-30 | 2010-12-11 | Winbond Electronics Corp | Non-volatile memory device and method of fabricating the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI334633B (en) * | 2005-03-30 | 2010-12-11 | Winbond Electronics Corp | Non-volatile memory device and method of fabricating the same |
| CN101017799A (en) * | 2006-02-07 | 2007-08-15 | 海力士半导体有限公司 | Method of manufacturing a flash memory device |
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