CN112750790A - Flash memory and manufacturing method thereof - Google Patents
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- CN112750790A CN112750790A CN202110093752.7A CN202110093752A CN112750790A CN 112750790 A CN112750790 A CN 112750790A CN 202110093752 A CN202110093752 A CN 202110093752A CN 112750790 A CN112750790 A CN 112750790A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
The invention provides a flash memory and a manufacturing method thereof.A separation structure which extends towards an initial floating gate layer and covers the upper surface of the initial floating gate layer is formed in the initial floating gate layer, so that when part of the initial floating gate layer is etched to form the floating gate layer, the part of the initial floating gate layer covered by the separation structure is not etched, and at least the part of the floating gate layer covered by the separation structure forms a floating gate tip. When the floating gate tip formed by the manufacturing method of the flash memory is subjected to electron erasing operation, a local electric field can be enhanced, and the erasing efficiency is improved.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a flash memory and a method for manufacturing the same.
Background
Flash memory is an important device in integrated circuit products. The main feature of flash memory is to retain the stored information for a long period of time without the application of a voltage. Flash memories have the advantages of high integration, fast access speed, easy erasing, etc., and thus are widely used.
Current flash memories are divided into two types: stacked gate flash memory and split gate flash memory. The stacked gate flash memory has a floating gate and a control gate above the floating gate, and the control gates in the same column are connected to be used as word lines. Different from a stacked gate flash memory, the split gate flash memory forms a word line serving as an erase gate on one side of a floating gate, and programs by utilizing hot electron injection of a source end, so that the split gate flash memory has higher programming efficiency.
However, the self-aligned split-gate flash memory formed in the prior art has poor erasing performance, a high voltage needs to be applied to a word line in the erasing process, and a large area of a peripheral circuit needs to be occupied in design, so that the power consumption of the device is high when the device is erased.
Disclosure of Invention
The invention aims to provide a flash memory and a manufacturing method thereof, which aim to solve the problem that the power consumption is higher when the existing split gate flash memory is erased.
To solve the above problems, the present invention provides a method for manufacturing a flash memory,
providing a substrate;
forming an initial floating gate layer on the substrate, wherein a first groove extending to the substrate is formed in the initial floating gate layer;
forming an isolation structure, wherein the isolation structure fills the first groove and extends to cover part of the upper surface of the initial floating gate layer;
etching the initial floating gate layer to form a floating gate tip at least on the part of the initial floating gate layer covered by the isolation structure so as to form a floating gate layer;
and etching the floating gate layer to form a second groove, and forming an erasing gate layer in the second groove.
Optionally, the method for forming the first trench and the isolation structure includes:
sequentially forming a floating gate material layer and a first mask layer with a first opening on the substrate;
etching the floating gate material layer and the substrate by taking the first mask layer as a mask, and stopping on the substrate to form the initial floating gate layer and the first groove;
etching the first mask layer to enlarge the first opening;
and forming the isolation structure in the enlarged first opening and the first groove so that the isolation structure extends to cover part of the upper surface of the initial floating gate layer.
Optionally, the increased width of the first opening is 0.02um to 0.08 um.
Optionally, the method for forming the isolation structure and the initial floating gate layer includes:
forming a floating gate material layer on the substrate;
sequentially etching the floating gate material layer and the substrate and stopping on the substrate to form the initial floating gate layer and the first groove;
forming an isolation material layer on the first trench and the upper surface of the initial floating gate layer;
and etching the isolation material layer to enable the isolation structure to cover part of the upper surface of the initial floating gate layer so as to form the isolation structure.
Optionally, the width of the isolation structure covering the upper surface of the initial floating gate layer is 0.01um to 0.04 um.
Optionally, the height difference between the top and the bottom of the floating gate tip is 10nm to 30 nm.
Optionally, the method for forming the erase gate layer includes:
forming a mask function layer on the isolation structure and the floating gate layer, wherein a first slot is formed in the mask function layer, and a part of the isolation structure and the floating gate layer are exposed out of the first slot;
etching the floating gate layer by taking the mask function layer as a mask so as to form a second groove in the floating gate layer;
and forming the erasing gate layer in the second groove.
Optionally, the method for forming the mask function layer includes:
forming a second mask layer on the floating gate layer and the isolation structure, wherein a third groove is formed in the second mask layer;
and forming a side wall on the side wall of the third groove to form the mask function layer by using the side wall and the second mask layer, and defining the first groove by the side wall on the side wall opposite to the third groove.
Optionally, before forming the erase gate layer in the second trench, the method further includes: and forming an oxide layer on the side wall and the bottom of the second groove.
In order to solve the above problems, the present invention further provides a flash memory, which is manufactured according to the method for manufacturing a flash memory as described in any one of the above embodiments.
According to the manufacturing method of the flash memory, the isolation structure which extends towards the initial floating gate layer and covers the upper surface of the initial floating gate layer is formed in the initial floating gate layer, so that when part of the initial floating gate layer is etched to form the floating gate layer, the part of the initial floating gate layer covered by the isolation structure is not etched, and at least the part of the formed floating gate layer covered by the isolation structure forms a floating gate tip. When the floating gate tip formed by the method is used for carrying out electron erasing operation, a local electric field can be enhanced, and erasing efficiency is improved.
Drawings
FIG. 1 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the present invention;
FIGS. 2-10 are schematic structural views of a semiconductor manufacturing method in the fabrication process thereof according to an embodiment of the present invention;
wherein the reference numbers are as follows:
10-a substrate;
20-a first dielectric layer; 200-a first dielectric material layer;
3-floating gate; 30' -an initial floating gate layer;
30-a floating gate layer; 300-a layer of floating gate material;
40-a first mask layer;
50-an isolation structure;
60-a mask functional layer; 61-a second mask layer;
62-a first side wall; 600-a layer of mask material;
71-a second side wall; 72-a third side wall;
73-a fourth side wall;
80-an erase gate layer;
90-word lines;
101-a first opening; 102-a second opening;
100-a first trench;
201-first slot; 202-second grooving;
200-second trench.
Detailed Description
The following describes a flash memory and a method for manufacturing the same in detail with reference to the accompanying drawings and embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
FIG. 1 is a flow chart of a method for manufacturing a flash memory according to an embodiment of the present invention; fig. 2 to 10 are schematic structural views of a semiconductor manufacturing method in a manufacturing process thereof according to an embodiment of the present invention. The steps of the method for manufacturing the backside illuminated sensor according to the present embodiment will be described in detail with reference to fig. 1 to 10.
In step S10, as shown in fig. 2, a substrate 10 is provided, and an initial floating gate layer 30' is formed on the substrate 10. In this embodiment, the substrate 10 may include a semiconductor material, an insulating material, a conductor material, or any combination thereof, and may have a single-layer structure or a multi-layer structure. Thus, the substrate may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. Layered substrates such as, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator may also be included.
In step S20, as shown in fig. 3, an initial floating gate layer 30 'is formed on the substrate 1, and a first trench 100 extending to the substrate is formed in the initial floating gate layer 30'.
In step S30, as shown in fig. 5, an isolation structure 50 is formed, wherein the isolation structure 50 fills the first trench 100 and extends to cover a portion of the upper surface of the initial floating gate layer 30'. In this embodiment, the width of the isolation structure covering the upper surface of the initial floating gate layer 30' is 0.01um to 0.04 um.
In the present embodiment, the method for forming the first trench 100 and the isolation structure 50 includes the following steps one to four.
In step one, as shown in fig. 2 and 3, a floating gate material layer 300 and a first mask layer 40 having a first opening 101 are sequentially formed on the substrate 10.
The material of the first mask layer 40 may be silicon nitride, and the method for forming the first mask layer 40 may be sequentially forming a first mask material layer (not shown) and a photoresist layer (not shown) on the floating gate material layer 300, and etching the first mask material layer (not shown) by using the photoresist layer (not shown) as a mask to form the first mask layer 40. And, the material of the floating gate material layer 300 may be polysilicon.
In addition, in this embodiment, before forming the floating gate material layer 300 on the substrate 10, the method further includes: a first dielectric material layer 200 is formed on the substrate 10, wherein the material of the first dielectric material layer 200 may be silicon oxide.
In a second step, as shown in fig. 3, the floating gate material layer 300 and the substrate 10 are sequentially etched using the first mask layer 40 as a mask to form an initial floating gate layer 30 ', and the first opening 101 extends to the initial floating gate layer 30 ' and the substrate 10, and stops in the substrate 10 to form the initial floating gate layer 30 ' and the first trench 100.
In the present embodiment, after the first opening 101 extends to the initial floating gate layer 30' and the substrate 10, a second opening 102 is formed, and the first opening 101 and the second opening 102 penetrate to form a first trench 100. In this embodiment, while the floating gate material 300 and the substrate 10 are sequentially etched using the first mask layer 40 as a mask, the method further includes: the first dielectric material layer 200 is etched to form a first dielectric layer 20, and the second opening 102 extends through the first dielectric layer 20.
In this embodiment, the etching method for etching the floating gate material layer 300 and the substrate 10 may be wet etching or dry etching. The specific etching method is not specifically limited herein, and is subject to the actual situation.
In step three, as shown in fig. 4, the first mask layer 40 is etched to increase the width of the first opening 101,
in this embodiment, the first opening 101 has an increased width of 0.02um to 0.08 um. And the increased width of the first opening 101 is greater than the width of the second opening 102.
Further, in this embodiment, an etching method for etching the first mask layer 40 is wet etching, and in an alternative embodiment, an etching method of the second etching process may also be dry etching.
In step four, as shown in fig. 5, the isolation structure 50 is formed in the first trench 100 of the enlarged first opening 101, so that the isolation structure 50 extends to cover a part of the upper surface of the initial floating gate layer 30'. In this embodiment, the method for forming the isolation structure 50 may include: an isolation material is deposited on the upper surfaces of the first trench 100 and the first mask layer 40 to form an isolation material layer, and then the isolation material layer on the upper surface of the first mask layer 40 is removed by grinding to form an isolation structure 50 in the first trench 100. In this embodiment, the isolation material may be silicon oxide or silicon nitride, and the method for depositing the isolation material includes a chemical vapor deposition method.
Alternatively, the method of forming the first trench 100 and the isolation structure 50 may further include the following first to fourth steps.
In a first step, a layer of floating gate material 300 is formed on the substrate 10, as shown in fig. 2.
In a second step, as shown in fig. 3, the floating gate material layer 300 and the substrate 10 are sequentially etched and stopped in the substrate 10 to form the initial floating gate layer 30' and the first trench 100.
In a third step, a layer of isolating material is formed on the upper surfaces of the first trenches 100 and the initial floating gate layer 30'. In this step, the spacer material layer may be formed by depositing a spacer material by a chemical vapor deposition method.
In a fourth step, the isolation material layer is etched to form the isolation structure 50, and the isolation structure 50 covers a part of the upper surface of the initial floating gate layer 30'. In this embodiment, a photoresist layer may be formed on the isolation material layer, the photoresist layer has a plurality of third openings therein, the third openings are located on the initial floating gate layer 30 'and the width of the third openings is smaller than that of the initial floating gate layer 30' between adjacent isolation structures 50. And etching the isolation material layer by using the photoresist layer as a mask to form the isolation structure 50.
In step S40, as shown in fig. 6, in the present embodiment, the initial floating gate layer 30 'is etched to form the floating gate layer 30, and floating gate tips a are formed at least in the portion of the initial floating gate layer 30' covered by the isolation structure 50.
In this embodiment, as shown in fig. 6, in this embodiment, the initial floating gate layer 30 'between adjacent isolation structures 50 is etched to remove a portion of the initial floating gate layer 30' away from the substrate 10. This is done so that the initial floating gate layer 30' located below the top of the isolation structure 50 is retained to form the floating gate tip a. The etched floating gate layer 30 is in an arc shape at a portion between adjacent isolation structures 50. In this embodiment, the etching method for etching the initial floating gate layer is dry etching.
And, in the present embodiment, the height difference between the top and bottom of the floating gate tip a is formed to be 10nm to 30 nm. Thus, the discharge effect of the floating gate tip A is optimal. Wherein the top refers to the end of the floating gate tip farthest from the substrate 10, and the bottom is the end of the floating gate tip contacting the substrate 10.
In step S50, as shown in fig. 10, the floating gate layer 30 is etched to form a second trench 200, and an erase gate layer 80 is formed in the second trench 200. Wherein, the extension direction of the erase gate 80 is the same as the extension direction of the isolation structure 50.
In the present embodiment, as shown in fig. 7, the method of forming the erase gate layer 80 includes the following steps one to three.
In step one, referring to fig. 7 to 10, a mask function layer 60 is formed on the isolation structure 50 and the floating gate layer 30, wherein a first open groove 201 is formed in the mask function layer 60, and a portion of the isolation structure 50 and the floating gate layer 30 is exposed from the first open groove 201. In this embodiment, the extending direction of the first slot 201 and the extending direction of the isolation structure 50 are perpendicular to each other.
In a second step, as shown in fig. 9, the floating gate layer 30 is etched by using the mask function layer 60 as a mask, so as to form a second open groove 202 in the floating gate layer 30, and the first open groove 201 and the second open groove 202 penetrate to form a second trench 200. In addition, in this embodiment, while the floating gate layer 30 is etched, the method further includes etching the first dielectric layer 20, so that the second trench 202 extends into the first dielectric layer 20.
In the present embodiment, the method for forming the mask function layer 60 includes the following steps.
First, as shown in fig. 8, a second mask layer 61 is formed on the floating gate layer 30 and the isolation structure 50, and a third trench (not shown) is opened in the second mask layer 61.
Next, a sidewall 62 is formed on the sidewall of the third trench (not shown), so that the sidewall 62 and the second mask layer 61 form the mask function layer 60, and the sidewall 62 on the opposite sidewall of the third trench (not shown) defines the first trench 201. The second mask layer 61 and the sidewall spacers 62 may be made of silicon nitride or silicon oxide.
In step three, the erase gate layer 80 is formed within the second trench 200. In this embodiment, the erase gate layer 80 may be made of polysilicon, wherein the method for forming the erase gate layer 80 may include: a polysilicon layer is formed on the upper surfaces of the second trench 200 and the mask function layer 60, and the polysilicon layer on the upper surface of the mask function layer 60 is removed by grinding to form the erase gate layer 80 in the second trench 200.
In addition, in this embodiment, before forming the erase gate layer 80 in the trench 200, the method further includes: a first oxide layer 71 is formed on the sidewalls and bottom of the second trench 200. The first oxide layer 71 may be made of silicon oxide, and the first oxide layer 71 is used to insulate the floating gate layer 30 and the erase gate layer 80.
Further, as shown in fig. 10, after forming the erase gate layer 80, the method further includes: and removing the second mask layer 61, and removing part of the first dielectric layer 20 and the floating gate layer 30 by taking the first side wall 62 as a mask through self-aligned etching. And forming a third sidewall 72 on the sidewall of the etched floating gate layer 30, forming a word line 90 on the sidewall of the third sidewall 72, and forming a fourth sidewall 73 on the sidewall of the word line 90. The third side wall 72 and the fourth side wall 73 may be made of silicon oxide. The third sidewall 72 is used for insulating the etched floating gate layer 30 and the word line 90.
Further, the embodiment also discloses a flash memory, and the flash memory is prepared according to the manufacturing method of the flash memory.
It should be noted that, in the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, similar parts between the embodiments may be referred to each other, and different parts between the embodiments may also be used in combination with each other, which is not limited by the present invention.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method for manufacturing a flash memory is characterized in that,
providing a substrate;
forming an initial floating gate layer on the substrate, wherein a first groove extending to the substrate is formed in the initial floating gate layer;
forming an isolation structure, wherein the isolation structure fills the first groove and extends to cover part of the upper surface of the initial floating gate layer;
etching the initial floating gate layer to form a floating gate tip at least on the part of the initial floating gate layer covered by the isolation structure so as to form a floating gate layer;
and etching the floating gate layer to form a second groove, and forming an erasing gate layer in the second groove.
2. The method of manufacturing a flash memory of claim 1, wherein the method of forming the first trench and the isolation structure comprises:
sequentially forming a floating gate material layer and a first mask layer with a first opening on the substrate;
etching the floating gate material layer and the substrate by taking the first mask layer as a mask, and stopping on the substrate to form the initial floating gate layer and the first groove;
etching the first mask layer to enlarge the first opening;
and forming the isolation structure in the enlarged first opening and the first groove so that the isolation structure extends to cover part of the upper surface of the initial floating gate layer.
3. The method of claim 2, wherein the width of the first opening increases from 0.02um to 0.08 um.
4. The method of manufacturing a flash memory of claim 1, wherein the method of forming the isolation structure and the initial floating gate layer comprises:
forming a floating gate material layer on the substrate;
sequentially etching the floating gate material layer and the substrate and stopping on the substrate to form the initial floating gate layer and the first groove;
forming an isolation material layer on the first trench and the upper surface of the initial floating gate layer;
and etching the isolation material layer to form the isolation structure, and enabling the isolation structure to cover part of the upper surface of the initial floating gate layer.
5. The method of claim 1, wherein the isolation structure covers the top surface of the initial floating gate layer with a width of 0.01um to 0.04 um.
6. The method of manufacturing a flash memory of claim 1, wherein a height difference between the top and the bottom of the tip of the floating gate is 10nm to 30 nm.
7. The method of manufacturing a flash memory of claim 1, wherein the method of forming the erase gate layer comprises:
forming a mask function layer on the isolation structure and the floating gate layer, wherein a first slot is formed in the mask function layer, and a part of the isolation structure and the floating gate layer are exposed out of the first slot;
etching the floating gate layer by taking the mask function layer as a mask so as to form a second groove in the floating gate layer;
and forming the erasing gate layer in the second groove.
8. The method of manufacturing a flash memory of claim 7, wherein the method of forming the mask function layer comprises:
forming a second mask layer on the floating gate layer and the isolation structure, wherein a third groove is formed in the second mask layer;
and forming a side wall on the side wall of the third groove to form the mask function layer by using the side wall and the second mask layer, and defining the first groove by the side wall on the side wall opposite to the third groove.
9. The method of manufacturing a flash memory of claim 8, wherein before forming the erase gate layer within the second trench, the method further comprises: and forming an oxide layer on the side wall and the bottom of the second groove.
10. A flash memory prepared by the method of any one of claims 1 to 9.
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