CN105679713A - Method for manufacturing flash memories - Google Patents
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- CN105679713A CN105679713A CN201610264764.0A CN201610264764A CN105679713A CN 105679713 A CN105679713 A CN 105679713A CN 201610264764 A CN201610264764 A CN 201610264764A CN 105679713 A CN105679713 A CN 105679713A
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- 238000005530 etching Methods 0.000 claims abstract description 273
- 230000008569 process Effects 0.000 claims abstract description 42
- 230000004888 barrier function Effects 0.000 claims description 47
- 239000000463 material Substances 0.000 claims description 29
- 239000000758 substrate Substances 0.000 claims description 24
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- 238000005516 engineering process Methods 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
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- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
Abstract
A method for manufacturing flash memories comprises the following steps: a graphical hard mask layer forms an opening penetrating a hard mask layer in a thickness direction; a floating gate layer with a first thickness below the opening is etched and removed with a first etching process, wherein etching time of the first etching process is determined based on the initial thickness of the floating gate layer below the opening before the first etching process, so that the thickness of the floating gate layer after the first etching process is completed is a fixed value; after the first etching process, a second etching process is adopted to etch and remove the floating gate layer with a second thickness, part of the floating gate layer below the hard mask layer is also etched and removed, and a floating gate tip region is formed below the hard mask layer, wherein the etching time of the second etching process is fixed. The method improves the morphological stability of formed floating gate tips, so that the yield of manufactured flash memories is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly to the manufacture method of a kind of flush memory device.
Background technology
In current semiconductor industry, IC products can be divided mainly into three major types type: analog circuit, digital circuit and D/A hybrid circuit, wherein, and an important kind in digital circuit during memory device. And in memory device, the development in flash memory in this year (FlashMemory is called for short flash memory) is particularly rapid. The information being mainly characterized by when not powered keeping for a long time storage of flash memory; And there is integrated level height, storage speed is fast, be prone to the advantages such as erasing and rewriting, thus be widely used in the multinomial field such as microcomputer, Automated condtrol.
Flush memory device mainly includes gate stack (StackGate) structure and point grid (SplitGate) structure, wherein, grid dividing structure is owing to having higher programming efficiency, functionally can avoid excessive erasable problem erasable, thus be widely used in all kinds of such as smart card, SIM, microcontroller, mobile phone and step in electronic product.
But, the yield of flush memory device of the prior art has much room for improvement.
Summary of the invention
The problem that this invention address that is to provide the manufacture method of a kind of flush memory device, it is ensured that have good and stable floating boom tip pattern in each flush memory device, improves the flush memory device yield formed in semiconductor technology processing procedure.
For solving the problems referred to above, the present invention provides the manufacture method of a kind of flush memory device, including: substrate is provided, is positioned at suprabasil coupling oxide layer and is positioned at the floating gate layer on described coupling oxide layer; Described floating gate layer is formed hard mask layer; Graphical described hard mask layer forms the opening running through described hard mask layer thickness; The first etching technics etching is adopted to remove the floating gate layer being positioned at the first thickness below described opening, wherein, according to the original depth carrying out described first etching technics anteposition floating gate layer below opening, determine the etching duration of described first etching technics so that the first etching technics is positioned at the thickness of the floating gate layer below described opening after completing be fixed value;After carrying out described first etching technics, the second etching technics etching is adopted to remove the floating gate layer of the second thickness, and also etching removes the part floating gate layer being positioned at below hard mask layer, floating boom tip region is formed in described floating gate layer, wherein, the etching duration of described second etching technics is fixing duration; Etching removes described hard mask layer, exposes described floating gate layer; The floating gate layer exposed described in etching, until exposing coupling oxide layer, forms floating boom in the position at described floating boom tip region place most advanced and sophisticated.
Optionally, before adopting, feedback etching system carries out described first etching technics; Before carrying out described first etching technics, measure the original depth being positioned at the floating gate layer below described opening.
Optionally, described second etching technics is isotropic dry etch process.
Optionally, before forming described hard mask layer, described floating gate layer is formed barrier layer, and described barrier layer is between described floating gate layer and described hard mask layer, the material on described barrier layer is different from the material of described hard mask layer, and the material on described barrier layer is different from the material of floating gate layer; Described open bottom exposes described barrier layer surface.
Optionally, before carrying out described first etching technics, further comprise the steps of: and remove the barrier layer that described open bottom is exposed, until exposing floating gate layer surface.
Optionally, the material on described barrier layer is silicon oxide; The material of described hard mask layer is silicon nitride.
Optionally, adopting wet-etching technology etching to remove the barrier layer that described open bottom is exposed, wherein, the etch liquids that wet-etching technology adopts is hydrofluoric acid solution.
Optionally, being formed at graphical described hard mask layer in the technical process of opening running through described hard mask layer, also etching removes the floating gate layer being positioned at the segment thickness below described opening.
Optionally, described manufacture method carries out in units of lot; After carrying out described first etching technics, the thickness being positioned at the floating gate layer below opening in each lot is fixed value.
Optionally, after described second etching technics, etch described hard mask layer before, further comprise the steps of: and form the first side wall film covering the floating gate layer below described opening and opening; Adopting and etch described first side wall film without mask etching technique, form the first side wall covering described opening sidewalls and floating boom tip region sidewall, described first side wall is also located on part floating gate layer; Etching removes the floating gate layer that adjacent first side wall exposes, and exposes floating gate layer sidewall surfaces; Form the second side wall covering floating gate layer sidewall and the first side wall sidewall; Full source line layer is filled between adjacent second side wall.
Compared with prior art, technical scheme has the advantage that
In the technical scheme of the manufacture method of flush memory device provided by the invention, formed in hard mask layer after the opening running through its thickness, the first etching technics etching is adopted to remove the first floating gate layer being positioned at below opening, and first the etching duration of etching technics be determined according to the original depth of first etching technics anteposition floating gate layer below opening, thereby ensure that it is fixed value that the first etching technics completes the thickness of floating gate layer below after-opening; Corresponding after the first etching technics completes below the opening in each lot the thickness of floating gate layer be fixed value and thickness identical. Simultaneously, in the present invention in carrying out the process that the second etching technics formation floating boom is most advanced and sophisticated, the etching duration of the second etching technics is fixed value, and due to below the second etching technics open front the thickness of floating gate layer be fixed value and identical, therefore when the etching duration of the second etching technics is fixed value, below opening after the second etching technics forms floating boom tip region, the thickness of floating gate layer also will for fixed value, that is, after the second etching technics completes, below the opening in each lot, the thickness of floating gate layer is identical, meets process requirements.
In addition, owing to the etching duration of the second etching technics is fixing duration, and the thickness of floating gate layer is fixed value before the second etching technics, therefore the height and the radian that experience the floating boom tip region that described second etching technics is formed also will have stable state, the corresponding floating boom tip varying topography formed in the position at floating boom tip region place is little, therefore the floating boom tip in each lot is respectively provided with good pattern, avoid the occurrence of floating boom tip in some or certain some lot to cross and exceed sharp-pointed problem, also avoid the occurrence of the most advanced and sophisticated too low excessively blunt problem of floating boom in some or certain some lot, thus improving the yield of the flush memory device of manufacture.
Further, formed in the technical process of opening in etching, floating gate layer is served barrier effect by described barrier layer, make the floating gate layer below with a piece of wafer split shed from etching injury, therefore the consistency of thickness with the floating gate layer below a piece of wafer split shed is good, thus improving the pattern with the most advanced and sophisticated floating gate layer of floating boom of formation, for instance the thickness evenness with the most advanced and sophisticated floating gate layer of floating boom is good.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is a kind of cross-sectional view forming flush memory device process;
The cross-sectional view forming flush memory device process that Fig. 6 to Figure 12 provides for one embodiment of the invention;
The cross-sectional view forming flush memory device process that Figure 13 to Figure 17 provides for another embodiment of the present invention.
Detailed description of the invention
By background technology it can be seen that the yield of flush memory device that prior art is formed has much room for improvement.
Fig. 1 to Fig. 5 is a kind of cross-sectional view forming flush memory device process.
With reference to Fig. 1, it is provided that substrate 11, the coupling being positioned in substrate 11 aoxidize (CouplingOxide) layer 12, the floating gate layer 13 being positioned on coupling oxide layer 12 and be positioned at the hard mask layer 14 on floating boom 13;
With reference to Fig. 2, graphical described hard mask layer 14 forms the opening 15 running through described hard mask layer 14.
With reference to Fig. 3, with described graphical after hard mask layer 14 for mask, adopt the first etching technics to remove the floating gate layer 13 of the first thickness along described opening 15 etching.
Semiconductor technology processing procedure generally carries out with lot for a unit, remove in the technical process of floating gate layer 13 of the first thickness in etching, the first etching technics duration that each lot carries out is fixing duration, the first etching technics duration that each lot carries out is equal, and the first thickness therefore removed in each lot is fixed value.
Then, with reference to Fig. 4, residue floating gate layer 13 is carried out the second etching technics, etching removes the floating gate layer 13 of the second thickness, and described second etching technics due to have isotropism feature also etch be positioned at graphical after hard mask layer 14 below part floating gate layer 13 so that the floating gate layer 13 after etching has floating boom tip (FloatingGateTip) region 10.
Follow-up processing step also includes, and as shown in Figures 4 and 5, etching is removed described hard mask layer 14 and also etches the floating gate layer 13 being positioned at below hard mask layer 14, forms floating boom tip 20 in the position at floating boom tip region 10 (with reference to Fig. 4) place; And described floating gate layer 13 is performed etching process, and form the discrete floating boom 23 with floating boom tip 20, wherein, the pattern at described floating boom tip 20 is determined by the pattern of floating boom tip region 10.
As it is shown in figure 5, follow-up processing step also includes, form word line layer 15 in the side near floating boom tip 20; Form the floating boom side wall 14 covering floating boom 23 top and sidewall;Formed and fill the source line layer 16 in region between full phase neighbour's floating boom side wall 14; Wherein, described word line layer 15 lays respectively at, with described source line layer 16, the both sides that floating boom 23 is relative, and is formed with tunneling medium layer 17 between described word line layer 15 and described floating boom 23, and the floating boom tip 20 in described floating boom 23 is near described word line layer 15. The pattern (profile) at described floating boom tip 10 is relevant with the performance of flush memory device.
Concrete, the pattern at floating boom tip 20 determines flush memory device size of F-N (Fowler-Nordheim) tunnelling current when erasing, crossing blunt and low tip can make electric field intensity too low, thus occurring that flush memory device erasing electric current is too small, causes the situation that the erasing time is long; Crossing the sharp and high high-end meeting in tip accordingly makes flash memory programming efficiency reduce, and is also unfavorable for the operation of flush memory device.
Fixing to be positioned at the thickness of floating gate layer 13 below opening after making the second etching technics, before adopting, feedback etching system (feedforwardsystem) carries out described second etching technics. Concrete, the thickness of floating gate layer 13 in different lot was measured before carrying out the second etching technics, and determine the technique duration of the second etching technics according to the thickness of the floating gate layer 13 measured, it is ensured that after the second last etching technics, the thickness of floating gate layer 13 is fixed value.
But, the pattern of the floating boom tip region 10 that said method is formed is unstable, and the pattern at the floating boom tip 20 in the floating boom 23 then resulted in is unstable, and bigger diversity occur in height and the radian at the floating boom tip 20 in different lot. Further study show that, cause that main reason is that of bigger diversity occur in the height at the floating boom tip 20 in different lot and radian:
In the process of graphical hard mask layer 14, the floating gate layer 13 that described etching technics can be pointed to below opening 15 causes etching so that floating gate layer 13 has certain etching loss (etchloss), and the thickness of described etching loss is difficult to control to; Therefore, after adopting fixing duration to carry out the first etching technics, the thickness of the residue floating gate layer 13 between actually distinct lot is different; Thickness in order to remain floating gate layer 13 after making the second etching technics complete is identical, and in each lot, the duration of the second etching technics of floating gate layer 13 experience is different, in turn results in floating boom tip region 10 pattern formed in each lot and diversity occurs.
Such as, when in hard mask layer 14 process graphical in a certain lot, the loss of floating gate layer 13 etching is too small, the first thickness owing to removing in each lot is fixed value so that after the first etching technics completes, floating gate layer 13 thickness in this lot is thicker compared with the thickness of the floating gate layer 13 in other lot; For floating gate layer 13 consistency of thickness in lot each after ensureing the second etching technics, second etching technics duration of floating gate layer 13 experience that therefore described thickness is thicker is by longer, in turn resulting in the height of the floating boom tip region 10 formed in this lot higher compared with the height of floating boom tip region 10 formed in other lot and more sharp-pointed (sharper), the floating boom tip 20 formed in this lot accordingly is compared with the floating boom tip 20 formed in other lot more sharply and highly higher.
Again such as, when in hard mask layer 14 process graphical in a certain lot, the loss of floating gate layer 13 etching is excessive, the first thickness owing to removing in each lot is fixed value so that after the first etching technics completes, floating gate layer 13 thickness in this lot is thinner compared with the thickness of the floating gate layer 13 in other lot;Consistency of thickness for the floating gate layer 13 in lot each after ensureing the second etching technics, second etching technics duration of floating gate layer 13 experience that therefore described thickness is thinner is by shorter, in turn resulting in the height height shorter and more blunt (blunter) compared with the floating boom tip region 10 formed in other lot at the floating boom tip 20 formed in this lot, the floating boom tip 20 formed in this lot accordingly is shorter and more blunt compared with the floating boom tip 20 formed in other lot.
Analyzing discovery further, the depositing operation owing to forming floating gate layer 13 has certain technique unstability, is therefore likely to the problem occurring that in each lot, the original depth of the floating gate layer 13 of deposition has diversity. Same, there is deviation, causes that the floating boom tip pattern formed in manufacturing process is unstable in the pattern at this floating boom tip also resulting in formation.
For solving the problems referred to above, the present invention provides the forming method of a kind of flush memory device, including: substrate is provided, is positioned at suprabasil coupling oxide layer and is positioned at the floating gate layer on described coupling oxide layer; Described floating gate layer is formed hard mask layer; Graphical described hard mask layer forms the opening running through described hard mask layer; The first etching technics etching is adopted to remove the floating gate layer being positioned at the first thickness below described opening, wherein, determine the etching duration of described first etching technics according to the original depth of the floating gate layer before carrying out described first etching technics so that described first etching technics complete after the thickness of floating gate layer be fixed value; After carrying out described first etching technics, adopting the second etching technics etching to remove the floating gate layer of the second thickness, also etching removed the part floating gate layer being positioned at below hard mask layer later, formed floating boom tip region, wherein, the etching duration of described second etching technics is fixing duration; Etching removes described hard mask layer, exposes described floating gate layer; The floating gate layer exposed described in etching, until exposing coupling oxide layer, forms floating boom in the position at described floating boom tip region place most advanced and sophisticated.
In the present invention, formed in hard mask layer after the opening running through its thickness, the first etching technics etching is adopted to remove the first floating gate layer being positioned at below opening, and first the etching duration of etching technics be determined according to the original depth of first etching technics anteposition floating gate layer below opening, thereby ensure that it is fixed value that the first etching technics completes the thickness of floating gate layer below after-opening; Corresponding after the first etching technics completes below the opening in each lot the thickness of floating gate layer be fixed value and thickness identical. Simultaneously, in the present invention in the process carrying out the second etching technics formation floating boom tip region, the etching duration of the second etching technics is fixed value, and due to below the second etching technics open front the thickness of floating gate layer be fixed value and identical, therefore when the etching duration of the second etching technics is fixed value, below opening after the second etching technics forms floating boom tip region, the thickness of floating gate layer also will for fixed value, that is, after the second etching technics completes, below the opening in each lot, the thickness of floating gate layer is identical, meets process requirements.
In addition, owing to the etching duration of the second etching technics is fixing duration, and the thickness of floating gate layer is fixed value before the second etching technics, therefore the height and the radian that experience the floating boom tip region that described second etching technics is formed also will have stable state, the varying topography of the floating boom tip region formed in each lot is little, therefore the floating boom tip in each lot is respectively provided with good pattern, avoid the occurrence of floating boom tip in some or certain some lot to cross and exceed sharp-pointed problem, also avoid the occurrence of that floating boom in some or certain some lot is most advanced and sophisticated or too low excessively blunt problem, thus improving the yield of the flush memory device of manufacture.
Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
The cross-sectional view of the flush memory device manufacture process that Fig. 6 to Figure 12 provides for one embodiment of the invention.
With reference to Fig. 6, it is provided that substrate 101, the coupling oxide layer 102 being positioned in substrate 101 and be positioned at the floating gate layer 103 on described coupling oxide layer 102.
Described substrate 101 provides technique platform for manufacturing flush memory device, and described substrate 101 includes flash memory area (sign), it is also possible to include logic device area (sign), follow-up formation flush memory device in the substrate 101 of flash memory area. For making to electrically insulate between described flash memory area and described logic device area, between described flash memory area and logic device area, adopt isolation structure 110 electric insulation. In the present embodiment, described isolation structure 110 top is higher than floating gate layer 103 top.
The material of described substrate 101 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium; Described substrate 101 can also be the silicon substrate on insulator, the germanium substrate on insulator or the germanium silicon substrate on insulator. In the present embodiment, the material of described substrate 101 is silicon.
Described coupling oxide layer 102 is the boundary layer between floating gate layer 103 and substrate 101, plays and makes the effect of electric insulation between floating gate layer 103 and substrate 101. , follow-up being formed after floating boom on the basis of floating gate layer 103, described coupling oxide layer 102 is as the gate dielectric layer between floating boom and substrate 101 meanwhile.
The material of described coupling oxide layer 102 is silicon oxide, silicon oxynitride or silicon oxide carbide. In the present embodiment, the material of described coupling oxide layer 102 is silicon oxide.
Described floating gate layer 103 provides Process ba-sis for the floating boom being subsequently formed flush memory device. Chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process is adopted to form described floating gate layer 103. The polysilicon that material is polysilicon or doping of described floating gate layer 103. In the present embodiment, the material of described floating gate layer 103 is polysilicon.
It should be noted that the manufacture method of the flush memory device of the present embodiment offer carries out in units of lot, i.e. the substrate 101 of single treatment batch. The manufacture method of the flush memory device provided in other embodiments can also carry out with wafer (wafer) for unit, i.e. a piece of substrate of single treatment.
With reference to Fig. 7, described floating gate layer 103 forms barrier layer 104; Forming hard mask layer 105 on described barrier layer 104, wherein, described barrier layer 104 is between described floating gate layer 103 and described hard mask layer 105.
Subsequent patterning described hard mask layer 105 forms the opening running through its thickness, and then, floating gate layer 103 is performed etching by the hard mask layer 105 after graphically changing for mask. For this, the material of described hard mask layer 104 is different from the material of floating gate layer 103. The material of described hard mask layer 104 is silicon nitride, carbonitride of silicium or boron nitride. In the present embodiment, the material of described hard mask layer 104 is silicon nitride.
The material on described barrier layer 104 is different from the material of described hard mask layer 105, and the material on described barrier layer 104 is different from the material of described floating gate layer 103. And, the technique of the graphical hard mask layer 105 of subsequent etching is to having the first selectivity between hard mask layer 105 and floating gate layer 103, subsequent etching removes the technique on barrier layer 104 to having the second selectivity between described barrier layer 104 and floating gate layer 103, and described second selectivity is more than the first selectivity.
Therefore, in the technical process of subsequent patterning hard mask layer 105, the effect of etching stopping is played on described barrier layer 104, it is to avoid floating gate layer 103 is caused etching injury by the technique of described graphical hard mask layer 105;Further, etching is removed the technique on barrier layer 104 and hardly floating gate layer 103 is caused etching injury, thus avoiding the floating boom being subsequently formed and floating boom tip are had undesirable effect.
The material on described barrier layer 104 is silicon oxide, silicon oxynitride or carbon silicon oxynitride; Depositing operation or oxidation technology is adopted to form described barrier layer 104. In the present embodiment, the material on described barrier layer 104 is silicon oxide.
For ensureing that floating gate layer 103 is played enough protective effects by described barrier layer 104, the thickness on described barrier layer 104 should not be excessively thin; Further, if the thickness on described barrier layer 104 is blocked up, the technique duration needed for follow-up removal barrier layer 104 is also corresponding longer, is unfavorable on the one hand improving production efficiency, is also possible on the other hand increase the disadvantageous factor of floating gate layer 103. For this, in the present embodiment, the thickness on described barrier layer 104 is 20 angstroms～600 angstroms.
With reference to Fig. 8, graphical described hard mask layer 105 forms the opening 106 running through described hard mask layer 105 thickness.
In the present embodiment, described opening 106 bottom-exposed goes out surface, barrier layer 104. Adopt dry etch process etching technics, graphical described hard mask layer 105.
In one embodiment, the processing step of graphical described hard mask layer 105 includes: form patterned photoresist layer on described hard mask layer 105; With described patterned photoresist layer for mask, etching described hard mask layer 105 until exposing surface, barrier layer 104, forming described opening 106; Then, described patterned photoresist layer is removed.
In the technical process of graphical described hard mask layer 105; floating gate layer 103 is played a protective role by described barrier layer 104; described floating gate layer 103 is avoided to be exposed in the process environments of graphical described hard mask layer 105, so that floating gate layer 103 keeps good pattern and stable thickness. Especially, for for a piece of wafer, owing to the effect on described barrier layer 104 makes the thickness evenness being positioned at the floating gate layer 103 below opening 106 better, thus being conducive to improving the thickness performance of the follow-up floating boom formed in a piece of wafer.
With reference to Fig. 9, remove the barrier layer 104 exposed bottom described opening 106, until exposing floating gate layer 103 surface.
In order to reduce or avoid etching to remove the impact that floating gate layer 103 is caused by the technique on barrier layer 104 as far as possible, wet-etching technology etching is adopted to remove the barrier layer 104 exposed bottom described opening 106.
In the present embodiment, the material on described barrier layer 104 is silicon oxide, adopts wet-etching technology etching to remove described barrier layer 104, and the etch liquids of wet-etching technology is hydrofluoric acid solution.
With reference to Figure 10, the first etching technics etching is adopted to remove the floating gate layer 103 being positioned at the first thickness below described opening 106 so that described first etching technics is positioned at the thickness of the floating gate layer 103 below opening 106 after completing be fixed value.
Wherein, the etching duration of described first etching technics is determined according to the original depth of the floating gate layer 103 before carrying out described first etching technics.
For this, before carrying out described first etching technics, it is necessary to measure the original depth being positioned at floating gate layer 103 below described opening 106. Concrete, measure the original depth being positioned at the floating gate layer 103 below opening 106 in each lot, original depth according to the floating gate layer 103 measured in different lot, determine the etching duration that each lot is carried out the first etching technics, ensure that the thickness being positioned at the floating gate layer 103 below opening 106 after the first etching technics completes in each lot is fixed value, namely ensure that the thickness being positioned at the floating gate layer 103 below opening 106 after the first etching technics completes in each lot is equal.Such as, when measuring that the original depth of floating gate layer 103 is blocked up below a certain lot split shed 106, then the etching duration that this lot carries out the first etching technics is relatively more longer; Measure when being positioned in a certain lot that below opening 106, the original depth of floating gate layer 103 is crossed thin, then the etching duration that this lot carries out the first etching technics is more relatively much shorter.
In one embodiment, having multi-disc wafer in each lot, a piece of wafer chosen in each lot measures, and according to the original depth of the floating gate layer 103 of a piece of wafer in each lot measured, regulates each lot and carries out the etching duration of the first etching technics. In another embodiment, each lot has multi-disc wafer, choose all wafer in each lot to measure, according to the meansigma methods of the original depth of the floating gate layer 103 of all wafer in each lot measured, regulate each lot and carry out the etching duration of the first etching technics.
In other embodiments, when described manufacture method is with wafer for unit, then measure the original depth being positioned at the floating gate layer below opening in each wafer, original depth according to the described floating gate layer measured in different wafer, determine the etching duration that each wafer is carried out the first etching technics, ensure that the thickness being positioned at the floating gate layer below opening after the first etching technics completes in each wafer is fixed value, namely ensure that the thickness being positioned at the floating gate layer below opening after the first etching technics completes in each wafer is equal.
In the present embodiment, before adopting, feedback etching system (FeedForwardSystem) carries out described first etching technics. Described first etching technics is dry etch process, and in one embodiment, the etching gas that described first etching technics adopts is CF4Or CHF3。
Even if floating gate layer 103 original depth in different lot has diversity before carrying out the first etching technics, determine according to the original depth of floating gate layer 103 before carrying out the first etching technics yet with the etching duration of the first etching technics, after first etching technics is completed, the thickness being positioned at floating gate layer 103 below opening 106 of each lot is identical. Therefore, the etching duration being subsequently formed the second most advanced and sophisticated etching technics of floating boom is fixing duration, the thickness still enabling to the floating gate layer after forming floating boom tip in each lot is fixed value, namely disclosure satisfy that the thickness of the floating gate layer after forming floating boom tip in each lot is identical.
Wherein, it is arranged in floating gate layer 103 original depth below opening 106 there is diversity to be likely to be caused by one or more of following reason:
The depositing operation being previously formed floating gate layer 103 has unstability, causes the original depth of the floating gate layer 103 below different lot split shed 106 diversity occur; Or, floating gate layer 103 is had certain etching to lose by the barrier layer 104 that aforementioned etching is removed bottom opening 106, and described etching loss poor controllability, will also result in the original depth of the floating gate layer 103 below different lot split shed 106 and diversity occurs.
With reference to Figure 11, after carrying out described first etching technics, the second etching technics etching is adopted to remove the floating gate layer 103 of the second thickness, and also etching removes the part floating gate layer 103 being positioned at below hard mask layer 105, in described hard mask layer 105 floating boom tip region 120 formed below, wherein, the etching duration of the second etching technics is fixing duration.
The position at described floating boom tip region 120 place is used for being subsequently formed floating boom tip, it is follow-up after etching is removed described hard mask layer 105 and is positioned at the floating gate layer 103 below hard mask layer 105, form described floating boom most advanced and sophisticated, therefore highly consistent most advanced and sophisticated with the floating boom that is subsequently formed of the height of described floating boom tip region 120, the radian that described floating boom tip region 120 has is consistent with the radian that the floating boom tip being subsequently formed has.
Described second etching technics is isotropic dry etch process, therefore while continuing the floating gate layer 103 of etching removal the second thickness, additionally it is possible to etching removes the part floating gate layer 103 being positioned at below hard mask layer 105.
According to processing performance demand, after the second etching technics completes, being positioned at the thickness of floating gate layer 103 below opening 106 also for fixed value, say, that after the second etching technics completes, the thickness being positioned at floating gate layer 103 below opening 106 in each lot is identical. In other embodiments, after the second etching technics completes, the thickness being positioned at floating gate layer below opening in each wafer is identical.
From Such analysis, owing to being fixed value carrying out the second etching technics and be previously located in the thickness of the floating gate layer 103 below opening 106, therefore when to meet the floating gate layer 103 with floating boom tip region 120 being positioned at below opening 106 and be fixed value, it is desirable to the etching duration of described second etching technics is fixed value.
Further, owing in the present embodiment, the etching duration of the second etching technics is fixed value, the floating boom tip region 120 therefore experiencing the second etching technics formation will have fixing pattern, and described floating boom tip region 120 has fixing height and sharpness. Therefore, for different lot, floating boom tip region 120 pattern in each lot is all identical, namely, height and the sharpness diversity of the floating boom tip region 120 in each lot are little, the stable appearance making the floating boom tip region 120 of formation is good, and the height of the floating boom tip region 120 formed and sharpness are satisfied by process requirements. And in prior art, second etching technics is front feedback etching technics, cause in the variable thickness carrying out second etching technics anteposition floating gate layer below opening, in order to make the second etching technics complete the floating gate layer consistency of thickness below after-opening, the etching duration of the second etching technics of each lot experience differs, in turn resulting in the floating boom tip pattern formed in each lot and have diversity, the stable appearance at the floating boom tip of formation is poor, and then affects electric property and the yield of the flush memory device manufactured.
In addition, in the present embodiment, for for a piece of wafer, due in the technical process of etching formation opening 106, floating gate layer 103 is served barrier effect by described barrier layer 104, make the floating gate layer 103 below with a piece of wafer split shed 106 from etching injury, therefore the consistency of thickness with the floating gate layer 103 below a piece of wafer split shed 106 is good, thus improving the pattern of the floating gate layer 103 with floating boom tip region 120 of formation, for instance the thickness evenness of the floating gate layer 103 with floating boom tip region 120 is good.
With reference to Figure 12, etching removes described hard mask layer 105 (with reference to Figure 11), exposes described floating gate layer 103; The floating gate layer 103 exposed described in etching, until exposing coupling oxide layer 102, forms floating boom tip 130 in the position at described floating boom tip region 120 (with reference to Figure 11) place.
Before etching described hard mask layer 105, further comprise the steps of: and form the first side wall film covering the floating gate layer 103 below described opening 106 and opening 106; Adopting and etch described first side wall film without mask etching technique, form the first side wall 131 covering described opening sidewalls and floating boom tip region 120 sidewall, described first side wall is also located on part floating gate layer 103; Etching removes the floating gate layer 103 that adjacent first side wall 131 exposes, and exposes floating gate layer 103 sidewall surfaces;Form the second side wall 132 covering floating gate layer 103 sidewall and the first side wall 131 sidewall; Full source line layer 133 is filled between adjacent second side wall 132.
After forming described floating boom tip 130, further comprise the steps of: and form tunneling medium layer 134 on most advanced and sophisticated 130 sidewalls of described floating boom; Forming word line layer 135 in described tunneling medium layer 134, wherein, described word line layer 135 lays respectively at the both sides that described floating boom tip 130 is relative with described source line layer 133.
By Such analysis it can be seen that the floating boom tip 130 formed in the present embodiment has stable pattern, thus improve the yield of the flush memory device of formation.
Another embodiment of the present invention also provides for the manufacture method of a kind of flush memory device, the cross-sectional view forming flush memory device process that Figure 13 to Figure 17 provides for another embodiment of the present invention.
With reference to Figure 13, it is provided that substrate 201, the coupling oxide layer 202 being positioned in substrate 201 and be positioned at the floating gate layer 203 on coupling oxide layer 202.
Description about substrate 201, coupling oxide layer 202 and floating gate layer 203 is referred to describing accordingly of previous embodiment, does not repeat them here.
With continued reference to Figure 13, described floating gate layer 203 forms hard mask layer 205.
In the present embodiment, described hard mask layer 205 is positioned at described floating gate layer 203 top surface.
With reference to Figure 14, graphical described hard mask layer 205 forms the opening 206 running through described hard mask layer 205 thickness.
In the present embodiment, adopt dry etch process, etch described hard mask layer 205 and form described opening 206, and formed at graphical described hard mask layer 205 in the technical process of opening running through described hard mask layer 205, also etching removes the floating gate layer 203 being positioned at the segment thickness below described opening 206, and the etching loss of described floating gate layer 203 is more difficult to be avoided.
In other embodiments, it is also possible to by the etching technics of hard mask layer graphical described in more precise control so that described etching technics stops immediately after exposing floating gate layer top surface.
With reference to Figure 15, the first etching technics etching is adopted to remove the floating gate layer 203 being positioned at the first thickness below described opening 206, wherein, according to the original depth carrying out described first etching technics anteposition floating gate layer 203 below opening 206, determine the etching duration of described first etching technics so that described first etching technics complete after the thickness of floating gate layer 203 be fixed value.
In the present embodiment, before adopting, feedback etching system (FeedForwardSystem) carries out described first etching technics. Described first etching technics is dry etch process, and in one embodiment, the etching gas that described first etching technics adopts is CF4Or CHF3。
In the present embodiment, even if floating gate layer 203 original depth in different lot has diversity before carrying out the first etching technics, determine according to the original depth of floating gate layer 203 before carrying out the first etching technics yet with the etching duration of the first etching technics, after first etching technics is completed, the thickness being positioned at floating gate layer 203 below opening 206 of each lot is identical. Therefore, the etching duration being subsequently formed the second etching technics of floating boom tip region is fixing duration, the thickness still enabling to the floating gate layer after forming floating boom tip region in each lot is fixed value, namely disclosure satisfy that the thickness of the floating gate layer after forming floating boom tip region in each lot is identical.
Wherein, it is arranged in floating gate layer 203 original depth below opening 206 there is diversity to be likely to be caused by one or more of following reason:
The depositing operation being previously formed floating gate layer 203 has unstability, causes the original depth of the floating gate layer 203 below different lot split shed 206 diversity occur;Or, floating gate layer 203 is had certain etching loss and the poor controllability of described etching loss by the technique that aforementioned etching forms opening 206, will also result in the original depth of the floating gate layer 203 below different lot split shed 206 and diversity occurs.
With reference to Figure 16, after carrying out described first etching technics, the second etching technics etching is adopted to remove the floating gate layer 203 of the second thickness, and also etching removes the part floating gate layer 203 being positioned at below hard mask layer 205, in described hard mask layer 205 floating boom tip region 220 formed below, wherein, the etching duration of described second etching technics is fixing duration.
It is most advanced and sophisticated that the follow-up position at described floating boom tip region 220 place forms floating boom. Described second etching technics is isotropic dry etch process.
According to processing performance demand, after the second etching technics completes, being positioned at the thickness of floating gate layer 203 below opening 206 also for fixed value, say, that after the second etching technics completes, the thickness being positioned at floating gate layer 203 below opening 206 in each lot is identical. In other embodiments, after the second etching technics completes, the thickness being positioned at floating gate layer below opening in each wafer is identical.
From Such analysis, owing to being fixed value carrying out the second etching technics and be previously located in the thickness of the floating gate layer 203 below opening 206, therefore when to meet the floating gate layer 203 with floating boom tip 220 being positioned at below opening 206 and be fixed value, it is desirable to the etching duration of described second etching technics is fixed value.
Owing in the present embodiment, the etching duration of the second etching technics is fixed value, the floating boom tip region 220 therefore experiencing the second etching technics formation will have fixing pattern, and described floating boom tip region 220 has fixing height and sharpness. Therefore, for different lot, most advanced and sophisticated 220 patterns of floating boom in each lot are all identical, namely, height and the sharpness diversity of the floating boom tip region 220 in each lot are little, the stable appearance making the floating boom tip region 220 of formation is good, and the height of the floating boom tip region 220 formed and sharpness are satisfied by process requirements. In another embodiment, for different wafer, the floating boom tip region pattern in each wafer is all identical, namely, height and the sharpness diversity of the floating boom tip region in each wafer are little so that the stable appearance of the floating boom tip region of formation is good and meets process requirements.
With reference to Figure 17, etching removes described hard mask layer 205 (with reference to Figure 16), exposes described floating gate layer 203; The floating gate layer 203 exposed described in etching, until exposing coupling oxide layer 202, forms floating boom tip 230 in the position at described floating boom tip region 220 (with reference to Figure 16) place.
Before etching described hard mask layer 205, further comprise the steps of: and form the first side wall film covering the floating gate layer 203 below described opening 206 and opening 206; Adopting and etch described first side wall film without mask etching technique, form the first side wall 231 covering described opening sidewalls and floating boom tip region 220 sidewall, described first side wall is also located on part floating gate layer 203; Etching removes the floating gate layer 203 that adjacent first side wall 231 exposes, and exposes floating gate layer 203 sidewall surfaces; Form the second side wall 232 covering floating gate layer 203 sidewall and the first side wall 231 sidewall; Full source line layer 233 is filled between adjacent second side wall 232.
After forming described floating boom tip 230, further comprise the steps of: and form tunneling medium layer 234 on most advanced and sophisticated 230 sidewalls of described floating boom;Forming word line layer 235 in described tunneling medium layer 234, wherein, described word line layer 235 lays respectively at the both sides that described floating boom tip 230 is relative with described source line layer 233.
By Such analysis it can be seen that the floating boom tip 230 formed in the present embodiment has stable pattern, thus improve the yield of the flush memory device of formation.
Although present disclosure is as above, but the present invention is not limited to this. Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. the manufacture method of a flush memory device, it is characterised in that including:
Substrate is provided, is positioned at suprabasil coupling oxide layer and is positioned at the floating gate layer on described coupling oxide layer;
Described floating gate layer is formed hard mask layer;
Graphical described hard mask layer forms the opening running through described hard mask layer thickness;
The first etching technics etching is adopted to remove the floating gate layer being positioned at the first thickness below described opening, wherein, according to the original depth carrying out described first etching technics anteposition floating gate layer below opening, determine the etching duration of described first etching technics so that the first etching technics is positioned at the thickness of the floating gate layer below described opening after completing be fixed value;
After carrying out described first etching technics, the second etching technics etching is adopted to remove the floating gate layer of the second thickness, and also etching removes the part floating gate layer being positioned at below hard mask layer, floating boom tip region is formed in described floating gate layer, wherein, the etching duration of described second etching technics is fixing duration;
Etching removes described hard mask layer, exposes described floating gate layer;
The floating gate layer exposed described in etching, until exposing coupling oxide layer, forms floating boom in the position at described floating boom tip region place most advanced and sophisticated.
2. the manufacture method of flush memory device as claimed in claim 1, it is characterised in that before adopting, feedback etching system carries out described first etching technics; Before carrying out described first etching technics, measure the original depth being positioned at the floating gate layer below described opening.
3. the manufacture method of flush memory device as claimed in claim 1, it is characterised in that described second etching technics is isotropic dry etch process.
4. the manufacture method of flush memory device as claimed in claim 1, it is characterized in that, before forming described hard mask layer, described floating gate layer is formed barrier layer, and described barrier layer is between described floating gate layer and described hard mask layer, the material on described barrier layer is different from the material of described hard mask layer, and the material on described barrier layer is different from the material of floating gate layer; Described open bottom exposes described barrier layer surface.
5. the manufacture method of flush memory device as claimed in claim 4, it is characterised in that before carrying out described first etching technics, further comprise the steps of: and remove the barrier layer that described open bottom is exposed, until exposing floating gate layer surface.
6. the manufacture method of flush memory device as claimed in claim 4, it is characterised in that the material on described barrier layer is silicon oxide; The material of described hard mask layer is silicon nitride.
7. the manufacture method of flush memory device as claimed in claim 6, it is characterised in that adopting wet-etching technology etching to remove the barrier layer that described open bottom is exposed, wherein, the etch liquids that wet-etching technology adopts is hydrofluoric acid solution.
8. the manufacture method of flush memory device as claimed in claim 1, it is characterised in that being formed at graphical described hard mask layer in the technical process of opening running through described hard mask layer, also etching removes the floating gate layer being positioned at the segment thickness below described opening.
9. the manufacture method of flush memory device as claimed in claim 1, it is characterised in that described manufacture method carries out in units of lot; After carrying out described first etching technics, the thickness being positioned at the floating gate layer below opening in each lot is fixed value.
10. the manufacture method of flush memory device as claimed in claim 1, it is characterised in that after described second etching technics, etch described hard mask layer before, further comprise the steps of: and form the first side wall film covering the floating gate layer below described opening and opening; Adopting and etch described first side wall film without mask etching technique, form the first side wall covering described opening sidewalls and floating boom tip region sidewall, described first side wall is also located on part floating gate layer; Etching removes the floating gate layer that adjacent first side wall exposes, and exposes floating gate layer sidewall surfaces; Form the second side wall covering floating gate layer sidewall and the first side wall sidewall; Full source line layer is filled between adjacent second side wall.
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