CN106229316B - A kind of technique manufacturing method for obtaining Split-gate flash memory and stablizing floating gate tip - Google Patents
A kind of technique manufacturing method for obtaining Split-gate flash memory and stablizing floating gate tip Download PDFInfo
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- CN106229316B CN106229316B CN201610890802.3A CN201610890802A CN106229316B CN 106229316 B CN106229316 B CN 106229316B CN 201610890802 A CN201610890802 A CN 201610890802A CN 106229316 B CN106229316 B CN 106229316B
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- 238000007667 floating Methods 0.000 title claims abstract description 129
- 238000000034 method Methods 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 35
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 66
- 229920005591 polysilicon Polymers 0.000 claims abstract description 64
- 238000005530 etching Methods 0.000 claims abstract description 38
- 230000008569 process Effects 0.000 claims abstract description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000008878 coupling Effects 0.000 claims abstract description 5
- 238000010168 coupling process Methods 0.000 claims abstract description 5
- 238000005859 coupling reaction Methods 0.000 claims abstract description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 4
- 230000008901 benefit Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000012360 testing method Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000026267 regulation of growth Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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Abstract
A kind of technique manufacturing method for obtaining Split-gate flash memory and stablizing floating gate tip, comprising: coupling oxide layer and floating gate polysilicon layer is formed on the substrate, forms floating gate silicon nitride layer on floating gate polysilicon layer, arranges exposure mask, forms mask pattern；Floating gate silicon nitride layer is performed etching using exposure mask while guaranteeing that floating gate polysilicon has loss amount to prevent the floating gate silicon nitride residue of open area, based on the later floating gate polysilicon residual thickness of floating gate silicon nitride etch using feedback system and isotropic etching is so that the floating gate polysilicon residual thickness after isotropic etching is identical, the floating gate polysilicon with different radians is ultimately formed；The first side wall, the second side wall, source polysilicon lines are formed on the floating gate polysilicon layer of floating gate silicon nitride open area；It is formed by radian size according to floating gate polysilicon layer isotropic etching, different wet processes is executed to the first side wall and is laterally etched back to the time.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of acquisition Split-gate flash memory
Stablize the technique manufacturing method at floating gate tip.
Background technique
The advantages that flash memory is convenient with its, and storage density is high, good reliability is as the hot spot studied in non-volatility memorizer.
Since first flash memory products appearance of the 1980s, with the development of technology with each electronic product to storage
Demand, flash memory are widely used in mobile phone, notebook, palm PC and USB flash disk etc. be mobile and communication apparatus in.
Flash memory is a kind of nonvolatile memory, and operation principles are by changing the critical of transistor or memory cell
Voltage controls the switch in gate pole channel to achieve the purpose that storing data, makes the data stored in memory will not be because of power supply
It interrupts and disappears, and flash memory is a kind of special construction of electrically erasable and programmable read-only memory.Nowadays flash memory has accounted for
According to most of market share of non-volatile semiconductor memory, become non-volatile semiconductor memory with fastest developing speed.
In general, flash memory is the combination of grid dividing structure or stacked gate structure or two kinds of structures.Gate-division type flash memory is due to its spy
Different structure all embodies its unique performance advantage, therefore sub-gate knot compared to gatestack flash memory when programmed and erased
Structure is due to having many advantages, such as high programming efficiency, and the structure of wordline can be to avoid " cross and wipe ", and application is especially extensive.
In the prior art, in the technical process of manufacture Split-gate flash memory, following manufacture treatment processes can be undergone:
Coupling oxide layer 20 and floating gate polysilicon layer 30 are sequentially formed on substrate 10 (general, substrate 10 is silicon substrate), and in institute
Formation floating gate silicon nitride layer 40 on floating gate polysilicon layer 30 is stated, then arranges exposure mask, and form the pattern 50 of the exposure mask；With
The floating gate silicon nitride layer is performed etching using the exposure mask for forming pattern afterwards while guaranteeing that floating gate polysilicon has centainly
Loss amount to prevent the floating gate silicon nitride residue of open area, 51 are shown as open area and floating gate polysilicon has in Fig. 2
Certain loss amount.
It is then based on the later floating gate polysilicon residual thickness of floating gate silicon nitride etch and utilizes feedback system and isotropism
To form the floating gate polysilicon with different radians in floating gate polysilicon, radian size depends on isotropic etching for etching
Time；Then the first side wall, the second side wall, source polysilicon are formed on the floating gate polysilicon layer of floating gate silicon nitride open area
Line；Then, identical wet process is executed to the first side wall and is laterally etched back to the time；Finally using the first side wall as exposure mask, pass through dry method
Floating gate polysilicon is etched, to form final floating gate tip；
Finally being formed in floating gate polysilicon in the prior art using feedback system and isotropic etching has different arcs
The floating gate polysilicon of degree, however, being laterally etched back to the time in the identical wet process of the first side wall execution and being to cover with the first side wall
Film, by dry etching floating gate polysilicon, the floating gate tip of formation can due to initial floating gate radian difference and occur different
Floating gate tip；For example, if initial floating gate radian is excessive, but wet process is laterally etched back to that the time is too short, and final floating gate tip is just
Can be more higher sharper, it is easy to appear programming failure, if initial floating gate radian is too small, but wet process is laterally etched back to overlong time, most
The lower whole floating gate tip will be the more blunt, is easy to appear erasing failure.
Accordingly, it is desirable to be able to provide a kind of technique manufacturer that can be obtained Split-gate flash memory and stablize floating gate tip
Method.
Summary of the invention
The technical problem to be solved by the present invention is to for drawbacks described above exists in the prior art, providing one kind can be obtained
Split-gate flash memory stablizes the technique manufacturing method at floating gate tip.
In order to achieve the above technical purposes, according to the present invention, a kind of stable floating gate of acquisition Split-gate flash memory is provided
The technique manufacturing method at tip, comprising: first step: sequentially forming coupling oxide layer and floating gate polysilicon layer on substrate, and
And floating gate silicon nitride layer is formed on the floating gate polysilicon layer, then arrange exposure mask, and form the pattern of the exposure mask；The
Two steps: the floating gate silicon nitride layer is performed etching followed by the exposure mask for forming pattern while guaranteeing floating gate polysilicon
The floating gate silicon nitride residue that open area is prevented with certain loss amount is then based on later floating of floating gate silicon nitride etch
Gate polysilicon residual thickness is finally formed in floating gate polysilicon using feedback system and isotropic etching has different radians
Floating gate polysilicon, radian size depend on isotropic etching period；Third step: life is formed on floating gate polysilicon layer
Long first side wall, the second side wall, source polysilicon lines；Four steps: according to the floating gate polysilicon layer isotropic etching institute
The radian size of formation executes different wet processes to the first side wall and is laterally etched back to the time；5th step: being to cover with the first side wall
Film, by dry etching floating gate polysilicon, to form final floating gate tip；6th step: formed tunnel oxide, wordline with
And wordline side wall.
Preferably, in the technique manufacturing method that above-mentioned acquisition Split-gate flash memory stablizes floating gate tip, in the shape
At radian it is of different sizes in the case where, need to be implemented the different lateral wet process etch-back time；
Preferably, in the technique manufacturing method that above-mentioned acquisition Split-gate flash memory stablizes floating gate tip, the formation
Radian it is bigger, it is longer to need to be implemented the process time that lateral wet process is etched back to.
Preferably, in the technique manufacturing method that above-mentioned acquisition Split-gate flash memory stablizes floating gate tip, the formation
Radian it is smaller, it is shorter to need to be implemented the process time that lateral wet process is etched back to.
Preferably, in the technique manufacturing method that above-mentioned acquisition Split-gate flash memory stablizes floating gate tip, in second step
In rapid, the etching period of isotropic etching is longer, and the radian of floating gate polysilicon is bigger.
Preferably, in the technique manufacturing method that above-mentioned acquisition Split-gate flash memory stablizes floating gate tip, in second step
In rapid, the etching period of isotropic etching is shorter, and the radian of floating gate polysilicon is smaller.
Preferably, in the technique manufacturing method that above-mentioned acquisition Split-gate flash memory stablizes floating gate tip, the substrate
It is silicon substrate.
In the present invention, it is formed by radian size according to the floating gate polysilicon layer isotropic etching, to first
Side wall executes different wet processes and is laterally etched back to the time；Make it possible to obtain Split-gate flash memory and stablizes floating gate tip.Moreover,
The present inventor tests method of the invention, and experimental result shows that method of the invention can obtain grid-division flash
Memory stablizes floating gate tip, to the erasing of the flash memory avoided or become to fail.
Detailed description of the invention
In conjunction with attached drawing, and by reference to following detailed description, it will more easily have more complete understanding to the present invention
And its adjoint advantage and feature is more easily to understand, in which:
Fig. 1 schematically shows a step in the technical process of manufacture Split-gate flash memory.
Fig. 2 schematically shows another steps in the technical process of manufacture Split-gate flash memory.
Fig. 3 schematically shows the big radian wheel of grid polycrystalline silicon bottom corners generated when manufacture Split-gate flash memory
It is wide.
Fig. 4 schematically shows the small radian wheels of grid polycrystalline silicon bottom corners generated when manufacture Split-gate flash memory
It is wide.
Fig. 5 schematically shows floating gate tip profile.
Fig. 6 schematically shows a kind of acquisition Split-gate flash memory according to the preferred embodiment of the invention and stablizes floating gate
The flow chart of the technique manufacturing method at tip.
It should be noted that attached drawing is not intended to limit the present invention for illustrating the present invention.Note that indicating that the attached drawing of structure can
It can be not necessarily drawn to scale.Also, in attached drawing, same or similar element indicates same or similar label.
Specific embodiment
In order to keep the contents of the present invention more clear and understandable, combined with specific embodiments below with attached drawing in of the invention
Appearance is described in detail.
Fig. 6 schematically shows a kind of acquisition Split-gate flash memory according to the preferred embodiment of the invention and stablizes floating gate
The flow chart of the technique manufacturing method at tip.
Specifically, as shown in fig. 6, a kind of acquisition Split-gate flash memory according to the preferred embodiment of the invention stablizes floating gate
The technique manufacturing method at tip includes:
First step S1: coupling oxide layer 20 and floating gate polysilicon layer 30 are sequentially formed on substrate 10, and described
Floating gate silicon nitride layer 40 is formed on floating gate polysilicon layer 30, then arranges exposure mask, and form the pattern of required exposure mask 50, such as
Shown in Fig. 1；
Generally, substrate 10 is silicon substrate.
Second step S2: the floating gate silicon nitride layer is performed etching while is protected followed by the exposure mask for forming pattern
Card floating gate polysilicon has certain loss amount 51 to prevent the floating gate silicon nitride residue of open area, is then based on floating gate nitridation
Silicon etches later floating gate polysilicon residual thickness using feedback system and isotropic etching in floating gate polysilicon to form
Floating gate polysilicon with different radians, radian size depend on isotropic etching period.In second step, isotropism
The etching period of etching is longer, and the radian of floating gate polysilicon is bigger.In the second step, the etching period of isotropic etching is got over
Short, the radian of floating gate polysilicon is smaller.
As a result, in second step S2, the residual thickness of floating gate polysilicon is different after floating gate silicon nitride etch, and floating gate is more
The isotropic etching of crystal silicon needs to select the different time identical with the residual thickness after keeping isotropic to etch, therefore,
The radian of floating gate polysilicon is different after isotropic etches.
Third step S3: one side wall of growth regulation, the second side wall, source polysilicon lines are formed on floating gate polysilicon layer；
Four steps S4: it is formed by radian size according to the floating gate polysilicon layer isotropic etching, to first
Side wall executes different wet processes and is laterally etched back to the time；
5th step S5: using the first side wall as exposure mask, by dry etching floating gate polysilicon, to form final floating gate point
End；
6th step S6: tunnel oxide, wordline and wordline side wall are formed.
In the fourth step s 4, in four steps, the radian of the formation is bigger (as indicated at 61), needs
It is longer to execute the process time that lateral wet process is etched back to.In the fourth step s 4, smaller (such as attached drawing mark of the radian of the formation
Shown in note 62), it is shorter to need to be implemented the process time that lateral wet process is etched back to.
In the present invention, it is formed by radian size according to the floating gate polysilicon layer isotropic etching, to first
Side wall executes different wet processes and is laterally etched back to the time；Make it possible to obtain Split-gate flash memory and stablizes floating gate tip.Moreover,
The present inventor tests method of the invention, and experimental result shows that method of the invention can obtain grid-division flash
Memory stablizes floating gate tip, to the erasing of the flash memory avoided or become to fail.
It should be noted that between first step S1 and second step S2 and in second step S2 and third step S3
Between and between third step S3 and four steps S4 etc., the other marks of Split-gate flash memory manufacturing process can be executed
Quasi- processing step is omitted herein herein due to other unrelated with key point of the invention.
Preferably, the technique manufacturing method for obtaining the stable floating gate tip of Split-gate flash memory is advantageously used for making
Make Split-gate flash memory.
In addition, it should be noted that, unless stated otherwise or point out, the otherwise term " first " in specification, "
Two ", the descriptions such as " third " are used only for distinguishing various components, element, the step etc. in specification, each without being intended to indicate that
Component, element, the logical relation between step or ordinal relation etc..
It is understood that although the present invention has been disclosed in the preferred embodiments as above, above-described embodiment not to
Limit the present invention.For any person skilled in the art, without departing from the scope of the technical proposal of the invention,
Many possible changes and modifications all are made to technical solution of the present invention using the technology contents of the disclosure above, or are revised as
With the equivalent embodiment of variation.Therefore, anything that does not depart from the technical scheme of the invention are right according to the technical essence of the invention
Any simple modifications, equivalents, and modifications made for any of the above embodiments still fall within the range of technical solution of the present invention protection
It is interior.
And it should also be understood that the present invention is not limited thereto and locate the specific method described, compound, material, system
Technology, usage and application are made, they can change.It should also be understood that term described herein be used merely to describe it is specific
Embodiment, rather than be used to limit the scope of the invention.Must be noted that herein and appended claims used in
Singular "one", "an" and "the" include complex reference, unless context explicitly indicates that contrary.Therefore, example
Such as, the citation to one or more elements is meaned to the citation of " element ", and including known to those skilled in the art
Its equivalent.Similarly, as another example, the citation of " step " or " device " is meaned to one or
The citation of multiple steps or device, and may include secondary step and second unit.It should be managed with broadest meaning
All conjunctions that solution uses.Therefore, word "or" should be understood that the definition with logical "or", rather than logical exclusive-OR
Definition, unless context explicitly indicates that contrary.Structure described herein will be understood as the function of also quoting from the structure
Equivalent.It can be interpreted that approximate language should be understood like that, unless context explicitly indicates that contrary.
Claims (9)
1. a kind of technique manufacturing method for obtaining Split-gate flash memory and stablizing floating gate tip, characterized by comprising:
First step: coupling oxide layer and floating gate polysilicon layer are sequentially formed on substrate, and in the floating gate polysilicon layer
Then upper formation floating gate silicon nitride layer arranges exposure mask, and forms the pattern of the exposure mask；
Second step: the floating gate silicon nitride layer is performed etching followed by the exposure mask for forming pattern while guaranteeing floating gate
Polysilicon has certain loss amount to prevent the floating gate silicon nitride residue of open area, be then based on floating gate silicon nitride etch with
Floating gate polysilicon residual thickness afterwards makes the floating gate polysilicon after isotropic etching using feedback system and isotropic etching
Residual thickness is identical, the floating gate polysilicon with different radians is ultimately formed, when radian size depends on isotropic etching
Between；The residual thickness of floating gate polysilicon is different after floating gate silicon nitride etch in this step, the isotropic of floating gate polysilicon
It is identical with the residual thickness after keeping isotropic to etch that etching needs to select the different time, therefore, isotropic etching with
The radian of floating gate polysilicon is different afterwards；
Third step: the first side wall, the second side wall, source polycrystalline are formed on the floating gate polysilicon layer of floating gate silicon nitride open area
Silicon line；
Four steps: it is formed by radian size according to the floating gate polysilicon layer isotropic etching, the first side wall is held
The different wet process of row is laterally etched back to the time；
5th step: using the first side wall as exposure mask, by dry etching floating gate polysilicon, to form final floating gate tip.
2. the technique manufacturing method according to claim 1 for obtaining Split-gate flash memory and stablizing floating gate tip, feature
It is to further include the 6th step: forms tunnel oxide, wordline and wordline side wall.
3. the technique manufacturing method according to claim 1 for obtaining Split-gate flash memory and stablizing floating gate tip, feature
It is, in four steps, in the case where the radian of the formation is of different sizes, needs to execute the first side wall different cross
To the wet process etch-back time.
4. the technique manufacturing method according to claim 1 or 2 for obtaining Split-gate flash memory and stablizing floating gate tip, special
Sign is, in four steps, the radian of the formation is bigger, needs to be implemented the process time that lateral wet process is etched back to and gets over
It is long.
5. the technique manufacturing method according to claim 1 or 2 for obtaining Split-gate flash memory and stablizing floating gate tip, special
Sign is that the radian of the formation is smaller, and it is shorter to need to be implemented the process time that lateral wet process is etched back to.
6. the technique manufacturing method according to claim 1 or 2 for obtaining Split-gate flash memory and stablizing floating gate tip, special
Sign is that in the second step, the etching period of isotropic etching is longer, and the radian of floating gate polysilicon is bigger.
7. the technique manufacturing method according to claim 1 or 2 for obtaining Split-gate flash memory and stablizing floating gate tip, special
Sign is that in the second step, the etching period of isotropic etching is shorter, and the radian of floating gate polysilicon is smaller.
8. the technique manufacturing method according to claim 1 or 2 for obtaining Split-gate flash memory and stablizing floating gate tip, special
Sign is that the Split-gate flash memory that obtains stablizes the technique manufacturing method at floating gate tip for manufacturing grid-division flash storage
Device.
9. the technique manufacturing method according to claim 1 or 2 for obtaining Split-gate flash memory and stablizing floating gate tip, special
Sign is that the substrate is silicon substrate.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538367A (en) * | 2014-12-30 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Mirror image split gate flash memory and forming method thereof |
| CN105679713A (en) * | 2016-04-26 | 2016-06-15 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memories |
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| KR100771418B1 (en) * | 2006-03-31 | 2007-10-30 | 주식회사 엑셀반도체 | Self Align type Flash Memory Device and Method of Forming the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104538367A (en) * | 2014-12-30 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Mirror image split gate flash memory and forming method thereof |
| CN105679713A (en) * | 2016-04-26 | 2016-06-15 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing flash memories |
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