CN104934430B - NOR flash memory and manufacturing method thereof - Google Patents
NOR flash memory and manufacturing method thereof Download PDFInfo
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- CN104934430B CN104934430B CN201410150290.8A CN201410150290A CN104934430B CN 104934430 B CN104934430 B CN 104934430B CN 201410150290 A CN201410150290 A CN 201410150290A CN 104934430 B CN104934430 B CN 104934430B
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
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Abstract
The invention discloses a NOR type flash memory and a manufacturing method thereof, which comprises a memory cell arranged on a substrate. A memory cell, comprising: stacked gate structure, auxiliary gate dielectric layer, lightly doped region, and drain region. The stacked gate structure is disposed on the substrate. The auxiliary gate is disposed on the substrate at the first side of the stacked gate structure. The auxiliary gate dielectric layer is disposed between the auxiliary gate and the substrate. The lightly doped region is disposed in the substrate under the auxiliary gate, wherein an inversion layer is formed in the substrate under the auxiliary gate as a source region by applying a voltage to the auxiliary gate. And the drain region is arranged in the substrate at the second side of the stacked gate structure, and the first side is opposite to the second side.
Description
Technical field
The present invention relates to a kind of semiconductor elements, and more particularly to a kind of NOR type flash memories and its manufacturing method.
Background technique
Flash memory cells movement, and the number being stored in such as can repeatedly carry out the deposit of data, read, erase due to having
The advantages of according to that will not disappear after a loss of power, so it is non-volatile to have become one kind that PC and electronic equipment are widely used
Property memory component.
Typical flash memory cells are with polysilicon production floating grid (Floating Gate) adulterated and control gate
Pole (Control Gate).Moreover, floating grid and control grid between be separated by with dielectric layer, and between floating grid and substrate with
Tunnel oxidation layer (Tunnel Oxide) is separated by.As the behaviour that flash memories be written/erase with (Write/Erase) data
When making, by being biased in control grid with source/drain regions, so as to electron injection floating grid or make electronics from floating grid
Pole pulls out.And when reading the data in flash memories, apply an operating voltage on the control gate, at this time floating grid
Electriferous state will affect the ON/OFF of its lower channel (Channel), and the ON/OFF in this channel is interpretation data value " 0 " or " 1 "
Foundation.
Just developed when with integrated circuit with the element of higher integrated level towards miniaturization, the size of storage unit can lead to
The grid length mode of reduction storage unit is crossed to reach.But grid length becomes smaller and can shorten below tunnel oxidation layer
Passage length (Channel Length) is easy between drain region and source area when operating such flash memories
Abnormal electrically perforation (Punch Through) occurs,
It so will seriously affect the electrical performance of this storage unit, and lead to the erroneous judgement of data.
Industry proposes a kind of separated grid (Split Gate) flash memories at present.Separated grid (Split Gate) dodges
It is sequentially dielectric layer between tunnel dielectric, floating grid, grid (Inter-gate Dielectric) memory is deposited by substrate
With selection gate, wherein selection gate is in addition to position on the floating gate side, and still some is extended to above substrate, and and base
It is separated by between bottom with selection gate dielectric layer.Source area is located in the substrate of floating grid side, and drain region, which is then located at, extends to base
In the substrate of the selection gate side at bottom.So when operating such flash memories, even if floating grid down channel is selecting
When selecting that grid is undressed to be made persistently to open under voltage status, the channel below selection gate remains to remain off, so that
Drain region can not be connected with source area, and can prevent the erroneous judgement of data.
However, there is biggish memory cell size since separated grid structure needs biggish separated grid region,
Therefore its memory cell size is big compared with the memory cell size of stack grid structure, and generates the so-called element that can not increase and integrate
The problem of spending.
Summary of the invention
The present invention provides a kind of NOR type flash memories, and the integrated level of memory component can be improved, reduce to programme and do
It disturbs, and improves the service speed of memory component.
The present invention provides a kind of manufacturing method of NOR type flash memories, is not required to be additionally formed selection gate, can be not
In the case where the size for increasing storage unit, make storage unit that there is good electrical performance, and can be with existing manufacture craft
It combines.
A kind of NOR type flash memories of the invention, comprising: the first storage unit.First storage unit is arranged in substrate
On.First storage unit, comprising: stacked gate architectures, auxiliary grid, auxiliary grid dielectric layer, light doped region, drain region.Heap
Gatestack pole structure setting is in substrate.Auxiliary grid is arranged in the substrate of the first side of stacked gate architectures.Auxiliary grid is situated between
Electric layer is arranged between auxiliary grid and substrate.Light doped region is arranged in the substrate below auxiliary grid, wherein by auxiliary
It helps grid to apply a voltage and forms inversion layer in the substrate below auxiliary grid using as source area.Drain region, setting exist
In the substrate of second side of stacked gate architectures, the first side is opposite with second side.
In one embodiment of this invention, NOR type flash memories further include the second storage unit, single with the first storage
Member is in mirror configuration, shares auxiliary grid or drain region.
In one embodiment of this invention, above-mentioned stacked gate architectures include at least: floating grid, tunnel dielectric, control
Dielectric layer between grid processed, grid.Floating grid is arranged in substrate.Tunnel dielectric is arranged between floating grid and substrate.Control
Grid setting processed is on the floating gate.Dielectric layer setting is between control grid and floating grid between grid.
In one embodiment of this invention, NOR type flash memories further include clearance wall, and stacked gate architectures are arranged in
Side wall.
In one embodiment of this invention, the material of above-mentioned floating grid includes DOPOS doped polycrystalline silicon.
In one embodiment of this invention, the material of above-mentioned tunnel dielectric includes silica.
In one embodiment of this invention, the material of dielectric layer includes silicon oxide/silicon nitride/silicon oxide between above-mentioned grid.
The manufacturing method of a kind of NOR type flash memories of the invention, including the following steps: firstly, being formed in the substrate
Component isolation structure, and at least two stacked gate architectures are formed on the substrate.The shape in the substrate on the outside of two stacked gate architectures
At drain region.Remove the component isolation structure between two stacked gate architectures.Shape in substrate between two stacked gate architectures
At light doped region.Auxiliary grid dielectric layer is formed in substrate between two stacked gate architectures.Two stacked gate architectures it
Between substrate on form auxiliary grid.
In one embodiment of this invention, the step of drain region is formed in the substrate in the above-mentioned outside in two stacked gate architectures
It suddenly include: that the first mask layer is formed on the substrate, to cover the substrate between two stacked gate architectures；With the first mask layer and two
Stacked gate architectures are mask, are doped injection and form drain region；And remove the first mask layer.
In one embodiment of this invention, the manufacturing method of above-mentioned NOR type flash memories further includes in two piled grids
The side wall of structure forms clearance wall.
In one embodiment of this invention, the step of drain region is formed in the above-mentioned substrate on the outside of two stacked gate architectures
It include: to form the first mask layer on this substrate, to cover the substrate between two stacked gate architectures；With the first mask layer and two
Stacked gate architectures are mask, are doped injection and form light doped drain region；Remove the first mask layer；In two piled grids
The side wall of structure forms clearance wall；The second mask layer is formed on the substrate, to cover the substrate between two stacked gate architectures；With
Second mask layer and two stacked gate architectures with clearance wall are mask, are doped injection and form doped region；And it moves
Except the second mask layer.
In one embodiment of this invention, above-mentioned the step of at least two stacked gate architectures are formed on the substrate include:
The first dielectric layer is formed in substrate；The first conductor layer is formed on the first dielectric layer；Pattern the first conductor layer；Patterned
The first conductor layer on form the second dielectric layer；The second conductor layer is formed on the second dielectric layer；Pattern the second conductor layer with
Form control grid；And the second dielectric layer of patterning, patterned first conductor layer, the first dielectric layer are situated between with being formed between grid
Electric layer, floating grid and tunnel dielectric.
In one embodiment of this invention, auxiliary grid dielectric is formed in the above-mentioned substrate between two stacked gate architectures
The method of layer includes thermal oxidation method, chemical vapour deposition technique or atomic layer deposition method.
In one embodiment of this invention, the step of auxiliary grid is formed in the above-mentioned substrate between two stacked gate architectures
It suddenly include: that third conductor layer is formed on the substrate；And part third conductor layer is removed to form auxiliary grid.
In one embodiment of this invention, above-mentioned removal part third conductor layer includes back in the method for forming auxiliary grid
Etching method.
In NOR type flash memories of the invention and its manufacturing method, in no applied voltage before auxiliary grid, auxiliary
Source area is not formed in substrate below grid, therefore the electric leakage from source area to drain region can be generated to avoid storage unit
Stream.And when operating storage unit, applies a voltage in auxiliary grid and form reversion in the substrate below auxiliary grid
Layer is using as source area.Since NOR type flash memories of the invention do not need the volume as existing separated grid memory
Outer setting selection gate, therefore can make storage unit that there is good electricity in the case where not increasing the size of storage unit
Sex expression.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is attached appended by cooperation
Figure is described in detail below.
Detailed description of the invention
Figure 1A is the top view of the NOR type flash memories of one embodiment of the invention；
Figure 1B is the sectional view of the NOR type flash memories in Figure 1A of one embodiment of the invention, and wherein region A is edge
The section of A-A ' line, region B are the section along B-B ' line；
Fig. 2A is the programming operation mode schematic diagram of the NOR type flash memories of one embodiment of the invention；
Fig. 2 B is the read mode schematic diagram of the NOR type flash memories of one embodiment of the invention；
Fig. 2 C is the operation mode schematic diagram of erasing of the NOR type flash memories of one embodiment of the invention；
Fig. 3 A to Fig. 3 F is the manufacturing process sectional view of the NOR type flash memories of one embodiment of the invention.
Symbol description
100,300: substrate
102: active region
104,302: component isolation structure
106: stacked gate architectures
108,304a: tunnel dielectric
110,306a, FG: floating grid
112,308a: dielectric layer between grid
114,310a, CG: control grid
116,330, AG: auxiliary grid
118,328: auxiliary grid dielectric layer
120,326: light doped region
122,324, D: drain region
122a, 316: light doped drain region
122b, 322: doped region
124, S: source area
126,318: clearance wall
304,308: dielectric layer
306,310: conductor layer
314,320: mask layer
312: stacked gate architectures
A, B: region
MC1, MC2: storage unit
Specific embodiment
The top view of the depicted NOR type flash memories for one embodiment of the invention of Figure 1A.Figure 1B is depicted for this
The sectional view of NOR type flash memories in Figure 1A of one embodiment of invention, wherein region A is the section along A-A ' line, area
Domain B is the section along B-B ' line.
Firstly, Figure 1A to Figure 1B is please referred to, to illustrate NOR type flash memories of the invention.NOR type flash memory of the present invention is deposited
Reservoir include substrate 100, active region 102, component isolation structure 104, stacked gate architectures 106 (include: tunnel dielectric 108,
Between floating grid 110, grid dielectric layer 112 and control grid 114), auxiliary grid 116, auxiliary grid dielectric layer 118, light doping
Area 120 and drain region 122.
Substrate 100 is, for example, silicon base.It is provided with component isolation structure 104 in this substrate 100, to define active region
102.Component isolation structure 104 is, for example, arranged in parallel in the X direction.Component isolation structure 104 is, for example, shallow trench isolation knot
Structure.The material of component isolation structure 104 is, for example, silica.
Stacked gate architectures 106 are arranged in substrate 100.Stacked gate architectures 106 include tunnel dielectric 108, floating
Dielectric layer 112 and control grid 114 between grid 110, grid.Floating grid 110 is arranged in substrate 100, the material of floating grid 110
Matter is, for example, DOPOS doped polycrystalline silicon.Tunnel dielectric 108 is arranged between floating grid 110 and substrate 100, tunnel dielectric 108
Material be, for example, silica.It controls grid 114 to be arranged on floating grid 110, the material of control grid 114 is, for example, to adulterate
Polysilicon.The setting of dielectric layer 112 is between control grid 114 and floating grid 110 between grid.The material example of dielectric layer 112 between grid
Silica/silicon nitride in this way or silicon oxide/silicon nitride/silicon oxide.In one embodiment, the side wall of stacked gate architectures 106
It can have clearance wall 126.The material of clearance wall 126 is, for example, silicon nitride.
Auxiliary grid 116 is arranged in the substrate 100 of the side of stacked gate architectures 106.The material example of auxiliary grid 116
DOPOS doped polycrystalline silicon in this way.Auxiliary grid dielectric layer 118 is arranged between auxiliary grid 116 and substrate 100, auxiliary grid dielectric layer
118 material is, for example, silica.Light doped region 120 is arranged in the substrate 100 below auxiliary grid 116, wherein by
Auxiliary grid 116 applies a voltage and forms inversion layer in substrate 100 below auxiliary grid 116 using as source area 124.
As illustrated in figures 1A and ib, auxiliary grid 116 and light doped region 120 are, for example, arranged in parallel in the Y direction, and in the Y direction
It is upper extension and it is in a strip shape.Moreover, not having component isolation structure 104, therefore auxiliary in substrate 100 below auxiliary grid 116
Helping grid 116 that can insert will be formed by groove after the removal of component isolation structure 104.
Drain region 122 is arranged in the substrate 100 of 106 other side of stacked gate architectures.That is drain region 122 and auxiliary grid
116 are arranged in the opposite two sides of stacked gate architectures 106.Drain region 122 is, for example, by light doped drain region 122a and doping
Area 122b is constituted.
Stacked gate architectures 106 (include: dielectric layer 112 and control gate between tunnel dielectric 108, floating grid 110, grid
Pole 114), auxiliary grid 116, auxiliary grid dielectric layer 118, light doped region 120 and drain region 122 constitute storage unit.
As illustrated in figures 1A and ib, multiple storage units are formed in substrate 100, these storage units are, for example, to arrange
At an array.Two adjacent storage units MC1, MC2 e.g. have identical and symmetrical structure (in mirror configuration), and altogether
With auxiliary grid 116 (light doped region 120) or drain region 122.
In NOR type flash memories of the invention, in no applied voltage before auxiliary grid 116, auxiliary grid 116
Source area is not formed in the substrate 100 of lower section, therefore the electric leakage from source area to drain region can be generated to avoid storage unit
Stream.And when operating storage unit, by auxiliary grid 116 apply one voltage and substrate below auxiliary grid 116
Inversion layer is formed in 100 using as source area 122.Since NOR type flash memories of the invention are not needed such as existing separation
Selection gate is generally additionally arranged in Gate Memory, therefore can make to store in the case where not increasing the size of storage unit
Unit has good electrical performance.
Then, A, Fig. 2 B and Fig. 2 C referring to figure 2., the operation mould of the flash memories of the preferred embodiment of the present invention is illustrated
Formula comprising programming (Program, Fig. 2A) reads (read, Fig. 2 B) and operation modes such as (Erase, Fig. 2 B) of erasing.
When being programmed sequence to storage unit, apply voltage Vp1 in control grid CG, Vp1 is, for example, 10 volts
Voltage；Apply voltage Vp2 in auxiliary grid AG, voltage Vp2 is enough to form inversion layer in the substrate below auxiliary grid AG
Using as source area S, wherein voltage Vp2 is, for example, the voltage of 1 volts；In drain region, D applies voltage Vp3, is, for example, 6
Volts；Source area S is the voltage of 0 volts.In this way, electronics is mobile from source area S to drain region D in programming,
And accelerated at the drain region end D by high channel electric field and generate thermoelectron, kinetic energy is enough to overcome the energy of tunnel dielectric to hinder
Barrier, so that thermoelectron is from the drain region end D injection floating grid FG.
When being read out to storage unit, apply voltage Vr1 in control grid CG, Vr1 is, for example, the electricity of 4 volts
Pressure；Apply voltage Vr2 in auxiliary grid AG, voltage Vr2 is, for example, the voltage of 4 volts；In drain region, D applies voltage Vr3,
It is, for example, 1.2~3 volts.Closed due to the channel for the storage unit that total charge dosage is negative in floating grid FG at this time and
Electric current very little, and the channel of the slightly positive storage unit of total charge dosage is opened in floating grid FG and electric current is big, therefore storage can be passed through
The channel switch of unit/channel current size is come to judge to store the digital signal in this storage unit be " 1 " or " 0 ".
When erasing to storage unit, applies voltage Ve1 in control grid CG, be, for example, -10 volts.?
Substrate applies voltage Ve2, is, for example, 6 volts.In this way, can be established between floating grid FG and substrate one big
Electric field, and be able to that electronics is drawn out to substrate from floating grid FG using F-N tunnel-effect.
It is a kind of manufacturing process of NOR type flash memory cell of the preferred embodiment of the present invention depicted in Fig. 3 A to Fig. 3 F
Figure, to illustrate the manufacturing method of flash memories of the invention.In Fig. 3 A to Fig. 3 F, region A is in corresponding diagram 1A along A-
The section of A ' line, region B are the section in corresponding diagram 1A along B-B ' line.
Firstly, A referring to figure 3., provides substrate 300.This substrate 300 is, for example, silicon base.It has for example been formed in substrate 300
Component isolation structure 302, and to define active region.The forming method of component isolation structure 302 is, for example, zone oxidation method
(Local Oxidation, LOCOS) or shallow trench isolation method (Shallow Trench Isolation, STI).Element isolation
Structure 302 is, for example, arranged in parallel in the X direction, and is extended in the X direction and in a strip shape (as shown in Figure 1A).In this substrate
One dielectric layer 304 is formed on 300.The material of dielectric layer 304 is, for example, silica.The forming method of dielectric layer 304 is, for example,
Thermal oxidation method or chemical vapour deposition technique.
B referring to figure 3., forms conductor layer 306 on dielectric layer 304, and material is, for example, the polysilicon adulterated.This conductor
The forming method of layer 306 is, for example, after utilizing chemical vapour deposition technique to form one layer of undoped polysilicon layer, to carry out ion implanting
Step is to form；Or it in a manner of injecting doping when participating in the cintest, is formed using chemical vapour deposition technique.Then, in substrate
A pattern layers mask layer (not shown) is formed on 300, this patterned mask layer is distributed into strips.Removal is not patterned mask
After the doped polysilicon layer of layer covering, then patterned mask layer is removed, patterned conductor layer 306 can be formed.It is patterned
Conductor layer 306 be, for example, in the X direction it is arranged in parallel, extend in the X direction and in a strip shape, and position is in component isolation structure 302
Between substrate 300 on.
Dielectric layer 308 is formed in patterned conductor layer 306.The material of dielectric layer 308 is, for example, silica/nitridation
Silicon/oxidative silicon layer.The forming method of dielectric layer 308 is, for example, after first forming one layer of silica with thermal oxidation method, to recycle chemistry
Vapour deposition process sequentially forms silicon nitride layer and another layer of silicon oxide layer.Another layer of conductor layer 310 is formed in substrate 300.It leads
The material of body layer 310 is, for example, the polysilicon adulterated.The forming method of this conductor layer 310 is, for example, to utilize chemical vapour deposition technique
After forming one layer of undoped polysilicon layer, ion implanting step is carried out to form the conductor layer 310；Or to inject doping when participating in the cintest
Mode, the conductor layer 310 is formed using chemical vapour deposition technique.
C referring to figure 3. forms a pattern layers mask layer (not shown) in substrate 300, this patterned mask layer is at item
Shape distribution, to define the control grid of flash memories.Remove the doped polysilicon layer for not being patterned mask layer covering
Afterwards, the control grid 310a as flash memories can be formed.Then, continue to remove Jie for not being patterned mask layer covering
Electric layer 308, patterned conductor layer 306, dielectric layer 304 are to form dielectric layer 308a, floating grid 306a and tunnel Jie between grid
Electric layer 304a.Wherein, dielectric layer 308a, floating grid 306a and tunnel dielectric 304a between grid 310a, grid are controlled and constitutes heap
Folded gate structure.Later, patterned mask layer is removed.Two stacked gate architectures are only depicted in fig. 3 c, but the present invention is not
Limit is herein.Wherein, the conductor layer 310 on the B of region, dielectric layer 308, patterned conductor layer 306 and the quilt completely of dielectric layer 304
It removes, and exposes component isolation structure 302.
Then, in substrate 300 formed mask layer 314, with cover two stacked gate architectures 312 between substrate 300 (after
Continue the position of pre-formed auxiliary grid).The forming method of mask layer 314 is for example initially formed one layer of layer of photoresist material, it
Lithographic fabrication process is carried out afterwards to be formed.Then, it is mask with mask layer 314 and two stacked gate architectures 314, is doped
Injection, and in the substrate 300 in the outside of two stacked gate architectures 312 side that side of drain region (predetermined formed) substrate
Light doped drain region 316 is formed in 300.The method of injection doping is, for example, to carry out an ion implanting step.
D referring to figure 3. after removing mask layer 314, forms clearance wall 318 in the side wall of two stacked gate architectures 312.Between
The forming method of gap wall 318 is, for example, after first forming a layer insulating (not shown) in substrate 300, to utilize anisotropic etching
Method removes partial insulative layer to be formed.Later, mask layer 320 is formed, in substrate 300 to cover two stacked gate architectures
Substrate 300 (position of subsequent pre-formed auxiliary grid) between 312.The forming method of mask layer 320 is for example initially formed one layer
Layer of photoresist material carries out lithographic fabrication process to be formed later.With mask layer 320 and two with clearance wall 318
Stacked gate architectures 312 are mask, are doped injection, and the side in the substrate 300 in the outside of two stacked gate architectures 312
It is formed in the substrate 300 of (predetermined that side for forming drain region) and forms doped region 322.Injection doping method be, for example, into
One ion implanting step of row.Wherein, light doped drain region 316 constitutes the drain region 338 of flash memories with doped region 322.?
In another embodiment, doped region 322 optionally can also be only formed as the drain region 324 of flash memories.
E referring to figure 3. after removing mask layer 320, removes the component isolation structure between two stacked gate architectures 312
302.The method for removing the component isolation structure 302 between two stacked gate architectures 312 is, for example, first to form one in substrate 300
Pattern layers mask layer (not shown), this patterned mask layer have opening (extending in the Y-direction of Figure 1A) into strips with sudden and violent
Expose the substrate 300 (position of subsequent pre-formed auxiliary grid) between two stacked gate architectures 312, then proceed to remove not by
The component isolation structure 302 of patterned mask layer covering.Later, it is doped injection, and between two stacked gate architectures 312
Substrate 300 in form light doped region 326.
Then, one dielectric layer is formed in substrate 300, wherein Jie in the substrate 300 between two stacked gate architectures
Electric layer is as auxiliary grid dielectric layer 326.The material of auxiliary grid dielectric layer 326 is, for example, silica.The formation side of dielectric layer
Rule thermal oxidation method in this way, chemical vapour deposition technique or atomic layer deposition method.
F referring to figure 3. forms auxiliary grid 330 in the substrate 300 between two stacked gate architectures 312.Form auxiliary
The method of grid 330 is, for example, first to form conductor layer in substrate 300, this conductor layer is filled up between two stacked gate architectures 312
Gap, then remove part this conductor layer to form auxiliary grid 330.It include etch-back in the method for removing part conductor layer
Method.Moreover, not having component isolation structure 302, therefore 330 meeting of auxiliary grid in substrate 300 below auxiliary grid 330
Filling is formed by groove after removing component isolation structure 302.
The subsequent manufacture craft for completing NOR type flash memories is well known to prior art person, and details are not described herein.
The present invention is using auxiliary grid 330 is formed in the substrate 300 between two stacked gate architectures 312, due to not having
Using photoetching technique is arrived, therefore manufacture craft nargin can be increased.Moreover, in the above-described embodiments, it is single to form two storages
Meta structure explains for example.Certainly, using the manufacturing method of NOR type flash memories of the invention, actual needs can be regarded
And form number storage unit appropriate.The manufacturing method of NOR type flash memories of the invention, actually applies and is being formed
Whole memory cell array.
It is auxiliary in no applied voltage before auxiliary grid in NOR type flash memories of the invention and its manufacturing method
It helps in the substrate below grid and source area is not formed, therefore the leakage from source area to drain region can be generated to avoid storage unit
Electric current.And when operating storage unit, by auxiliary grid apply one voltage and in the substrate below auxiliary grid shape
At inversion layer using as source area.Since NOR type flash memories of the invention are not needed such as existing separated grid memory
General additional setting selection gate, therefore storage unit can be made to have good in the case where not increasing the size of storage unit
Good electrical performance.
Although disclosing the present invention with preferred embodiment, it is not intended to limit the invention, it is any to be familiar with this technology
Person can make some changes and embellishment without departing from the spirit and scope of the present invention, therefore protection scope of the present invention should
It is subject to what the appended claims were defined.
Claims (15)
1. a kind of NOR type flash memories, comprising: the first storage unit is arranged in a substrate, the first storage unit packet
It includes:
Stacked gate architectures, setting is on this substrate；
Auxiliary grid is arranged in substrate of one first side of the stacked gate architectures；
Auxiliary grid dielectric layer is arranged between the auxiliary grid and the substrate；
Light doped region is provided only in the substrate below the auxiliary grid between two stacked gate architectures, wherein by
The auxiliary grid applies a voltage and forms an inversion layer in the substrate below the auxiliary grid using as source region,
In, do not have component isolation structure in the substrate below auxiliary grid, and light doped region is continuous strip；And
Drain region is arranged in the substrate of second side for the stacked gate architectures, and first side is opposite with the second side.
2. NOR type flash memories as described in claim 1 further include the second storage unit, with first storage unit
In mirror configuration, the auxiliary grid or the drain region are shared.
3. NOR type flash memories as described in claim 1, wherein the stacked gate architectures are included at least:
Floating grid, setting is on this substrate；
Tunnel dielectric is arranged between the floating grid and the substrate；
Grid is controlled, is arranged on the floating grid；And
Dielectric layer between grid is arranged between the control grid and the floating grid.
4. NOR type flash memories as described in claim 1, further include a clearance wall, the stacked gate architectures are arranged in
Side wall.
5. NOR type flash memories as claimed in claim 3, wherein the material of the floating grid includes DOPOS doped polycrystalline silicon.
6. NOR type flash memories as claimed in claim 3, wherein the material of the tunnel dielectric includes silica.
7. NOR type flash memories as claimed in claim 3, wherein the material of dielectric layer includes silica/nitridation between the grid
Silicon/oxidative silicon.
8. a kind of manufacturing method of NOR type flash memories, comprising:
A component isolation structure is formed in a substrate；
At least two stacked gate architectures are formed on this substrate；
A drain region is formed in the substrate on the outside of two stacked gate architectures；
Remove the component isolation structure between two stacked gate architectures；
A light doped region is formed in the substrate between two stacked gate architectures, so that the light doped region is provided only on this
Between two stacked gate architectures；
An auxiliary grid dielectric layer is formed in the substrate between two stacked gate architectures；And
An auxiliary grid is formed in the substrate between two stacked gate architectures, and by applying one in the auxiliary grid
Voltage and an inversion layer is formed in the substrate below the auxiliary grid using as source region, wherein the light doped region is set
It sets in the lower section of the auxiliary grid, does not have component isolation structure in the substrate below auxiliary grid, and light doped region is
Continuous strip.
9. the manufacturing method of NOR type flash memories as claimed in claim 8, wherein on the outside of two stacked gate architectures
The step of drain region is formed in the substrate include:
One first mask layer is formed, on this substrate to cover the substrate between two stacked gate architectures；
Using first mask layer and two stacked gate architectures as mask, it is doped injection and forms the drain region；And
Remove first mask layer.
10. the manufacturing method of NOR type flash memories as claimed in claim 8, wherein further including in the two piled grids knot
The side wall of structure forms a clearance wall.
11. the manufacturing method of NOR type flash memories as claimed in claim 10, wherein in the outer of two stacked gate architectures
The step of forming the drain region in the substrate of side include:
One first mask layer is formed, on this substrate to cover the substrate between two stacked gate architectures；
Using first mask layer and two stacked gate architectures as mask, it is doped injection and forms a light doped drain region；
Remove first mask layer；
The clearance wall is formed in the side wall of two stacked gate architectures；
One second mask layer is formed, on this substrate to cover the substrate between two stacked gate architectures；
Two stacked gate architectures using second mask layer and with the clearance wall are doped injection and form one as mask
Doped region；And
Remove second mask layer.
12. the manufacturing method of NOR type flash memories as claimed in claim 8, wherein forming at least two heaps on this substrate
The step of folded gate structure includes:
One first dielectric layer is formed on this substrate；
One first conductor layer is formed on first dielectric layer；
Pattern first conductor layer；
One second dielectric layer is formed in patterned first conductor layer；
One second conductor layer is formed on second dielectric layer；
Second conductor layer is patterned to form a control grid；And
Pattern second dielectric layer, patterned first conductor layer, first dielectric layer with formed dielectric layer between a grid,
One floating grid and a tunnel dielectric.
13. the manufacturing method of NOR type flash memories as claimed in claim 8, wherein between two stacked gate architectures
The substrate on to form the method for the auxiliary grid dielectric layer include thermal oxidation method, chemical vapour deposition technique or atomic layer deposition
Method.
14. the manufacturing method of NOR type flash memories as claimed in claim 8, being somebody's turn to do between two stacked gate architectures
A step of auxiliary grid is formed in substrate include:
A third conductor layer is formed on this substrate；And
The part third conductor layer is removed to form the auxiliary grid.
15. the manufacturing method of NOR type flash memories as claimed in claim 14 is removing the part third conductor layer with shape
Method at the auxiliary grid includes eatch-back lithography.
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| TWI696273B (en) | 2019-05-15 | 2020-06-11 | 力晶積成電子製造股份有限公司 | Flash memory with assistant gate and method of fabricating the same |
| CN110211875B (en) * | 2019-06-06 | 2021-11-02 | 武汉新芯集成电路制造有限公司 | Method for manufacturing semiconductor device |
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| CN1373517A (en) * | 2001-03-06 | 2002-10-09 | 力旺电子股份有限公司 | Embedded flash memory and its operating method |
| CN1855508A (en) * | 2005-04-18 | 2006-11-01 | 力晶半导体股份有限公司 | Non-volatile memory, its production and operation |
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| CN1855508A (en) * | 2005-04-18 | 2006-11-01 | 力晶半导体股份有限公司 | Non-volatile memory, its production and operation |
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