TWI224858B - Flash memory cell, manufacturing method of memory cell and operation method thereof - Google Patents

Abstract

A memory cell is consisted of a substrate, gate structure, source region, erasing gate, erasing gate dielectric layer, selecting gate, selecting gate dielectric layer and drain region. The gate structure comprised a tunneling oxide, a floating gate, a inter-gate dielectric layer, control gate and spacer is set on the substrate. The source region is set in the substrate at one side of the gate structure. The erasing gate is set on the source region at one side of the gate structure. The erasing gate dielectric layer is set between the erasing gate and source region. The selecting gate is set at the other side of gate structure. The selecting gate dielectric layer is set between the selecting gate and the substrate. The drain region is set in the substrate at one side of the selecting gate.

Description

1224858 _Case No. 92106129_ Revised Year of the Month_ V. Description of the Invention (1) [Technical Field to which the Invention belongs] The present invention relates to a memory element, and more particularly to a flash memory cell, a flash memory cell Manufacturing method and operation method. [Previous technology] Flash memory devices have become a personal computer and an advantage because they can store, read, and erase data multiple times, and the stored data will not disappear even after the power is turned off. A non-volatile memory element widely used in electronic equipment. A typical flash memory device is made of doped polycrystalline silicon to make a floating gate and a control gate. Moreover, the control gate is directly arranged on the floating gate, the floating gate and the control gate are separated by a dielectric layer, and the floating gate and the substrate are separated by a tunnel oxide layer (also (The so-called stacked gate flash memory). When writing data to the flash memory, the control gate and source / drain regions are biased so that electrons are injected into the floating gate. When reading the data in the flash memory, a working voltage is applied to the control gate. At this time, the charged state of the floating gate will affect the on / off of its lower channel (Channel), and the on / off of this channel Off is the basis for judging the data value "0" or "1". When flash memory is erasing data, the relative potential of the substrate, drain (source) region, or control gate is increased, and the tunneling effect is used to pass electrons from the floating gate through the tunneling oxide layer. (Tunneling Oxide) and drain to the substrate or source (ie, Substrate Erase or Drain (Source) Side Erase), or pass through the dielectric layer and drain to the control gate.

10575twf1.ptc Page 8 1224858 _Case No. 92106129_ Year, Month, and Day Amendment__ 5. Description of the Invention (2) However, when erasing the data in the flash memory, it is difficult to control the amount of electrons discharged from the floating gate. Therefore, it is easy for the floating gate to discharge too many electrons with a positive charge, which is called over-erase. When this over-erase phenomenon is too serious, even the channel below the floating gate will continue to be in a conducting state when the control gate is not applied with a working voltage, and the data will be misjudged. Therefore, in order to solve the problem of excessive erasure of components, many flash memories will adopt the design of a split gate. Its structure is characterized in that in addition to the control gate and the floating gate, it also has a control gate. Select the gate (or erase gate) from the side of the floating gate and above the base. This selection gate (erase gate) is connected to the control gate, floating gate, and base with a gate. The dielectric layers are separated. In this way, when the over-erase phenomenon is too serious, and the channel below the floating gate is continuously opened without the control voltage applied to the gate, the channel below the selected gate (erasing the gate) can remain closed. The state makes the drain / source region impossible to conduct and prevents misjudgment of data. FIG. 1 is a cross-sectional view showing a conventional structure of a split gate flash memory cell. Please refer to Fig. 1. This flash memory cell sequentially arranges a tunneling oxide layer 10 on a substrate 100, a floating gate electrode 10, an inter-gate dielectric layer 106, and a control gate electrode 10. 8. A gap wall 1 10 is provided on the side wall and the top of the control gate electrode 106, and a gap wall 1 12 is provided on the side wall of the floating gate electrode 104. The selection gate 1 1 4 is set on the side wall of the floating gate 10 4 and the control gate 1 0 6. Select gate The oxide layer 1 1 6 is disposed between the select gate 1 1 4 and the substrate 100. The source region 1 1 8 is provided in a floating gate 1 104 on which the selection gate 1 1 4 is not formed and a substrate 1 0 0 on the side of the control gate 1 0 6. The drain region 1 2 0 is provided on the selective gate 1 1 4

10575twf1.ptc Page 9 1224858 _Case No. 92106129_ Year Month Amendment _ V. Description of the invention (3) The floating gate 1 0 4 and the control gate 1 0 6 are in the substrate 1 0 0 on the side. When the flash memory cell is programmed, a bias voltage of 10 volts is applied to the control gate 108; a bias voltage of 10 volts is applied to the select gate 1 1 4; and a source voltage of 1 1 8 is applied to 6 With a bias of volts, the drain region 120 is 0 volts. In this way, during programming, the electron system can be moved from the drain region 120 to the source region 118, and the electrons can be injected from the source region 118 to the floating gate 104, and the program化 Memory cells. When erasing the memory cell, 0 volts are applied to the control gate 10 8; a bias voltage of 10 to 12 volts is applied to the selection gate 1 1 4; the source region 1 1 8; the drain Zone 1 2 0 is floating. In this way, a large electric field can be established between the floating gate 1 0 4 and the selection gate 1 1 4, and the F-N tunneling effect can be used to pull electrons from the floating gate 1 0 4 to the selection. Gate 1 1 4 For the above flash memory cell, the gate 1 1 4 series is selected as the channel transistor and the erase gate at the same time. That is, when erasing, the gate 1 1 4 is selected as the erasing gate. If the thickness of the gate oxide layer is too thin, the substrate will be destroyed during erasing (Substrate breakdown), so it must be increased. The thickness of the gate oxide layer 1 16 is selected (it needs to be greater than about 200 angstroms) to avoid substrate collapse. However, when programming, the gate system is selected as the gate of the channel transistor. When the thickness of the gate oxide layer 1 1 6 is increased, the channel transistor needs to be opened to apply the gate 1 1 4 The larger voltage causes the channel transistor to have a high starting voltage, and the current flowing from the source to the drain cell becomes smaller, resulting in a slower memory cell operation speed. Furthermore, if the channel transistor is made to have a low starting voltage, when the thickness of the selected gate oxide layer 1 16 becomes thicker, the control of the selected gate channel becomes worse, and the substrate leakage current becomes larger. . Because memory cells are programmed very efficiently,

10575twf1.ptc Page 10 1224858 _ Case No. 92106129_ Year Month Day Amendment _ V. Description of the Invention (4) Therefore, there will be a situation of programmatic interference (Disturb). [Summary of the Invention] In view of this, one object of the present invention is to provide a flash memory cell, a method for manufacturing the flash memory cell, and an operating method thereof, which can increase the cell current of the memory cell, reduce stylized interference, and improve memory. Element operating speed. The invention provides a flash memory cell. The flash memory cell comprises a substrate, a tunneling dielectric layer disposed on the substrate, a floating gate disposed on the tunneling dielectric layer, and a floating gate disposed on the floating gate. Inter-gate dielectric layer, control gate provided on inter-gate dielectric layer, first gap wall provided on side wall and top of control gate, second gap wall provided on side wall of floating gate, provided on control The gate electrode and the source region in the substrate on the first side of the floating gate, the erase gate disposed on the source region, and the erase gate dielectric disposed between the source region and the erase gate Layers, a selection gate disposed on a side wall on the second side of the control gate and the floating gate, a selection gate dielectric layer disposed between the substrate and the selection gate, and a selection gate disposed on the selection gate side The drain region in the substrate. In the flash memory cell described above, the thickness of the erased gate dielectric layer is about 200 angstroms to 250 angstroms. The thickness of the gate dielectric layer is selected to be about 50 angstroms to 75 angstroms. The thickness of the tunneling dielectric layer is about 85 to 110 angstroms. According to the present invention, an erase gate is provided on the source region, so that the erase gate of the flash memory cell is separated from the selection gate. Therefore, the thickness of the selection gate dielectric layer can be reduced, and the gate dielectric layer can be erased. The thickness can be increased. Therefore, when the memory cell is programmed, it is not necessary to apply a large voltage to the selection gate. Moreover, since the oxide layer under the selection gate can be thinned, it can be increased during reading.

10575twf1.ptc Page 11 1224858 _ Case No. 92106129_ Year Month Amendment _ V. Description of the Invention (5) The memory cell current can be added to maintain the operation rate of the memory cell. In addition, the memory cell does not collapse when it is erased. The invention provides a flash memory cell, which is composed of a substrate; a first gate structure and a second gate structure provided on the substrate; and each of the first gate structure and the second gate structure includes at least A floating gate on a substrate and a control gate provided on the floating gate; a source region provided in the substrate between the first gate structure and the second gate structure; and a first gate structure and Erase gates between the second gate structure and located on the source region; erase gate dielectric layers disposed between the source region and the erase gate; respectively disposed opposite the source region A first selection gate and a second selection gate on a side wall of one side of the first gate structure and the second gate structure; a selection gate provided between the substrate and the first selection gate and the second selection gate A dielectric layer; and a drain region in the substrate on the side of the first selection gate and the second selection gate, respectively. In the flash memory cell described above, the thickness of the erased gate dielectric layer is about 200 angstroms to 250 angstroms. The thickness of the gate dielectric layer is selected to be about 50 angstroms to 75 angstroms. The thickness of the tunneling dielectric layer is about 85 to 110 angstroms. According to the present invention, an erase gate is provided on the source region between the first gate structure and the second gate structure, so that the erase gate of the flash memory cell is separated from the selected gate, so the gate dielectric layer is selected The thickness of the dielectric layer can be reduced, and the thickness of the gate dielectric layer can be increased. Therefore, when the memory cell is programmed, it is not necessary to apply a large voltage to the selection gate. Moreover, since the oxide layer under the selected gate can be thinned, the memory cell current can be increased during reading, and the operation rate of the memory cell can be maintained. In addition, when the memory cells are erased,

10575twf1.ptc Page 12 1224858 _Case No. 92106129_ Year Month Revision _ V. Description of the invention (6) The phenomenon of base collapse will occur. Moreover, the present invention shares one erase gate for every two adjacent two gate structures, so the volume of flash memory cells is not increased. The invention provides a method for manufacturing a flash memory cell. This method provides a substrate on which a first gate structure and a second gate structure have been formed. The first gate structure and the second gate structure are respectively formed by A tunneling dielectric layer formed on a substrate, a floating gate formed on the tunneling dielectric layer, an inter-gate dielectric layer formed on the floating gate, and a control gate formed on the inter-gate dielectric layer And a first gap formed on the top and side walls of the control gate. Next, a source region is formed in the substrate between the first gate structure and the second gate structure, an erased gate dielectric layer is formed on the surface of the source region, and a second gate electrode is formed on the side wall of the floating gate. Gap wall. Then, an erase gate is formed on the source region, and the erase gate fills a gap between the first gate structure and the second gate structure. After forming a third gap wall on the side wall of the first gate structure and the second gate structure, a selective gate dielectric layer is formed on the substrate, and a first selective gate is formed on the side wall of the third gap wall. With the second selection gate. After that, the first > polar region and the second polar region are formed in the substrate on the side of the first selected gate and the second selected gate. In the above method for manufacturing a memory cell, the first gate structure and the second gate structure are formed in a step of sequentially forming a first dielectric layer, a first conductor layer, and a second dielectric layer on a substrate. Next, a second conductor layer is formed on the second dielectric layer, and the second conductor layer is patterned to form a control gate. Then, a first gap wall is formed on the side wall and the top of the control gate electrode, and the control gate electrode with the first gap wall is masked to pattern the second dielectric layer and the first conductor.

10575twfl.ptc Page 13 1224858 _Case No. 92106129_Year_Year__ 5. Description of the invention (7) layer, the first dielectric layer to form an inter-gate dielectric layer, a floating gate and a tunneling dielectric layer. According to the present invention, the conductor layer is formed as the erase gate in the source region, so that the erase gate is separated from the selective gate, so the thickness of the erase dielectric layer can be made thicker (greater than about 200 angstroms). The selection gate dielectric layer under the selection gate need not be so thick, but can be made thinner (about 65 Angstroms). Therefore, the starting voltage can be reduced, the cell current can be increased, and the interference when programming the memory cell can be reduced, so that the operation speed of the memory cell can be accelerated. Moreover, the thicker dielectric layer can avoid the problem of substrate collapse during the erasing. The invention provides a method for operating a flash memory cell, which is applicable to at least a substrate, a floating gate disposed on the substrate, a control gate disposed on the floating gate, and a control gate and a floating gate. A source region in the substrate on the first side, an erase gate disposed on the first side of the control gate and the floating gate and the source region, and a second region disposed on the control gate and the floating gate A selection gate on a side wall, and a flash memory cell disposed in a drain region of the substrate on one side of the selection gate; the method includes: applying a control gate to the control gate when the flash memory is programmed; The first positive voltage is a second positive voltage applied to the selection gate, the third positive voltage is applied to the source region and the drain region is left floating to program the flash memory cell using the channel hot electron injection effect. When erasing the flash memory cell, a fourth positive voltage is applied to the erase gate, so that the control gate is 0 volts, and the source and drain regions are floating to erase the flash using the F-N tunneling effect. Memory element. In the method for operating a flash memory cell, the present invention

10575twf1.ptc Page 14 1224858 ------- M No. 92106129 __ ^ _ β_S_MODIFY__ V. Description of the invention (8) Operation time 'Electrons are removed through the erase gate, not through the selective gate Therefore, the thickness of the gate dielectric layer can be made thicker (greater than about 200 angstroms), and the selection of the gate dielectric layer under the gate need not be so thick, and it can be made. Thinner (about 65 Angstroms). Therefore, the initial voltage can be reduced, and the cell current can be increased, and the interference when programming the memory cell can be reduced, so that the operation speed of the memory cell is accelerated. In addition, the thicker dielectric layer can avoid the problem of substrate collapse during erasing. ^ In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in conjunction with the accompanying drawings, and described in detail as follows: [Embodiment] Figure 2 shows It is a structural cross-sectional view of a flash memory of the present invention. Please refer to FIG. 2. The flash memory of the present invention is composed of a substrate 200, a gate structure 2 0, a source region 2 0 4, an erase gate 2 0, and an erase gate dielectric layer 2. 〇8, the spacer 2 1 〇, the selection gate 2 1 2, the selection gate dielectric layer 2 1 4 and the drain region 2 16 is formed. The gate structure 202 is disposed on the substrate 200. The gate structure 202 is formed by a through oxide layer 2 1, a floating gate 2 2 0, an inter-gate dielectric layer 2 2 2, and a control gate. 2 2 4 and the partition wall 2 2 6, 2 2 8, and every two adjacent gate structures 2 2 2 are a gate structure group 2 3 0. The tunneling oxide layer 2 1 8 is disposed on the substrate 2 0 0. The floating gate electrode 2 2 0 is disposed on the tunneling oxide layer 2 1 8. The inter-gate dielectric layer 2 2 2 is disposed on the floating gate electrode 220. The control gate electrode 2 2 4 is disposed on the inter-gate dielectric layer 2 2 2. The partition wall 2 2 6 is disposed on the top and the side wall of the control gate electrode 2 2 4. The partition wall 2 2 8 is disposed on a side wall of the floating gate electrode 2 2 0.

10575twfl.ptc Page 15 1224858-Case No. 92106129_Year Month Date --- 5. Description of the invention (9) The source region 2 0 4 is arranged in the substrate 2 between the gate structure groups 2 3 0 (That is, in the gate structure 2 0 2 -side base 2 0 0). The erase gate 2 6 is disposed on the source region 2 4 between the gate structure groups 2 3 0. The erase gate dielectric layer 20 is disposed between the erase gate 206 and the source region 204, and the material thereof is, for example, silicon oxide, and the thickness thereof is, for example, greater than about 200 angstroms. The partition wall 2 10 is provided on the side walls on both sides of the gate structure group 2 2 8 (that is, on the other side wall of the gate structure 2 02 where the gate electrode 2 06 is not provided). The selection gate 2 1 2 is disposed on a side wall of the partition wall 2 1 0. The selection gate dielectric layer 2 1 4 is disposed between the selection gate 2 12 and the substrate 200, and the material thereof is, for example, silicon oxide, and the thickness is, for example, about 50 angstroms to 70 angstroms. The drain region 2 1 6 is disposed in the substrate 2 0 0 on the side of the selection gate 2 1 2. In the above flash memory cell, a wiper is additionally provided on the source 'danger zu 4-gate 2 6 to separate the erase of the flash memory cell 2 6 from the selection gate 2 1 2'. The thickness of the selected gate dielectric layer 214 under the selected gate electrode 212 can be reduced, and the erased gate dielectric layer 208 below the gate electrode 206 can be thickened. Therefore, when the memory cell is programmed, it is not necessary to apply a large voltage to the selection '^' 2 to maintain the operation rate of the memory cell, and the memory cell does not cause the collapse of the substrate when it is erased. It was invented in every two adjacent two wide-polar structures 202 (memory cells) to have a total of 206 winter gates, so it will not increase the volume of flash memory cells. Next, the flash memory of the present invention will be explained. Figure 3F of the manufacturer shows a cross-section of the manufacturing process of the flash memory of the present invention:

Baixian Please refer to FIG. 3A to provide the substrate 3 0 0. Here its ^ ηη main r formation-layer through dielectric layer 3G2 ′ of this tunneling dielectric layer 3 () 2 = K

Page 16 1224858 _Case No. 92106129_ Years and Months Revision_ V. Description of the Invention (10) The method for forming the silicon oxide and the tunnel dielectric layer 3 0 2 is, for example, a thermal oxidation method, and its thickness is, for example, 8 5 angstroms to 1 About 10 Angstroms. Next, a conductive layer 304 is formed on the tunneling dielectric layer 302. The conductive layer 304 is made of, for example, doped polycrystalline stone. The conductive layer 304 is formed, for example, by chemical vapor deposition to form an undoped layer. After the polycrystalline silicon layer, an ion implantation step is performed to form it. The thickness of the conductive layer 304 is, for example, about 200 angstroms, and the dopant implanted into the conductive layer 304 is, for example, arsenic ions, so as to facilitate the formation of a circular shape that is favorable for erasing in the subsequent thermal oxidation process. Then, an inter-gate dielectric layer 3 06 is formed on the substrate. The material of the inter-gate dielectric layer 3 0 6 is, for example, silicon oxide / silicon nitride / silicon oxide, and the thickness of each layer is 60 to 100 angstrom, 70 to 100 angstrom, and 60 to 100 0 Angstroms. The step of forming the inter-gate dielectric layer 3 06 is, for example, firstly forming a silicon oxide layer by a thermal oxidation method, then forming a silicon nitride layer by a chemical vapor deposition method, and then using wet hydrogen / oxygen (H2 / 02 gas). ) Deoxidizing part of the nitrided stone layer to form another layer of oxidized stone layer. Of course, the material of the inter-gate dielectric layer 306 can also be a silicon oxide layer, silicon oxide / silicon nitride, or the like. Next, refer to Figure 3B. After a conductive layer (not shown) is sequentially formed on the substrate 300, the conductive layer is patterned using a mask to define the conductive layer 308 for controlling the gate. The material of the conductive layer 308 is, for example, doped polycrystalline silicon, and the method of forming the conductive layer 308 is, for example, formed by using a chemical vapor deposition method in a field (I η-Si t u) doped ion. After the cover is removed, an insulating layer 3 1 0 (gap wall) is formed on the side wall and the top of the conductive layer 3 0 8. The material of the insulating layer 3 1 0 (spacer wall) is, for example, silicon oxide, and the method of forming the insulating layer 3 1 0 (spacer wall) is, for example, a thermal oxidation method.

10575twf1.ptc Page 17 1224858 ___ Case No. 92106129 Vehicle month date correction _ V. Description of the invention (11) Then refer to Figure 3 C, with the conductor layer 3 〇8 and the insulation layer 3 1 0 (gap wall) as the cover The curtain defines the inter-gate dielectric layer 306, the conductor layer 304, and the tunneling dielectric layer 302 'so that they form the inter-gate dielectric layer 306a, the conductor layer 304a, and the tunneling dielectric layer 302a, respectively. Among them, the conductor layer 3 0 4 a is used as a floating gate. That is, the conductor layer (control gate) 3 0 8 shown in the figure, the inter-gate dielectric layer 3 6 a, the conductor layer (floating gate) 3 0 4 a, and the oxide layer 3 0 2 (tunneling oxide layer) ) Constitute the gate structure 3 1 1. Then, a patterned masking layer 312 is formed on the entire substrate 300, and the patterned masking layer 312 exposes a region intended to form the source region 314. Then, a patterned mask layer 3 1 2 is used as a mask to perform an ion implantation step, and a dopant is implanted into the substrate 300 on one side of the gate structure to form a source region 3 1 4. Among them, the two gate structures 3 1 1 can be regarded as one gate structure group. In the gate structure group, a source region 3 1 4 is formed between the gate structures 3 1 1. Then referring to FIG. 3D, after the patterned mask layer 3 1 2 is removed, an erased gate dielectric layer 3 丨 6 is formed on the surface of the source region 3 1 4 between the gate structures, and the substrate 300 is formed. A dielectric layer 318 is formed, and an insulating layer (spacer) 3 2 0 is formed on a side wall of the conductive layer 304a (floating gate). The material of the gate dielectric layer 316, the dielectric layer 318, and the insulating layer (gap wall) 3 2 0 is, for example, silicon oxide, and the electrode dielectric layer 316, the dielectric layer 318, and the insulation layer (gap wall) 32 are erased. The method of forming 〇 is, for example, a thermal oxidation method. Among them, if the thickness of the erased oxide layer 3 丨 6 is greater than 200 angstroms or more, its thickness is preferably 200 angstroms to 25 angstroms ^. Then, a layer 3 2 2 is formed on the source region 3 1 4 (that is, between the gate structures 3 丨 i). The conductor layer 3 2 2 is used for erasing the gate. Conductor layer 3 2 2-The material is, for example, doped polycrystalline silicon. The formation method of the conductor layer 3 2 2 is firstly doped with ions in the field by chemical vapor deposition on the substrate.

10575twf1.ptc Page 18 1224858 _Case No. 92106129_ Year and month revision_ V. Description of the invention (12) A conductor layer (not shown) is formed on 3 0 0, and this conductor layer fills the gate structure 3 1 1 Gap. Then, the conductor layers inside and outside the gap of the gate structure 3 1 1 are removed to form them. Next, referring to FIG. 3E, a spacer 3 2 4 is formed on the other side of the gate structure 3 1 1 where the conductor layer 3 2 2 is not formed. The step of forming the spacer 3 2 4 is, for example, first forming a high temperature silicon oxide layer (High Temperature Oxide (HTO)) having a thickness of about 150 angstroms to 400 angstroms, and then removing the part by using an anisotropic # etch process. It is formed by oxidizing the silicon layer at high temperature. Part of the dielectric layer 3 1 8 is also removed when the spacer 3 2 4 is formed, leaving only the dielectric layer 3 1 8 a. The dielectric layer 3 1 8 a can also be regarded as a part of the spacer 3 2 4. Then, a selective gate dielectric layer 3 2 6 is formed on the substrate 300, and an insulating layer 3 2 8 is formed on top of the conductive layer 3 2 2. The material of the gate dielectric layer 3 2 6 is, for example, silicon oxide, and its thickness is, for example, about 50 angstroms to 70 angstroms. The method of forming the gate dielectric layer 3 2 6 and the insulating layer 3 2 8 is, for example, a thermal oxidation method. . Referring to FIG. 3F, a conductive layer 3 3 0 is formed on the other side wall of the gate structure 3 1 1 where the conductive layer 3 2 2 is not formed. The material of the conductive layer 3 3 0 is, for example, doped polycrystalline silicon. The method of forming the conductive layer 3 3 3 is, for example, to form a conductive layer on the substrate 3 0 by chemical vapor deposition in the field doping ions method ( (Not shown). Then, a part of the conductor layer is removed by using an anisotropic etching process to form it. After that, using the gate structure 3 1 1 and the conductive layer 3 3 0 as a mask, an ion implantation method is used to form a drain region 3 3 2 in the substrate 3 3 0 on the side of the conductive layer 3 3 0. The subsequent process of completing flash memory is well known to those skilled in the art, and will not be repeated here. In the above embodiments, the present invention forms a conductor layer due to a source region.

10575twf1.ptc Page 19 1224858

V. Description of the invention (13) 3 2 2 As the erase gate, the erase gate is separated from the select gate, so the thickness of the inter-dielectric dielectric layer 316 can be made thicker (about 200 angstroms) However, the selective interlayer dielectric layer 3 2 6 under the selection gate does not need to be thickened, and can be made thinner (about 65 angstroms). Because of &, the initial can be reduced, the cell current can be increased, and the interference during the process of the memory cell can and can be reduced, so that the operation speed of the memory cell is accelerated. In addition, the f-degree of the f-electric layer is relatively thick, which can also avoid the problem of substrate collapse during the erasing. Next, please refer to FIG. 4A and FIG. 4B to understand the operation mode of the flash memory cell in the preferred embodiment of the present invention, which includes program (Program, FIG. 4A) and erase (Erase, FIG. 4B) and other operating modes. When the memory cell Qnl is programmed, a voltage of, for example, about 10 volts is applied to the selection gate 4068 to open a channel of the selection gate 4 06a; the control gate 4043 is applied A positive bias voltage ^ 4 is, for example, about 10 volts to about 12 volts; the source region 412 applies a positive bias voltage VSp, for example, about 6 volts / volt; the drain region 410a is grounded. In this way, when programming, the electrical system moves from the source region 408 to the source region 412, and at the end of the source region 412 is accelerated by a high-channel electrical field to generate thermoelectrons, whose kinetic energy is sufficient to overcome the tunneling medium Layer ΐ ί: barrier, plus a high positive bias i ^ applied to the control open electrode 404a, and electrons are injected into the floating gate 402a from the source region 4 and 2 terminals, and

Lin ,, ni. Similarly, • When the memory cell is set to 2, the selection gate is under 4 0 6b: m is a voltage of about 10 volts to open the selection gate. For example, a positive bias is applied to the control gate 404b. The redundant leaves are about 12 volts; the source region 412 applies a positive bias VSP ', which is, for example, about 6 volts; the non-polar region 4i0b is grounded. So for

Page 20 Ϊ224858

In the formula, the electron system moves from the drain region 4 1 0 b to the source region 4 1 2 and is accelerated by the high-channel electric field at the source region 4 12 to generate thermoelectrons. The energy barrier of the tunneling oxide layer, coupled with the control gate electrode ^ 〇4b ^, is also added with a 'positive bias', so that hot electrons are injected from the source region 4 1 2 terminal into the floating idle electrode 4 0 2b, and Stylized memory cell Qn2.彳 甲 富 applies 0 volts to the memory cells Qnl, Q [......... ###, then controls gate 404b; applies a positive bias to erase gate 408 VSGE is, for example, about 10 volts to 12 volts, and the source electrodes 412, $ = 410a, and 410b are floating. In this way, a large electric field can be established between the floating interpole 4, ^^ 40 2b and the erase gate 4 0 8: in order to take advantage of the F_N tunneling effect to transport electrons from the floating idler electrodes 4 2a, 4 〇2b is pulled out into the erase gate 408, as shown in FIG. 7β. 1 Gate In the above embodiment, the gate electrode of the present invention is removed by erasing the gate electrode 40 8 instead of / by erasing j to make a 1 'system, so that the electrons pass through the electrode 406b, so the gate dielectric is erased. Layer: choose the gate) 06a or choose the gate around m angstrom), and choose to close the above 1 degree. The thickness of 2 is relatively thick (the thickness of the large electric layer does not need to be thickened, but f ^ can be selected to select the gate electrode right). Therefore, the starting voltage can be made thinner for the driver ’s jacket (about 65 Angstroms to reduce the interference when stylized memory cells are used), I can be increased, and can be fast. Moreover, the thick sound of the dielectric layer is erased ° The speed of the operation of the cell increases and the problem of crashing can be avoided. X ^ 7 7 'can also avoid erasing the time base. Although the present invention has been limited to the present invention with a better f, anyone skilled in this technology U, as above, is not Within the scope of God, it can be used for a variety of & ^ 'without deviating from the scope of the present invention should be treated as a towel f attached, so the definition of the Bao Jiaming patent of the present invention shall prevail.

1224858 Amendment No. 92106129 Brief Description of the Drawings Figure 1 shows a cross section of a conventional flash memory cell; Figure 2 shows a cross section of a flash memory cell of the present invention; Figure 3 Α and Figure 3F is a cross-sectional view of the manufacturing process of the flash memory cell of the present invention; Figure 4A is a schematic diagram of the stylized operation mode of the flash memory of the present invention. FIG. 4B is a schematic diagram of the flash memory erasing operation mode of the present invention. 3 0 0, 400 Tunneling oxide layer 2 2 0: Floating gate, 306, 306a: Control gate > 210 > 226: Select gate > 326, 314 > 332: Inter-gate dielectric layer 2 2 8, 31 0 > 3 2 0, 3 2 4: spacer 222 224 112 212 214 204 216 3 1 1: gate structure erase gate 3 1 6: erase gate dielectric layer 302, 30 2a : Tunneling dielectric layer memory cell group diagram description 100 > 200 102 104 106 108 110 1 14 116 118 120 202 206 208 218 230: substrate selection gate dielectric layer source region > and polar region

10575twf1.ptc Page 22 1224858 _Case No. 92106129_ Year, month, and day correction diagrams 304 > 304a, 308, 322, 330: Conductor layer 3 1 2: Patterned photoresist layer 318, 318a: Dielectric layer 3 2 8: Insulation layer

10575twf1.ptc Page 23

Claims (1)

1224858 _Case No. 92106129_ Amendment of the month of the year _ 6. The scope of patent application 1. A flash memory cell includes: a substrate; a tunneling dielectric layer disposed on the substrate; a floating gate disposed on On the tunneling dielectric layer; an inter-gate dielectric layer disposed on the floating gate; a control gate disposed on the inter-gate dielectric layer; a first gap wall disposed on the control gate A side wall and a top; a second gap wall disposed on the side wall of the floating gate; a source region disposed in the substrate on the first side of the control gate and the floating gate; an erase gate A gate dielectric layer is disposed between the source region and the erase gate; a selection gate is disposed between the control gate and the floating gate; One of the sidewalls on the second side; a selection gate dielectric layer disposed between the substrate and the selection gate; and a drain region disposed in the substrate on one side of the selection gate, wherein the wiper The thickness of the gate-eliminating dielectric layer is greater than the thickness of the selected gate dielectric layer. 2. The flash memory cell according to item 1 of the scope of patent application, wherein the thickness of the erased gate dielectric layer includes about 200 angstroms to about 250 angstroms. 3. The flash memory cell according to item 1 of the scope of patent application, wherein the thickness of the selected gate dielectric layer includes about 50 angstroms to 75 angstroms. 10575twf1.ptc Page 24 1224858 _Case No. 92106129_ Year Month Date__ VI. Patent Application Range 4. The flash memory cell as described in the first patent application range, wherein the thickness of the tunneling dielectric layer includes 85 Angstroms to about 110 angstroms. 5. The flash memory cell according to item 1 of the scope of patent application, wherein a third gap wall is further provided between the selection gate, the control gate, and the floating gate. 6. A flash memory cell comprising: a substrate; a first gate structure and a second gate structure disposed on the substrate, the first gate structure and the second gate structure each including at least A floating gate disposed on the substrate and a control gate disposed on the floating gate; a source region disposed on the substrate between the first gate structure and the second gate structure A erase gate is disposed between the first gate structure and the second gate structure and is located on the source region; a erase gate dielectric layer is disposed between the source region and the erase In addition to the gates; a first selection gate and a second selection gate are respectively disposed on the side walls of the first gate structure and the second gate structure opposite to the source region; A selection gate dielectric layer is disposed between the substrate and the first selection gate and the second selection gate; and a pair of drain regions are provided with the first selection gate and the second selection gate, respectively. In the base on one side, 10575twfl.ptc Page 25 1224858 _Case No. 92106129_ Years and months Amendment_ VI. Scope of patent application Where the thickness of the erased gate dielectric layer is greater than the thickness of the selected gate dielectric layer. 7. The flash memory cell according to item 6 of the scope of patent application, wherein the thickness of the erased gate dielectric layer includes about 200 angstroms to about 250 angstroms. 8. The flash memory cell according to item 6 of the scope of patent application, wherein the thickness of the selected gate dielectric layer includes about 50 angstroms to 75 angstroms. 9. The flash memory cell according to item 6 of the scope of patent application, wherein the first gate structure and the second gate structure further include: a tunneling dielectric layer disposed on the floating gate and the substrate Between; a gate dielectric layer provided between the control gate and the floating gate; a first gap wall provided on a side wall and a top of the control gate; and a second gap wall provided On the side wall of the floating gate. 10. The flash memory cell according to item 9 of the scope of the patent application, wherein the thickness of the tunneling dielectric layer includes about 85 angstroms to about 110 angstroms. 1 1. A method for manufacturing a flash memory cell includes: providing a substrate on which a first gate structure and a second gate structure have been formed; the first gate structure and the second gate structure are formed by A tunneling dielectric layer formed on the substrate, a floating gate formed on the tunneling dielectric layer, an inter-gate dielectric layer formed on the floating gate, and the inter-gate dielectric A control gate on the electrical layer and a first gap formed on the top and side walls of the control gate; in the substrate between the first gate structure and the second gate structure 10575twfl.ptc Page 26 1224858 _Case No. 92106129_ Modified Year_6. The scope of patent application forms a source region; a gate dielectric layer is formed on the surface of the source region, and the floating gate is formed on the surface of the source region. A side wall forms a second gap wall; an erase gate is formed on the source region, and the erase gate fills a gap between the first gate structure and the second gate structure; A gate structure forms a third gap wall on a side wall of the second gate structure; a selective gate dielectric layer is formed on the substrate, wherein the thickness of the erased gate dielectric layer is greater than the selection The thickness of the gate dielectric layer; forming a first selection gate and a second selection gate on the sidewall of the third gap; and a side of the first selection gate and the second selection gate A first drain region and a second drain region are formed in the substrate. 12. The method for manufacturing a memory cell according to item 11 of the scope of patent application, wherein the step of forming the first gate structure and the second gate structure includes: forming a first dielectric layer on the substrate Forming a first conductor layer on the first dielectric layer; forming a second dielectric layer on the first conductor layer; forming a second conductor layer on the second dielectric layer; patterning the first conductor layer Two conductor layers to form the control gate; forming the first gap wall on the side wall and the top of the control gate; and masking the control gate with the first gap wall to pattern the second dielectric Layer, the first conductor layer, and the first dielectric layer to form the gate 10575twf1.ptc Page 27 1224858 Case No. 92106129 Amendment of six layers ^ 6- The tunnel between the gate and the gate is set to float around the center, please apply for the special level. Recall that the description of the flashing fast is described in the merging of the oxygen layer thermoelectric encapsulation method, and the gap is divided between the two sides: the shape of the U surface, the second table, the area, the polar source wall, and the side in the middle. Extremely gate, set the floating method of the method 5 2 cell to the memory of Yi Ai ο ο 2 flashes, including the thick layer 1i if, 6-Fan Li specially asked for the introduction of the items described in the quick description The electrode gate erases the left and right sides of the method, including the thick layer 11 ^ ¾ Fan Li specially invited the Zhongruji electrode gate to select the cells made by the memory of the ancient memory of the flash. The method from left to right 5 7 to right and right is as follows: 'If you apply, please pass through the special tunnel in the middle of the special tunnel in the base and the bottom fan 1 thick 1 in the first layer of the first circle 1 into the first circle. What's fast and fast The choice of Egypt :: to build. The right cell, the left cell, Ei Yi ο 1 1 The layer of the step in the cell's memory, making J, making clothes, M, and the layer of the memory 言 Quick father. i 极 之 彳 层 解 闸 ^ # Absolutely, choose two, which should be made into a first shape. The upper part of the upper part of the upper part of the upper part of the bottom part of the upper part of the bottom part of the upper part of the upper part of the upper part of the upper part of the upper part of the upper part of the base. . Record of the cell of the memory of the memory of multiple memory ΘΜν _ The rapid hybrid arsenic mixed with the inclusion of the material included in the gate is set to A ,, / 彳 This method ☆ Sinochem 19 its oxygen 'thermal method Zhongru Kuai Yi Zuo is used to remember the flash UAul seed pole in the cell body that uses the proper method to do the operation; the gate is placed on the floating gate, and the floating bottom is based on a bracketing package. Quickly go to the bottom, the base cell should remember the setting flash 10575twf1.ptc Page 28 1224858 _Case No. 92106129_Year Month__ VI. Patent application source area is set in the substrate on the first side of one of the control gate and the floating gate; one erase A gate is disposed on the control gate, the first side of the floating gate, and the source region; a selection gate is disposed on a side wall of the control gate and a second side of the floating gate Upper; a drain region is disposed in the substrate on one side of the selection gate; a selection gate dielectric layer is disposed between the selection gate and the substrate; a gate dielectric layer is erased and disposed Between the erase gate and the substrate, and the thickness of the erase gate dielectric layer is greater than the thickness of the selected gate dielectric layer; the method includes: when programming the flash memory cell, The control gate applies a first positive voltage, the selection gate applies a second positive voltage, the source region applies a third positive voltage, and the drain region is grounded to program the channel using the hot electron injection effect of the channel. Flash memory cell; and when erasing the flash memory cell, applying a Four positive voltage, so that the control gate is extremely 0 volts, the source region and the drain region floating, utilizing F - N tunneling erase the flash memory device. 10575twfl.ptc Page 29