WO2001017031A1 - Easy shrinkable novel non-volatile semiconductor memory cell utilizing split dielectric floating gate and method for making same - Google Patents

Easy shrinkable novel non-volatile semiconductor memory cell utilizing split dielectric floating gate and method for making same Download PDF

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Publication number
WO2001017031A1
WO2001017031A1 PCT/US2000/023504 US0023504W WO0117031A1 WO 2001017031 A1 WO2001017031 A1 WO 2001017031A1 US 0023504 W US0023504 W US 0023504W WO 0117031 A1 WO0117031 A1 WO 0117031A1
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Prior art keywords
control gate
layer
semiconductor substrate
dielectric composite
diffusion region
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PCT/US2000/023504
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French (fr)
Inventor
Hsiang Lan Lung
Tao Cheng Lu
Mam Tsung Wang
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Macronix America, Inc.
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Priority to JP2001520477A priority Critical patent/JP4969748B2/en
Priority to AU69409/00A priority patent/AU6940900A/en
Publication of WO2001017031A1 publication Critical patent/WO2001017031A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923—Programmable transistors with more than two possible different levels of programmation

Definitions

  • the present invention relates in general to non-volatile digital memories and, more particularly, to an improved cell structure for a programmable non-volatile memory (such as conventional EEPROM or Flash EEPROM) that stores two-bits of information and methods for fabricating same
  • a programmable non-volatile memory such as conventional EEPROM or Flash EEPROM
  • Non-volatile memory devices such as EPROM, EEPROM, and flash EPROM devices, generally include a series of transistors which act as memory cells for storing a single-bit of information Each transistor has source and drain regions formed on a n- or p-type semiconductor substrate, a thin tunnel dielectric layer formed on the surface of the semiconductor substrate positioned between the source and drain regions, a floating gate (formed of polysihcon) positioned on the insulating layer for holding a charge, a control gate and an interpoly dielectric positioned between the floating gate and control gate
  • EPROM cell has an electrically floating gate which is surrounded by insulation and generally disposed between a source and drain region formed in a silicon substrate In earlier versions of these cells, charge is injected through the insulation by avalanche injection Later versions of EPROMs relied on channel injection for charging the floating gate Exposing the array to ultraviolet radiation erases these EPROMs
  • EEPROMs Electrically erasable EPROMs
  • charge is place into and removed from a floating gate by tunneling the charge through a thin oxide region formed on the substrate
  • charge is removed through an upper electrode
  • Flash EPROM Another type of common EPROM/EEPROM is referred to as Flash EPROM or Flash EEPROM
  • Flash EPROM Flash EEPROM
  • the floating gate used therein is a conductive material, typically made of polysihcon, which is insulated from the channel of the transistor by a thin layer of oxide or other insulating material, and insulated from the control gate or word line of the transistor by a second layer of insulating material
  • the "program" step for a flash memory cell is accomplished through so-called hot electron injection by establishing a large positive voltage between the gate and source, as much as twelve volts, and a positive voltage between the drain and source, for instance, seven volts
  • the act of discharging the floating gate is called the "erase” function for a flash device
  • This erase function is typically carried out by an F-N tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase)
  • source erase source erase
  • channel erase channel erase
  • a source erase operation is induced by establishing a large positive voltage from the source to gate, while floating the drain of the respective memory cell This positive voltage can be as much as twelve volts
  • an insulating film for insulating a floating gate and control gate from each other is a single layer of silicon oxide
  • the thickness of the second gate insulating film is required to further decrease
  • the interpoly dielectric had consisted of a single layer of silicon dioxide (S ⁇ O )
  • SiO silicon dioxide
  • oxide/nit ⁇ de/oxide composites sometimes referred to as an ONO structure
  • Multilevel storage (often referred to as multilevel cells) means that a single cell can represent more than one bit of data
  • a single cell can represent more than one bit of data
  • conventional memory cell design only one bit has been represented by two different voltage levels, such as 0V and 5 V (in association with some voltage margin), which represent 0 or 1
  • 0V and 5 V in association with some voltage margin
  • multilevel storage more voltage ranges/current ranges are necessary to encode the multiple bits of data
  • the multiple ranges lead to reduced margins between ranges and require advanced design techniques
  • multilevel storage cells are difficult to design and manufacture Some exhibit poor reliability Some have slower read times than convention single-bit cells
  • the present application discloses a non-volatile semiconductor memory device for storing two-bits of information
  • the device has a semiconductor substrate of one conductivity type and right and left diffusion regions formed in the semiconductor substrate of the opposite conductivity type A channel region is formed between the left and right diffusion regions A control gate having a thin gate oxide film is formed over a center channel portion of the channel region
  • the device further includes a control gate electrode formed on the gate insulating film A dielectric composite substantially overlays the semiconductor substrate and the control gate electrode
  • a right charge storage region is formed within a portion of the dielect ⁇ c composite between the control gate electrode and right diffusion region
  • a left charge storage region is formed within a portion of the dielect ⁇ c composite between the control gate electrode and left diffusion region
  • a word ne substantially overlays the dielect ⁇ c composite
  • the present invention also includes a method for fabricating this novel memory cell which involves (1) forming a gate oxide insulating layer on a conductivity-type semiconductor substrate, (2) forming a control gate on the gate oxide insulating layer, (3) applying a right spacer and a left spacer adjacent right and left edges of the control gate so as to cover portions of the gate oxide insulating layer, (4) forming left and right diffusion regions within the semiconductor substrate, (5) removing the spacers, and (6) forming a dielectric composite positioned on the control gate and the semiconductor substrate, the dielectric composite including a bottom layer of silicon dioxide formed on the substrate and the control gate, a layer of silicon nitride formed on the bottom silicon dioxide layer, and a top layer of silicon dioxide formed on the nitride layer
  • Fig 1 is a cross-sectional view-taken along the wordhne-of the twin-bit nonvolatile memory cell according to the present invention
  • Fig 2 is a plan view of the layout of a segment of the cell according to the present invention
  • Figs 3 A — 3D are cross-sectional views-taken along the wordhne-of the various steps performed in a method for fabricating a twin-bit non-volatile memory cell according to the present invention
  • Fig 3E is a plan view of the pattern of the second layer of polysihcon deposited after the step illustrated in Fig 3D in the method of manufacturing a memory cell,
  • Fig 3F is a cross-sectional view-taken along the wordhne-illustrating the cell manufactured according to the steps illustrated in Figs 3A — 3E,
  • Fig 4A is a cross-sectional view-taken along the wordhne-illustrating the operation of the split floating gate to store charge in the right charge storage region
  • Fig 4B is a cross-sectional view-taken along the wordhne-illustrating the operation of the split floating gate to store charge in the left charge storage region
  • Fig 5 is a graphical depiction of the effect of reversing the directionality of the program and read steps on the threshold voltages exhibited by the twin-bit non-volatile cell structure of the present invention.
  • Fig 6 is a graphical depiction of the relationship between programming speed and thickness of the gate oxide
  • Fig 1 shows the twin-bit non-volatile memory structure or cell 100 according to the present invention
  • Memory structure 100 is based on a semiconductor substrate 102
  • semiconductor substrate 102 can be doped to form a p-type or n- type substrate
  • the present invention is equally applicable to a cell based on an n-type semiconductor substrate with adjustments that would be similarly understood
  • Right diffusion region or channel 104 is formed in semiconductor substrate 102 and has a conductivity type opposite to the conductivity type of substrate 102
  • Left diffusion region or channel 106 is fashioned in semiconductor substrate 102 apart from right diffusion region 104 thus forming channel region 108 between right and left diffusion regions 104, 106, with left diffusion region 106 having the same conductivity type as region 104 (n+ in the disclosed embodiment)
  • Cell 100 further comprises gate insulating film layer 1 10 (gate oxide layer) formed on center channel portion 112 of channel region 108
  • Control gate electrode 1 14 is created on layer 110 using polysihcon
  • control gate 114 also functions to insulate the left and right memory "cells" from one another
  • Thin (tunneling) oxide layer 120, nitride layer 122, and insulating oxide layer 124 are uniformly layered as over substrate 102 and control gate 1 14 as illustrated in Fig 1 to form an ONO dielectric composite layer 132
  • oxide layers 120 and 124 are each approximately 100 angstroms thick whereas the nitride layer is approximately 50 angstroms thick
  • these dielectric structures have been illustrated as being formed by sandwiching a nitride layer between a thin tunneling oxide and insulating oxide, other dielectric structures could be used instead, such as S ⁇ O 2 /Al 2 O 3 /S ⁇ O 2
  • Right charge storage region 116 is formed on a right portion 118 of channel region 108 between center channel portion 1 12 and right diffusion region 104
  • Left charge storage region 126 is created on a left portion 128 of channel region 108 between center channel portion 112 and left diffusion region 106
  • Right and left regions 1 16, 126 are capable of storing one-bit of data each Polysihcon
  • diffusion regions 104, 106 in a MOS transistor are indistinguishable in a zero-bias state, the role of each diffusion region is defined after terminal voltages are applied (1 e , the drain is biased higher than the source)
  • Figs 4 A and 4B show the operation principle of the twin-bit non-volatile memory structure of the present invention
  • twin-bit non-volatile memory cell 100 one-bit of data is stored and localized at each of charge storage regions 116 and 126
  • reversing the program and read directions of the cell interference between the charge storage at each of the two charge storage regions can be avoided
  • Fig 4A illustrates the programming and reading of the right bit
  • right diffusion region 104 is treated as the drain (by applying a voltage of about 4-6V) and left diffusion region 106 is treated as the source (by applying 0V or low voltage for hot-e program)
  • about 3 to 5 volts are applied to control gate electrode 1 14 to activate center channel portion 112
  • wordhne 130 receives about 8 to 10 volts
  • left diffusion region 106 is treated as drain (by applying a voltage of about 1 5-2 5 V) and right diffusion region 104 is treated as the source (by applying a voltage of 0V)
  • about 2 to 4 volts are applied to control gate 1 14 and wordhne 130 to activate center channel 1 12
  • similar operations would be used to program and read left storage cell 126
  • Fig 5 shows the Vt difference when trapped electrons are localized on the right side, indicating that right diffusion region 104 is used as a drain during programming
  • Line 1 is the threshold voltage read from the right side (right diffusion channel 104 is used as the drain and it is in the same direction as the program)
  • line 2 is the threshold voltage read from the left side (left diffusion channel 106 is used as a drain and it is in the reverse direction of the program)
  • reversing the program and read directions results in more efficient Vt behavior Therefore, even if both sides are programmed to store two bits, the threshold voltage of the single bit is read By reversing the direction in this way, two bits can be programmed and read without interfering with each other Erasing the two-bit storage can be executed one bit or two bits at a time If high voltage is applied at both diffusion terminals corresponding with zero or negative gate voltage, these two bits will be erased together
  • Arsenic 70 KeV/1 5* 10 ⁇ 15
  • Arsenic 70 KeV/1 5* 10 ⁇ 15
  • the oxide spacer is then removed and ONO (oxide/nitride/oxide) is deposited on the tunneling oxide as illustrated in Fig. 3D in a manner well known in the art to a thickness of 100/50/100 Angstroms.
  • the ONO composite 132 includes a bottom silicon dioxide layer 120 which is sufficiently thick to prevent hot electrons from traversing the layer and becoming trapped at the interface between the top silicon dioxide layer 124 and the silicon nitride layer 122.
  • the minimum required thickness for layer 120 depends on the integrity of the bottom oxide layer and the ability of the bottom oxide layer to conform to the topology of the underlying poly substrate 102 to provide a bottom oxide layer with a uniform thickness. Whether the bottom oxide layer possesses these features depends on the method by which the bottom oxide layer is formed.
  • the bottom oxide layer 120 may be deposited on substrate 102 by a variety of methods known in the art including, for example, thermal growth in an O 2 ambient environment, thermal growth in an N O ambient environment, low temperature chemical vapor deposition (CVD) (400° C) and high temperature CVD (800° -1000° C). It is preferred that the bottom silicon dioxide layer 120 be deposited by high temperature
  • the silicon nitride layer 122 used in the ONO composite of the present invention should be thinner that either the bottom 120 or top 124 oxide layers in the resulting composite.
  • Second polysihcon layer 130 is then deposited over layer 124 using CVD, and the word line mask is employed to pattern the polysihcon as shown in Figs. 3E — 3F.

Abstract

The present application discloses a non-volatile semiconductor memory device (100) for storing two-bits of information. The device has a semiconductor substrate (102) of one conductivity type and right (104) and left (106) diffusion regions formed in the semiconductor substrate of the opposite conductivity type. A channel region (108) is formed between the left and right diffusion regions. A control gate (114) having a thin gate oxide film (110) is formed over a center channel portion (112) of the channel region. The device further includes a control gate electrode formed on the gate insulating film. A dielectric composite (132) substantially overlays the semiconductor substrate and the control gate electrode. A right charge storage region is formed within a portion of the dielectric composite between the control gate electrode and right diffusion region. Similarly, a left charge storage region is formed within a portion of the dielectric composite between the control gate electrode and left diffusion region. A wordline (130 ) substantially overlays the dielectric composite. A method of fabricating this novel cell is also disclosed.

Description

EASY SHRINKABLE NOVEL NON VOLATILE SEMICONDUCTOR
MEMORY CELL UTILIZING SPLIT DIELECTRIC FLOATING
GATE AND METHOD FOR MAKING SAME
Background of the Invention
1 Field of the Invention
The present invention relates in general to non-volatile digital memories and, more particularly, to an improved cell structure for a programmable non-volatile memory (such as conventional EEPROM or Flash EEPROM) that stores two-bits of information and methods for fabricating same
2 Background Art
Non-volatile memory devices, such as EPROM, EEPROM, and flash EPROM devices, generally include a series of transistors which act as memory cells for storing a single-bit of information Each transistor has source and drain regions formed on a n- or p-type semiconductor substrate, a thin tunnel dielectric layer formed on the surface of the semiconductor substrate positioned between the source and drain regions, a floating gate (formed of polysihcon) positioned on the insulating layer for holding a charge, a control gate and an interpoly dielectric positioned between the floating gate and control gate
The most commonly used EPROM cell has an electrically floating gate which is surrounded by insulation and generally disposed between a source and drain region formed in a silicon substrate In earlier versions of these cells, charge is injected through the insulation by avalanche injection Later versions of EPROMs relied on channel injection for charging the floating gate Exposing the array to ultraviolet radiation erases these EPROMs
Electrically erasable EPROMs (EEPROMs) are also very common In some cases, charge is place into and removed from a floating gate by tunneling the charge through a thin oxide region formed on the substrate In the other instances, charge is removed through an upper electrode
Another type of common EPROM/EEPROM is referred to as Flash EPROM or Flash EEPROM These flash memory cells have the capability of electrically erasing, programming or reading a memory cell in the chip The floating gate used therein is a conductive material, typically made of polysihcon, which is insulated from the channel of the transistor by a thin layer of oxide or other insulating material, and insulated from the control gate or word line of the transistor by a second layer of insulating material
The "program" step for a flash memory cell is accomplished through so-called hot electron injection by establishing a large positive voltage between the gate and source, as much as twelve volts, and a positive voltage between the drain and source, for instance, seven volts
The act of discharging the floating gate is called the "erase" function for a flash device This erase function is typically carried out by an F-N tunneling mechanism between the floating gate and the source of the transistor (source erase) or between the floating gate and the substrate (channel erase) For instance, a source erase operation is induced by establishing a large positive voltage from the source to gate, while floating the drain of the respective memory cell This positive voltage can be as much as twelve volts
In conventional stacked non-volatile semiconductor memory devices, an insulating film (hereafter "second gate insulating film") for insulating a floating gate and control gate from each other is a single layer of silicon oxide There is an ever- increasing need for miniaturized semiconductor devices, and in this situation the thickness of the second gate insulating film is required to further decrease
Traditionally, the interpoly dielectric had consisted of a single layer of silicon dioxide (SιO ) To meet this requirement, more recently oxide/nitπde/oxide composites (sometimes referred to as an ONO structure) have been used in place of the silicon dioxide because they are thinner and still exhibit decreased charge leakage over the single oxide laver (see Chang et al U S Patent No 5,619,052)
U S Patent No 5,768, 192 to Eitan discloses that ONO structures (as well as other charge trapping dielectrics) have been used as both insulator and floating gate Eitan teaches that by programming and reading this transistor device in opposite directions (I e reversing "source" and "drain") shorter programming times still result in a high increase in exhibited threshold voltage Eitan suggests that this result is useful in reducing programming time while still preventing "punch through" (1 e a condition where the lateral electric field is strong enough to draw electrons through to the drain, regardless of the applied threshold level)
The semiconductor memory industry has been researching various techniques and approaches to lower the bit cost of non- volatile memory Two of the more important approaches are dimensional shrinking and multilevel storage
Dimensional shrinking is the attempt to design cells using smaller dimensions However, substantial improvements in technology will be necessary before dimensional shrinking reaches its full potential cost savings Multilevel storage (often referred to as multilevel cells) means that a single cell can represent more than one bit of data In conventional memory cell design, only one bit has been represented by two different voltage levels, such as 0V and 5 V (in association with some voltage margin), which represent 0 or 1 In multilevel storage more voltage ranges/current ranges are necessary to encode the multiple bits of data The multiple ranges lead to reduced margins between ranges and require advanced design techniques As a result, multilevel storage cells are difficult to design and manufacture Some exhibit poor reliability Some have slower read times than convention single-bit cells
Accordingly, it is an object of the present invention to produce a non- volatile memory structure that achieves cost-savings by providing a structure capable of storing two bits of data, thus doubling the size of the non-volatile memory It is an associated object of the present invention for this cell structure to operate without the use of reduced margins or advanced design techniques
It is another object of the present invention to produce a cell configuration significantly simpler in design that conventional EEPROM or Flash EEPROM by employing a dielectric floating gate It is an associated object of the present invention to provide a cell structure having a gate coupling ratio (GCR) of 100% thus permitting the use of lower voltages for both programming and erase functions than conventional EEPROM or Flash EEPROM cells while concomitantly having a read current that is significantly higher than EEPROM or Flash EEPROM It is an additional object of the present invention to provide a process to manufacture a two-bit memory cell which can be easily adapted to a system on a chip (SOC) application
These and other objects will be apparent to those of ordinary skill in the art having the present drawings, specification and claims before them Summary of the Disclosure
The present application discloses a non-volatile semiconductor memory device for storing two-bits of information The device has a semiconductor substrate of one conductivity type and right and left diffusion regions formed in the semiconductor substrate of the opposite conductivity type A channel region is formed between the left and right diffusion regions A control gate having a thin gate oxide film is formed over a center channel portion of the channel region The device further includes a control gate electrode formed on the gate insulating film A dielectric composite substantially overlays the semiconductor substrate and the control gate electrode A right charge storage region is formed within a portion of the dielectπc composite between the control gate electrode and right diffusion region Similarly, a left charge storage region is formed within a portion of the dielectπc composite between the control gate electrode and left diffusion region A word ne substantially overlays the dielectπc composite
The present invention also includes a method for fabricating this novel memory cell which involves (1) forming a gate oxide insulating layer on a conductivity-type semiconductor substrate, (2) forming a control gate on the gate oxide insulating layer, (3) applying a right spacer and a left spacer adjacent right and left edges of the control gate so as to cover portions of the gate oxide insulating layer, (4) forming left and right diffusion regions within the semiconductor substrate, (5) removing the spacers, and (6) forming a dielectric composite positioned on the control gate and the semiconductor substrate, the dielectric composite including a bottom layer of silicon dioxide formed on the substrate and the control gate, a layer of silicon nitride formed on the bottom silicon dioxide layer, and a top layer of silicon dioxide formed on the nitride layer
Brief Description of the Drawings
Fig 1 is a cross-sectional view-taken along the wordhne-of the twin-bit nonvolatile memory cell according to the present invention, Fig 2 is a plan view of the layout of a segment of the cell according to the present invention,
Figs 3 A — 3D are cross-sectional views-taken along the wordhne-of the various steps performed in a method for fabricating a twin-bit non-volatile memory cell according to the present invention,
Fig 3E is a plan view of the pattern of the second layer of polysihcon deposited after the step illustrated in Fig 3D in the method of manufacturing a memory cell,
Fig 3F is a cross-sectional view-taken along the wordhne-illustrating the cell manufactured according to the steps illustrated in Figs 3A — 3E,
Fig 4A is a cross-sectional view-taken along the wordhne-illustrating the operation of the split floating gate to store charge in the right charge storage region,
Fig 4B is a cross-sectional view-taken along the wordhne-illustrating the operation of the split floating gate to store charge in the left charge storage region,
Fig 5 is a graphical depiction of the effect of reversing the directionality of the program and read steps on the threshold voltages exhibited by the twin-bit non-volatile cell structure of the present invention, and
Fig 6 is a graphical depiction of the relationship between programming speed and thickness of the gate oxide
Best Modes of Carrying Out the Invention
While the present invention may be embodied in many different forms and produced by various different fabrication processes, there is shown in the drawings and discussed herein one specific embodiment and specific fabrication method with the understanding that the present disclosure is to be considered only as an exemplification of the principles of the invention and is not intended to limit the invention to the embodiments illustrated
Fig 1 shows the twin-bit non-volatile memory structure or cell 100 according to the present invention Memory structure 100 is based on a semiconductor substrate 102 As known, in the art, semiconductor substrate 102 can be doped to form a p-type or n- type substrate For purposes of the present explanation of the properties of the present invention, reference shall be made solely to a cell based on a p-type semiconductor substrate However, as would be understood by those skilled in the art, the present invention is equally applicable to a cell based on an n-type semiconductor substrate with adjustments that would be similarly understood
Right diffusion region or channel 104 is formed in semiconductor substrate 102 and has a conductivity type opposite to the conductivity type of substrate 102 Left diffusion region or channel 106 is fashioned in semiconductor substrate 102 apart from right diffusion region 104 thus forming channel region 108 between right and left diffusion regions 104, 106, with left diffusion region 106 having the same conductivity type as region 104 (n+ in the disclosed embodiment)
Cell 100 further comprises gate insulating film layer 1 10 (gate oxide layer) formed on center channel portion 112 of channel region 108 Control gate electrode 1 14 is created on layer 110 using polysihcon As detailed below, control gate 114 also functions to insulate the left and right memory "cells" from one another
Thin (tunneling) oxide layer 120, nitride layer 122, and insulating oxide layer 124 are uniformly layered as over substrate 102 and control gate 1 14 as illustrated in Fig 1 to form an ONO dielectric composite layer 132 In a preferred embodiment, oxide layers 120 and 124 are each approximately 100 angstroms thick whereas the nitride layer is approximately 50 angstroms thick Although these dielectric structures have been illustrated as being formed by sandwiching a nitride layer between a thin tunneling oxide and insulating oxide, other dielectric structures could be used instead, such as SιO2/Al2O3/SιO2 Right charge storage region 116 is formed on a right portion 118 of channel region 108 between center channel portion 1 12 and right diffusion region 104 Left charge storage region 126 is created on a left portion 128 of channel region 108 between center channel portion 112 and left diffusion region 106 Right and left regions 1 16, 126 are capable of storing one-bit of data each Polysihcon 130 is used as the wordhne and substantially overlays ONO dielectric composite layer 132
As is known by those of ordinary skill in the art, diffusion regions 104, 106 in a MOS transistor are indistinguishable in a zero-bias state, the role of each diffusion region is defined after terminal voltages are applied (1 e , the drain is biased higher than the source)
Compared to conventional EEPROM or Flash EEPROM, the process is much simpler because the floating gate is unnecessary Therefore, the cost is reduced greatly by double density and simple process
Figs 4 A and 4B show the operation principle of the twin-bit non-volatile memory structure of the present invention As noted above, in twin-bit non-volatile memory cell 100 one-bit of data is stored and localized at each of charge storage regions 116 and 126 As will be explained below, by reversing the program and read directions of the cell, interference between the charge storage at each of the two charge storage regions can be avoided
Fig 4A illustrates the programming and reading of the right bit To program the right bit, right diffusion region 104 is treated as the drain (by applying a voltage of about 4-6V) and left diffusion region 106 is treated as the source (by applying 0V or low voltage for hot-e program) Concurrently, about 3 to 5 volts are applied to control gate electrode 1 14 to activate center channel portion 112, wordhne 130 receives about 8 to 10 volts To read that right bit, left diffusion region 106 is treated as drain (by applying a voltage of about 1 5-2 5 V) and right diffusion region 104 is treated as the source (by applying a voltage of 0V) Simultaneously, about 2 to 4 volts are applied to control gate 1 14 and wordhne 130 to activate center channel 1 12 As depicted by Fig 4B, similar operations would be used to program and read left storage cell 126
The reason for reversing the program and the read directions is that localized trapped electrons exhibit different threshold voltages if read in different directions Fig 5 shows the Vt difference when trapped electrons are localized on the right side, indicating that right diffusion region 104 is used as a drain during programming Line 1 is the threshold voltage read from the right side (right diffusion channel 104 is used as the drain and it is in the same direction as the program), and line 2 is the threshold voltage read from the left side (left diffusion channel 106 is used as a drain and it is in the reverse direction of the program) As illustrated in Fig 5, reversing the program and read directions results in more efficient Vt behavior Therefore, even if both sides are programmed to store two bits, the threshold voltage of the single bit is read By reversing the direction in this way, two bits can be programmed and read without interfering with each other Erasing the two-bit storage can be executed one bit or two bits at a time If high voltage is applied at both diffusion terminals corresponding with zero or negative gate voltage, these two bits will be erased together If high voltage is applied only at a single diffusion terminal corresponding with zero or negative gate voltage, only a single bit is erased Additionally, no over-erase occurs in this structure because of central gate oxide layer 110 Even if the threshold voltages of storage regions 116, 126 are over-erased, the real threshold is determined by the region of central gate oxide 110 Therefore, the erased- Vt of structure 100 is exceptional and, thus, is suitable for low power applications In addition to twin bits storage and the simple operating principle, the GCR (gate coupling ratio) of the invention is 100% because there is no floating gate The performance is greatly enhanced by enlarging the read current Further, the circuit and process overhead is reduced because the program and erase voltages are lowered Another advantage of this structure is the fast programming speed Fig 5 shows the programmed Vt versus programming time for two different central gate oxide 110 thicknesses The fast programming speed can be achieved by employing a thinner central gate oxide 110 layer In a preferred embodiment, the thickness of thinner central gate oxide 110 is about 50 to 100 Angstroms depending on the power supply voltage and cell dimensions There are various possible methods for fabricating the twin-bit cell of the present invention In particular, one preferred process has been disclosed hereinbelow with the understanding that these processes merely exemplify the potential processes by which the twin-bit non-volatile memory structure of the present invention can be fabricated As illustrated in Fig 1, gate oxide film 110 is formed on the surface of p-type silicon substrate 102 by the combination of oxidation at 800° C in an H2/O2 atmosphere and oxynitπzidation at 950° C in an N2O atmosphere After Vt adjustment and gate oxide growth, a bit line mask is used to pattern the polysihcon layer 1 14 as illustrated in Fig 3 A The oxide spacer is next formed as illustrated in Fig 3B by depositing a layer of TEOS and then etching the deposited TEOS back to the desired width to form a spacer
As illustrated in Fig 3C, Arsenic (70 KeV/1 5* 10Λ15) is implanted into the exposed element regions of substrate 102, followed by a rapid thermal process to activate the implanted atoms, forming right diffusion region 104 and left diffusion region 106 The oxide spacer is then removed and ONO (oxide/nitride/oxide) is deposited on the tunneling oxide as illustrated in Fig. 3D in a manner well known in the art to a thickness of 100/50/100 Angstroms. The ONO composite 132 includes a bottom silicon dioxide layer 120 which is sufficiently thick to prevent hot electrons from traversing the layer and becoming trapped at the interface between the top silicon dioxide layer 124 and the silicon nitride layer 122. The minimum required thickness for layer 120 depends on the integrity of the bottom oxide layer and the ability of the bottom oxide layer to conform to the topology of the underlying poly substrate 102 to provide a bottom oxide layer with a uniform thickness. Whether the bottom oxide layer possesses these features depends on the method by which the bottom oxide layer is formed.
The bottom oxide layer 120 may be deposited on substrate 102 by a variety of methods known in the art including, for example, thermal growth in an O2 ambient environment, thermal growth in an N O ambient environment, low temperature chemical vapor deposition (CVD) (400° C) and high temperature CVD (800° -1000° C). It is preferred that the bottom silicon dioxide layer 120 be deposited by high temperature
CVD which produces an oxide film with a low concentration of defects which conforms to the surface of the underlying substrate 102.
The silicon nitride layer 122 used in the ONO composite of the present invention should be thinner that either the bottom 120 or top 124 oxide layers in the resulting composite.
Second polysihcon layer 130 is then deposited over layer 124 using CVD, and the word line mask is employed to pattern the polysihcon as shown in Figs. 3E — 3F.
The foregoing description and drawings merely explain and illustrate the invention and the invention is not limited thereto. Those of the skill in the art who have the disclosure before them will be able to make modifications and variations therein without departing from the scope of the present invention.

Claims

WHAT IS CLAIMED IS
1 A non-volatile semiconductor memory device comprising a semiconductor substrate of one conductivity type, a right diffusion region formed in said semiconductor substrate, said right diffusion region having a conductivity type opposite to the conductivity type of said semiconductor substrate, a left diffusion region formed in said semiconductor substrate apart from said right diffusion region thus forming a channel region between said right and left diffusion regions, said left diffusion region having the same conductivity type as said right diffusion region, a gate insulating film formed on a center channel portion of said channel region, a control gate electrode formed on said gate insulating film, a dielectric composite substantially overlaying the substrate and the control gate electrode, a right charge storage region within a portion of said dielectric composite between said control gate electrode and said right diffusion region, a left charge storage region within a portion of said dielectric composite between said control gate electrode and said left diffusion region, and, - a wordline substantially overlaying the dielectric composite
2 The non- volatile semiconductor memory device of Claim 1 wherein said dielectric composite comprises a Silicon nitride layer sandwiched between two silicon dioxide layers
3 The non-volatile semiconductor memory device of Claim 1 wherein said dielectric composite comprises an Aluminum oxide layer sandwiched between two silicon dioxide layers
4 A method for manufacturing a non-volatile memory cell, comprising
forming a gate oxide insulating layer on a conductivity-type semiconductor substrate, - forming a control gate on said gate oxide insulating layer, applying a right spacer and a left spacer adjacent right and left edges of said control gate so as to cover portions of said gate oxide insulating layer; forming left and right diffusion regions within the semiconductor substrate; removing the spacers; and forming a dielectric composite positioned on said control gate and the semiconductor substrate, the dielectric composite including a bottom layer of silicon dioxide formed on said substrate and said control gate; a layer of silicon nitride formed on said bottom silicon dioxide layer, and a top layer of silicon dioxide formed on said nitride layer.
PCT/US2000/023504 1999-08-27 2000-08-25 Easy shrinkable novel non-volatile semiconductor memory cell utilizing split dielectric floating gate and method for making same WO2001017031A1 (en)

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AU6940900A (en) 2001-03-26
CN1375114A (en) 2002-10-16

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