JPH05145080A - Nonvolatile storage device - Google Patents

Abstract

PURPOSE:To provide the title nonvolatile storage device having even and stable storage characteristics attaining the high integration. CONSTITUTION:The title nonvolatile storage device is composed of a structure wherein memory gate electrode 7 are provided on a pair of multiple gate insulating films 6 independently formed on a channel region of a semiconductor substrate 1 while an address gate electrode 9 is formed at least on a part between the memory gata electrode 7 and on the same through the intermediary of an insulating film 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile memory device, and more particularly to a non-volatile memory device which achieves high integration and has uniform and stable memory characteristics.

[0002]

2. Description of the Related Art Conventionally, as a general nonvolatile memory device, for example, an MNOS (Metal Nitride) is used.
Oxide Semiconductor type, MO
NOS (Metal Oxide Nitride O
Xide Semiconductor) type and the like are known.

In the memory cell of the non-volatile memory device,
Normally, between the gate oxide film and the polycrystalline silicon gate,
NMOS (n-type-MetalO) having a silicon nitride film
A xide semiconductor (transistor) transistor is used. In such a memory cell, an ordinary memory gate (gate of a storage device) exhibits enhancement-type characteristics after writing and depletion-type characteristics after erasing. Therefore, in order to prevent the channel region from being short-circuited when the memory cell in the erased state is not read, the non-volatile memory device is configured such that the 1-bit cell has a memory gate and an address gate having an enhancement type characteristic (when the memory device is selected, Only a gate to form a channel that allows drain current to pass)
, That is, a structure in which one storage device is substantially composed of two transistors.

[0004]

However, since the non-volatile memory device has a structure in which two transistors form one memory device, the area per bit becomes large and the device can be miniaturized. There was a problem that I could not. Therefore, in order to solve this problem, a memory cell is configured by two memory gates and one address gate, and the memory gate and the address gate are overlapped to store two bits in one cell. Non-volatile devices that reduce the area per bit are known.

However, in this conventional example, while the area per bit can be reduced, since the memory gate overlaps a part of the address gate, the memory area length with respect to the memory gate length becomes small. There is. Therefore, the effective memory area is small,
There was a problem that the memory operation became unstable. on the other hand,
In order to obtain a stable memory operation, the substantial memory area must be expanded, that is, the memory gate length must be increased, which poses a problem of impeding high integration. Further, the technique of overlapping the memory gate and the address gate has a problem in that the photo-process is complicated, so that an alignment error occurs, the memory region length easily varies, and the memory operation becomes unstable. .. There is also a problem that the cost is increased.

An object of the present invention is to solve such a problem, and it is an object of the present invention to provide a nonvolatile memory device which achieves high integration and has uniform and stable memory characteristics. ..

[0007]

In order to achieve this object, the present invention provides a memory gate electrode on a pair of multi-layered gate insulating films independently formed on a channel region of a semiconductor substrate, and the memory concerned. The present invention provides a non-volatile memory device characterized in that an address gate electrode is formed between gate electrodes and at least a part of the memory gate electrode via an insulating film.

[0008]

Since the nonvolatile memory device according to the present invention has a structure in which the address gate electrodes are formed between the memory gate electrodes and at least a part of the memory gate electrodes, the memory gate length becomes the memory region length directly. .. Therefore, the memory area can be maximized with respect to the area per bit, and the memory operation becomes stable. Therefore, even if the area per bit is smaller than the area of the conventional nonvolatile memory device, a stable memory operation similar to that of the conventional nonvolatile memory device can be ensured. Therefore, high integration is possible. Further, since the memory gate is formed below the address gate (on the side of the semiconductor substrate), it is not affected by the alignment error in the photo process unlike the conventional case. Therefore, the dimensional accuracy of the memory region can be improved, and the nonvolatile memory device has uniform and stable memory characteristics.

[0009]

Embodiments of the present invention will now be described with reference to the drawings. 1 to 4 are partial cross-sectional views showing a manufacturing process of a nonvolatile memory device (MONOS type) according to an embodiment of the present invention. In the step shown in FIG. 1, after a silicon oxide film 2 having a film thickness of about 20 Å is deposited on a p-type semiconductor substrate 1 by a known method, 70 to 150
Deposit silicon nitride film 3 with a thickness of about Å, and
A silicon oxide film 4 is deposited with a film thickness of about 0 to 80Å.
After that, 3000 to 500 are formed on the silicon oxide film 4.
A polycrystalline silicon film 5 is deposited with a film thickness of about 0Å.

Next, in the step shown in FIG. 2, the semiconductor substrate 1 obtained in the step shown in FIG. 1 is patterned to form a polycrystalline silicon film 5, a silicon oxide film 4, and a silicon nitride film 3.
And a silicon oxide film 2
Are selectively etched. In this way, two independent (a pair) memory gate electrodes 7 are formed on the semiconductor substrate 1.
Are formed through the multi-layer gate insulating film 6. In this way, the memory gate electrode 7 can be formed without performing the conventional complicated photo process, so that the dimensional accuracy of the memory region can be improved.

Next, in the step shown in FIG. 3, gate oxidation is performed on the semiconductor substrate 1 obtained in the step shown in FIG.
The insulating film 8 is deposited to a film thickness of about this. At this time, the thickness of the insulating film 8 deposited on the memory gate electrode 7 is 300 to 80.
It will be about 0Å. Next, polycrystalline silicon is deposited on the insulating film 8 to a film thickness of about 3000 to 5000 Å, and then patterned to selectively etch the polycrystalline silicon film to form the address gate electrode 9. Here, the patterning for forming the address gate electrode 9 is
The address gate electrode 9 is formed so as to overlap from one of the two memory gate electrodes 7 to the other. In this way, the address gate electrodes 9 were formed between the memory gate electrodes 7 and at least a part of the memory gate electrodes 7. The nonvolatile memory device having this structure has a memory area extremely larger than that of the conventional nonvolatile memory device.

Next, in the step shown in FIG. 4, a known semiconductor substrate 1 obtained in the step shown in FIG. 3 is formed so that the two memory gates 7 and the address gate electrodes 11 are formed on the channel region. Source 10 and drain 11 depending on the method
To form. After that, wiring and the like are formed by a normal process to complete the nonvolatile memory device. In this example,
Although the n-type memory cell is formed on the p-type semiconductor substrate, the present invention is not limited to this, and it goes without saying that an n-type semiconductor substrate may be used.

Although the MONOS type non-volatile memory device has been described in the present embodiment, the present invention is not limited to this.
Even when applied to an OS type non-volatile memory device or the like, the same effect can be obtained.

[0014]

As described above, according to the present invention,
Since the structure of the non-volatile memory device is such that the address gate electrodes are formed between the memory gate electrodes and at least a part of the memory gate electrodes, the memory gate length directly becomes the memory region length, resulting in an area per bit. It is possible to secure a stable memory operation even if is reduced.
Therefore, it is possible to provide a nonvolatile memory device which achieves high integration and has uniform and stable memory characteristics.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view showing a manufacturing process of a nonvolatile memory device according to an example of the invention.

FIG. 2 is a partial cross-sectional view showing the manufacturing process of the nonvolatile memory device according to the example of the invention.

FIG. 3 is a partial cross-sectional view showing the manufacturing process of the nonvolatile memory device according to the example of the invention.

FIG. 4 is a partial cross-sectional view showing the manufacturing process of the nonvolatile memory device according to the example of the invention.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Silicon Oxide Film 3 Silicon Nitride Film 4 Silicon Oxide Film 5 Polycrystalline Silicon Film 6 Multilayer Gate Insulation Film 7 Memory Gate Electrode 8 Insulation Film 9 Address Gate Electrode 10 Source 11 Drain

Claims (1)

[Claims] 1. A memory gate electrode is provided on a pair of multi-layer gate insulating films independently formed in a channel region of a semiconductor substrate, and an insulating film is provided between the memory gate electrodes and at least a part of the memory gate electrode. A non-volatile memory device characterized in that an address gate electrode is formed through the non-volatile memory device.