TW200419782A - Flash memory cell, manufacturing method of memory cell and operation method thereof - Google Patents

Flash memory cell, manufacturing method of memory cell and operation method thereof

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Publication number
TW200419782A
TW200419782A TW92106129A TW92106129A TW200419782A TW 200419782 A TW200419782 A TW 200419782A TW 92106129 A TW92106129 A TW 92106129A TW 92106129 A TW92106129 A TW 92106129A TW 200419782 A TW200419782 A TW 200419782A
Authority
TW
Taiwan
Prior art keywords
gate
memory cell
selecting
substrate
dielectric layer
Prior art date
Application number
TW92106129A
Other languages
Chinese (zh)
Other versions
TWI224858B (en
Inventor
Chih-Wei Hung
Cheng-Yuan Hsu
Chi-Shan Wu
Min-San Huang
Original Assignee
Powerchip Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powerchip Semiconductor Corp filed Critical Powerchip Semiconductor Corp
Priority to TW92106129A priority Critical patent/TWI224858B/en
Publication of TW200419782A publication Critical patent/TW200419782A/en
Application granted granted Critical
Publication of TWI224858B publication Critical patent/TWI224858B/en

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  • Non-Volatile Memory (AREA)

Abstract

A memory cell is consisted of a substrate, gate structure, source region, erasing gate, erasing gate dielectric layer, selecting gate, selecting gate dielectric layer and drain region. The gate structure comprised a tunneling oxide, a floating gate, an inter-gate dielectric layer, control gate and the spacer is set on the substrate. The source region is set in the substrate at one side of the gate structure. The erasing gate is set on the source region at one side of the gate structure. The erasing gate dielectric layer is set between the erasing gate and source region. The selecting gate is set at the other side of gate structure. The selecting gate dielectric layer is set between the selecting gate and the substrate. The drain region is set in the substrate at one side of the selecting gate.
TW92106129A 2003-03-20 2003-03-20 Flash memory cell, manufacturing method of memory cell and operation method thereof TWI224858B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW92106129A TWI224858B (en) 2003-03-20 2003-03-20 Flash memory cell, manufacturing method of memory cell and operation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW92106129A TWI224858B (en) 2003-03-20 2003-03-20 Flash memory cell, manufacturing method of memory cell and operation method thereof

Publications (2)

Publication Number Publication Date
TW200419782A true TW200419782A (en) 2004-10-01
TWI224858B TWI224858B (en) 2004-12-01

Family

ID=34568321

Family Applications (1)

Application Number Title Priority Date Filing Date
TW92106129A TWI224858B (en) 2003-03-20 2003-03-20 Flash memory cell, manufacturing method of memory cell and operation method thereof

Country Status (1)

Country Link
TW (1) TWI224858B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105633091A (en) * 2015-01-13 2016-06-01 北京芯盈速腾电子科技有限责任公司 Non-volatile memory unit and method for manufacturing the same
CN105931993A (en) * 2015-05-04 2016-09-07 北京芯盈速腾电子科技有限责任公司 Non-volatile Storage Unit And Manufacturing Method Thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105633091A (en) * 2015-01-13 2016-06-01 北京芯盈速腾电子科技有限责任公司 Non-volatile memory unit and method for manufacturing the same
CN105931993A (en) * 2015-05-04 2016-09-07 北京芯盈速腾电子科技有限责任公司 Non-volatile Storage Unit And Manufacturing Method Thereof
TWI594378B (en) * 2015-05-04 2017-08-01 北京芯盈速騰電子科技有限責任公司 Non-volatile memory cell and manufacture method of the same

Also Published As

Publication number Publication date
TWI224858B (en) 2004-12-01

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MM4A Annulment or lapse of patent due to non-payment of fees